- 13 Jan, 2020 1 commit
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Tvrtko Ursulin authored
We use PCI device path in the registered PMU name in order to distinguish between multiple GPUs. But since tools/perf reserves a special meaning to dash and colon characters we need to transliterate them to something else. We choose an underscore. v2: * Use strreplace. (Chris) * Dashes are not good either. (Chris) Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reported-by:
Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com> Fixes: 05488673 ("drm/i915/pmu: Support multiple GPUs") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200110113253.12535-1-tvrtko.ursulin@linux.intel.com
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- 11 Jan, 2020 5 commits
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Chris Wilson authored
A copy and paste error in setting up the !CONFIG_DRM_I915_CAPTURE_ERROR stubs left a conflicting duplicate declaration. Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200111083007.1619228-1-chris@chris-wilson.co.uk
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Michal Wajdeczko authored
uC sanitization is only meaningful if we are running with uC present or enabled. Make this function part of the uc_ops. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
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Michal Wajdeczko authored
uC preparation and cleanup steps are only meaningful if we are running with uC enabled. Make these functions part of the uc_ops. Signed-off-by:
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Michal Wajdeczko authored
Firmware fetching and cleanup steps are only meaningful if we are running with uC enabled. Make these functions part of the uc_ops. Signed-off-by:
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Michal Wajdeczko authored
Instead of spreading multiple conditionals across the uC code to find out current mode of uC operation, start using predefined set of function pointers that reflect that mode. Begin with pair of init_hw/fini_hw functions that are responsible for uC hardware initialization and cleanup. v2: drop ops_none, use macro to generate ops helpers v3: reuse __uc_check_hw to avoid redundant comment v4: forward declare ops struct vs functions Signed-off-by:
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- 10 Jan, 2020 14 commits
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Chris Wilson authored
We need to hold the runtime-pm wakeref to update the global PTEs (as they exist behind a PCI BAR). However, some systems invoke ACPI during runtime resume and so require allocations, which is verboten inside the vm->mutex. Ergo, we must not use intel_runtime_pm_get() inside the mutex, but lift the call outside. Closes: https://gitlab.freedesktop.org/drm/intel/issues/958Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200110144418.1415639-1-chris@chris-wilson.co.uk
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Vivek Kasireddy authored
Parsing the i2c element is mainly done to transfer the payload from the MIPI sequence block to the relevant slave device. In some cases, the commands that are part of the payload can be used to turn on the backlight. This patch is actually a refactored version of this old patch: https://lists.freedesktop.org/archives/intel-gfx/2014-December/056897.html In addition to the refactoring, the original patch is augmented by looking up the i2c bus from ACPI NS instead of relying on the bus number provided in the VBT. This patch was tested on Aava Mobile's Inari 10 tablet. It enabled turning on the backlight by transferring the payload to the device. v2: - Add DRM_DEV_ERROR for invalid adapter and failed transfer and also drop the DRM_DEBUG that existed originally. (Hans) - Add two gotos instead of one to clean things up properly. v3: - Identify the device on which this patch was tested in the commit message (Ville) Cc: Hans de Goede <hdegoede@redhat.com> Cc: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200110181123.14536-1-vivek.kasireddy@intel.com
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Chris Wilson authored
The list of requests from after the hang tells little about the hang itself, only how busy userspace was after the fact. As it pertains nothing to the HW state, drop it from the error state. Signed-off-by:
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Chris Wilson authored
The shadow ring regs (ring->head, ring->tail) are meaningless in the post-mortem dump as they do not related to anything on HW. Remove them from the coredump. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200110123059.1348712-3-chris@chris-wilson.co.uk
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Chris Wilson authored
While this is technically the batch as executed by the HW (in part at least), it is confusing, and only used for a minority of gen. Signed-off-by:
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Chris Wilson authored
In the near future, we will want to start a GPU error capture from a new context, from inside the softirq region of a forced preemption. To do so requires us to break up the monolithic error capture to provide new entry points with finer control; in particular focusing on one engine/gt, and being able to compose an error state from little pieces of HW capture. Signed-off-by:
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Chris Wilson authored
As we use the active state to keep the vma alive while we are reading its contents during GPU error capture, we need to mark the ring->vma as active during execution if we want to include the rinbuffer in the error state. Reported-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: b1e3177b ("drm/i915: Coordinate i915_active with its own mutex") Signed-off-by:
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Chris Wilson authored
As we use the active state to keep the vma alive while we are reading its contents during GPU error capture, we need to mark the context->state vma as active during execution if we want to include it in the error state. Reported-by:
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Chris Wilson authored
Currently we first to try to unbind the VMA (and lazily rebind on next use) as an optimisation during restore_ggtt_mappings. Ideally, the only objects in the GGTT upon resume are the pinned kernel objects which can't be unbound and need to be restored. As the unbind interferes with the plan to mark those objects as active for error capture, forgo the optimisation. Signed-off-by:
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Wambui Karuga authored
Convert to the use of new struct drm_device based logging macros to replace the use of the printk based macros in i915/intel_uncore.c Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7142083e727ab400797c8a90a2196ee37a22c201.1578409433.git.wambui.karugax@gmail.com
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Wambui Karuga authored
Replace the use of printk based debugging macros with the struct drm_device based logging macros in i915/intel_sideband.c. Signed-off-by:
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Wambui Karuga authored
Replace instances of printk based logging macros with the new struct drm_device logging macros in i915/intel_region_lmem.c. Signed-off-by:
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Wambui Karuga authored
This converts various instances of the struct device and printk based logging macros with the new struct drm_device based logging macros in i915/intel_pm.c Signed-off-by:
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Wambui Karuga authored
Convert the use of the DRM_DEBUG_KMS() logging macro to the new struct drm_device based drm_dbg_kms() logging macro in i915/intel_pch.c. Signed-off-by:
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- 09 Jan, 2020 17 commits
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Chen Zhou authored
Fix build error: drivers/gpu/drm/i915/gt/intel_ggtt.c: In function ggtt_restore_mappings: drivers/gpu/drm/i915/gt/intel_ggtt.c:1239:3: error: implicit declaration of function wbinvd_on_all_cpus; did you mean wrmsr_on_cpus? [-Werror=implicit-function-declaration] wbinvd_on_all_cpus(); ^~~~~~~~~~~~~~~~~~ wrmsr_on_cpus Reported-by:Hulk Robot <hulkci@huawei.com> Signed-off-by:
Chen Zhou <chenzhou10@huawei.com> Reviewed-by:
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Ville Syrjälä authored
I missed a few assert_pipe_disabled() cases when changing it to take enum transcoder instead of enum pipe, making sparse unhappy. Convert the leftovers. Reported-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200108145616.7349-1-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
When moving the pipe disable & co. function calls from haswell_crtc_disable() into the encoder .post_disable() hooks I neglected to account for the MST vs. DDI interactions properly. This now leads us to call these functions two times for the last MST stream (once from the MST code and a second time from the DDI code). The calls from the DDI code should only be done for SST and not MST. Add the proper check for that. This results in an MCE on ICL. My vague theory is that we turn off the transcoder clock from the MST code and then we proceed to touch something in the DDI code which still depends on that clock causing the hardware to become upset. Though I can't really explain why Stan's hack of omitting the pipe disable in the MST code would avoid the MCE since we should still be turning off the transcoder clock. But maybe there's something magic in the hw that keeps the clock on as long as the pipe is on. Or maybe the clock isn't the problem and we now touch something in the DDI disable code that really does need the pipe to be still enabled. v2: Rebase to latest drm-tip Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Reported-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/issues/901 Fixes: 773b4b54 ("drm/i915: Move stuff from haswell_crtc_disable() into encoder .post_disable()") Signed-off-by:
José Roberto de Souza <jose.souza@intel.com>
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Jani Nikula authored
Sync with drm-next to get the new logging macros, among other things. Signed-off-by: -
Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/i915/display/intel_crt.c:1066:1-28: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/display/intel_crt.c:928:2-29: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/display/intel_crt.c:443:2-29: WARNING: Assignment of 0/1 to bool variable Reported-by:
Ma Feng <mafeng.ma@huawei.com> Signed-off-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/i915/display/intel_dp.c:4950:1-33: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/display/intel_dp.c:4906:1-33: WARNING: Assignment of 0/1 to bool variable Reported-by:
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Ma Feng authored
Fixes coccicheck warning: drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to bool variable Reported-by:
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Chris Wilson authored
Now that we have moved the runtime-pm management out of intel_context_acctive_acquire, and that itself out of ce->ops->pin(), no explicit runtime pm wakeref is required in intel_context_pin(). Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200109085717.873326-3-chris@chris-wilson.co.uk
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Chris Wilson authored
While this is encroaching on midlayer territory, having already made the state allocation a previous step in pinning, we can now pull the common intel_context_active_acquire() into intel_context_pin() itself. This is a prelude to make the activation a separate step inside pinning, outside of the ce->pin_mutex Signed-off-by:
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Chris Wilson authored
Allow for knowledgeable users to preallocate the context state, and to separate the allocation step from the pinning step during intel_context_pin() Signed-off-by:
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Chris Wilson authored
Since we now allow the intel_context_unpin() to run unserialised, we risk our operations under the intel_context_lock_pinned() being run as the context is unpinned (and thus invalidating our state). We can atomically acquire the pin, testing to see if it is pinned in the process, thus ensuring that the state remains consistent during the course of the whole operation. Fixes: 84135022 ("drm/i915/gt: Drop mutex serialisation between context pin/unpin") Signed-off-by:
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Tvrtko Ursulin authored
This reverts commit 08fff7ae. For some yet unexplained reason not having this improves stability of some media workloads. Promise is that the media hang will be root caused properly and in the meantime absence of this workaround is unlikely to cause problems. Signed-off-by:
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Chris Wilson authored
Access through the GGTT (iomap) into the vma does require the device to be awake. However, we often take the i915_vma_pin_iomap() as an early preparatory step that is long before we use the iomap. Asserting that the device is awake at pin time does not protect us, and is merely a nuisance. Signed-off-by:
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Chris Wilson authored
If we have no fence and desire no fence on the vma, return before we try and take the vm->mutex. Signed-off-by:
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Chris Wilson authored
intel_timeline_enter() has been decoupled from intel_timeline_pin() and both enter/exit & pin/unpin are allowed [read expected] to run concurrently with one another. The assertion that they had better not is stale. Closes: https://gitlab.freedesktop.org/drm/intel/issues/940 References: a6edbca7 ("drm/i915/gt: Close race between engine_park and intel_gt_retire_requests") Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v5.6: UAPI Changes: - Allow overriding number of bootup penguins in fbcon using fbcon=logo-count:n. Cross-subsystem Changes: - fbdev fixes for mmp, and make it work with CONFIG_COMPILE_TEST. - Use devm_platform_ioremap_resource in fbdev drivers. - Various small fbdev fixes. Core Changes: - Support scanline alignment for dumb buffers. - Add atomic_check() hook to bridge ops, to support bus format negotiation. - Add gem_create_object() to vram helpers. Driver Changes: - Rockchip: Add support for PX30. - Use generic fbdev code and dumb helpers in hisilicon/hibmc. - Add support for Leadtek LTK500HD1829 panel, and xinpeng XPP055C272. - Clock fixes for atmel-hlcdc. - Various smaller fixes to all drivers. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8eff1e3f-ef0a-2dd9-9a14-6273b1d6f963@linux.intel.com
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Laurent Pinchart authored
The new helper drm_of_lvds_get_dual_link_pixel_order() introduced in commit 65290075 has a fallback stub when CONFIG_OF is not set, but the stub is declared in drm_of.h without a static inline. This causes multiple definitions of the function to be linked when the CONFIG_OF option isn't set. Fix it by making the stub static inline. Fixes: 65290075 ("drm: of: Add drm_of_lvds_get_dual_link_pixel_order") Reported-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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- 08 Jan, 2020 3 commits
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José Roberto de Souza authored
Capturing the restrictions of the BSpec pages bellow: SKL and CNL do not support MST in DDI E, DDI E only support 2 lanes and it is mostly used to support a 4 lanes eDP panel together with DDI A. ICL's DDI E support MST just like other ports but DDI A is still eDP and MIPI only. TGL supports MST in any DDI, including DDI A but TGL has it's own ddi_pre_enable_dp function already without any warning. [ 215.579791] ------------[ cut here ]------------ [ 215.579794] WARN_ON(is_mst && (port == PORT_A || port == PORT_E)) [ 215.579875] WARNING: CPU: 0 PID: 268 at drivers/gpu/drm/i915/display/intel_ddi.c:3576 intel_ddi_pre_enable+0x124/0xea0 [i915] [ 215.579878] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 btusb btrtl btbcm btintel bluetooth prime_numbers snd_hda_intel snd_intel_dspcfg snd_hda_codec e1000e snd_hwdep snd_hda_core asix mei_hdcp cdc_ether x86_pkg_temp_thermal mei_me snd_pcm r8152 coretemp usbnet mei crct10dif_pclmul mii ptp ecdh_generic crc32_pclmul i2c_i801 ecc pps_core ghash_clmulni_intel thunderbolt [ 215.579905] CPU: 0 PID: 268 Comm: kworker/0:2 Tainted: G W 5.4.0-rc8-zeh+ #1307 [ 215.579907] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3201.A00.1905140358 05/14/2019 [ 215.579912] Workqueue: events_long drm_dp_mst_link_probe_work [ 215.579975] RIP: 0010:intel_ddi_pre_enable+0x124/0xea0 [i915] [ 215.579978] Code: ff 8b 7c 24 10 89 44 24 30 85 ff 74 1f f7 44 24 18 fb ff ff ff 75 15 48 c7 c6 98 fa 48 a0 48 c7 c7 d3 df 4a a0 e8 cf d5 d0 e0 <0f> 0b 0f b6 4c 24 2c 41 8b b5 04 06 00 00 4c 89 e7 41 0f b6 95 0c [ 215.579980] RSP: 0018:ffffc90001a5f990 EFLAGS: 00010286 [ 215.579984] RAX: 0000000000000000 RBX: ffff88848356a000 RCX: 0000000000000000 [ 215.579986] RDX: 0000000000001df1 RSI: ffff88849340c998 RDI: ffffffff821489c5 [ 215.579989] RBP: ffff88848356a000 R08: 00000000c021a419 R09: 0000000000000000 [ 215.579991] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848356a118 [ 215.579994] R13: ffff88847f39c000 R14: ffff88847fe70000 R15: ffff88848356a000 [ 215.579996] FS: 0000000000000000(0000) GS:ffff88849f800000(0000) knlGS:0000000000000000 [ 215.579999] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 215.580001] CR2: 000055d3d5a26bc0 CR3: 0000000480ba6005 CR4: 0000000000760ef0 [ 215.580004] PKRU: 55555554 [ 215.580006] Call Trace: [ 215.580014] ? drm_dp_mst_topology_put_port+0x6f/0x130 [ 215.580072] intel_mst_pre_enable_dp+0x14b/0x170 [i915] [ 215.580129] intel_encoders_pre_enable+0x76/0x90 [i915] [ 215.580191] haswell_crtc_enable+0x84/0x880 [i915] [ 215.580266] intel_update_crtc+0x1e4/0x200 [i915] [ 215.580333] skl_commit_modeset_enables+0x287/0x420 [i915] [ 215.580405] intel_atomic_commit_tail+0x332/0x14e0 [i915] [ 215.580410] ? queue_work_on+0x41/0x70 [ 215.580489] intel_atomic_commit+0x31e/0x350 [i915] [ 215.580500] drm_client_modeset_commit_atomic+0x18b/0x220 [ 215.580523] drm_client_modeset_commit_force+0x4d/0x180 [ 215.580531] drm_fb_helper_restore_fbdev_mode_unlocked+0x46/0xa0 [ 215.580538] drm_fb_helper_set_par+0x27/0x50 [ 215.580543] drm_fb_helper_hotplug_event.part.0+0xa7/0xc0 [ 215.580549] drm_kms_helper_hotplug_event+0x21/0x30 [ 215.580553] process_one_work+0x25b/0x5b0 [ 215.580566] worker_thread+0x4b/0x3b0 [ 215.580578] kthread+0x100/0x140 [ 215.580581] ? process_one_work+0x5b0/0x5b0 [ 215.580585] ? kthread_park+0x80/0x80 [ 215.580591] ret_from_fork+0x24/0x50 [ 215.580603] irq event stamp: 1393930 [ 215.580606] hardirqs last enabled at (1393929): [<ffffffff8112a013>] vprintk_emit+0x143/0x330 [ 215.580609] hardirqs last disabled at (1393930): [<ffffffff81001cfa>] trace_hardirqs_off_thunk+0x1a/0x20 [ 215.580613] softirqs last enabled at (1393434): [<ffffffff81c00389>] __do_softirq+0x389/0x47f [ 215.580618] softirqs last disabled at (1393423): [<ffffffff810b7199>] irq_exit+0xa9/0xc0 [ 215.580621] ---[ end trace afd44ea9caa6373e ]--- BSpec: 4217 BSpec: 14004 BSpec: 20584 BSpec: 50583 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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José Roberto de Souza authored
Talked with HW team and this is a left over, driver should not program clockgating, mg or dekel firmware is reponsible for any clockgating programing. Also removing the register and bits definition related to clockgating. v2: Added WARN_ON v3: Only calling icl_phy_set_clock_gating() on intel_ddi_pre_enable_hdmi for GEN11 v4: ICL should also not program clockgating (thanks Matt for catching this) BSpec issue: 20885 BSpec: 49292 BSpec: 21735 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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José Roberto de Souza authored
Recent improvements in the state tracking in i915 caused PSR to not be enabled when reusing firmware/BIOS modeset, this is due to all initial commits returning ealier in intel_atomic_check() as needs_modeset() is always false. To fix that here forcing the state compute phase in CRTC that is driving the eDP that supports PSR once. Enable or disable PSR do not require a fullmodeset, so user will still experience glitch free boot process plus the power savings that PSR brings. It was tried to set mode_changed in intel_initial_commit() but at this point the connectors are not registered causing a crash when computing encoder state. v2: - removed function return - change arguments to match intel_hdcp_atomic_check v3: - replaced drm includes in intel_psr.h by forward declaration(Jani) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112253 Reported-by: <s.zharkoff@gmail.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200106152128.195171-1-jose.souza@intel.com
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