- 28 Jul, 2015 18 commits
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James Liao authored
Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by:
James Liao <jamesjj.liao@mediatek.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
clk providers are using the consumer APIs to set min/max rates on the clock they're providing. To encourage clk providers to move away from the consumer APIs, add a provider API to set the min/max rate of a clock. The assumption is that this is done before the clock can be requested via clk_get() and that the clock rate is already within the boundaries of the min/max that's configured. Tested-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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Axel Lin authored
Use devm_clk_register() to simplify the code by removing twl6040_clk_remove(). Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Axel Lin authored
The devm_clk_unregister() in .probe error case is not necessary as it will be automatically called when probe fails. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
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Geert Uytterhoeven authored
The CCF implementations for the various shmobile SoCs don't use clkdev functionality, hence drop the inclusion of <linux/clkdev.h>. Add the missing #include <linux/slab.h>, which was included implicitly through <asm/clkdev.h> before. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Stephen Boyd authored
Add __force here so that sparse doesn't complain about us playing tricks with __iomem. Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Stephen Boyd authored
Sparse complains about these structures missing static, but they also don't look to be used. Remove them. drivers/clk/ti/clk-3xxx.c:74:30: warning: symbol 'clkhwops_omap3430es2_ssi_wait' was not declared. Should it be static? drivers/clk/ti/clk-3xxx.c:157:30: warning: symbol 'clkhwops_omap3430es2_hsotgusb_wait' was not declared. Should it be static? Acked-by:
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Stephen Boyd authored
This variable isn't exported outside of this file so mark it static. Silences the following sparse warning: drivers/clk/ti/clk.c:36:24: warning: symbol 'ti_clk_features' was not declared. Should it be static? Acked-by:
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Stephen Boyd authored
smatch reports a failure to check kzalloc() here: drivers/clk/ti/clk.c:232 omap2_clk_provider_init() error: potential null dereference 'io'. (kzalloc returns null) Check for an allocation failure and return -ENOMEM. Acked-by:
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https://github.com/t-kristo/linux-pmStephen Boyd authored
From Tero Kristo: "This pull request contains the TI clock driver set to move the clock implementations under clock driver. Some small portions of the clock driver code still remain under mach-omap2 after this, it should be decided whether this code is now obsolete and should be deleted or should someone try to fix it." Slight merge conflicts with determine_rate prototype changes.
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Axel Lin authored
of_clk_get_parent_count() may return negative error code, so num_parents needs to be int rather than unsigned int. Signed-off-by:
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Stephen Boyd authored
The other ce clocks have the flag set, but ce1 doesn't, so clk_set_rate() doesn't propagate up the tree to the ce1_src_clk. Set the flag as this is supported. Reported-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Tested-by:
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Stephen Boyd authored
We don't unlock the mutex if we fail to allocate the parent names array. Unlock it and return an error in this case as well. Reported-by:
kbuild test robot <fengguang.wu@intel.com> Acked-by:
Julia Lawall <julia.lawall@lip6.fr> Cc: Sergej Sawazki <ce3a@gmx.de> Signed-off-by:
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Stephen Boyd authored
There doesn't seem to be any reason why we can't use the standard readb()/writeb() accessors here because ctrl_inb() and ctrl_outb() match the generic implementation of readb() and writeb() that the h8300 architecture uses. This allows us to test compile this driver on other architectures besides h8300. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
We don't need to print an error on allocation failures, drop it. While we're here, change the sizeof() to be sizeof(*<ptr>) to make code more future proof. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: -
Stephen Boyd authored
* clk-determine-rate-struct: clk: fix some determine_rate implementations clk: change clk_ops' ->determine_rate() prototype
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Boris Brezillon authored
Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org Signed-off-by:
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Boris Brezillon authored
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by:
Romain Perier <romain.perier@gmail.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by:
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- 14 Jul, 2015 1 commit
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Stephen Boyd authored
The error paths in this file leak memory and mappings and test for pointers being valid after dereferencing them. Fix these problems and properly free resources on errors. Fix some stylistic things too like using sizeof(*ptr) and fitting more code on a single line. Note that we don't unregister clocks here. That needs a clk_composite_unregister() API that we don't have right now. Acked-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Cc: Pankaj Dev <pankaj.dev@st.com> Signed-off-by:
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- 08 Jul, 2015 6 commits
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Stephen Boyd authored
* clk-fixes: drivers: clk: st: Incorrect register offset used for lock_status
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Stephen Boyd authored
The list isn't used after of_clk_init() is called, so we don't need to keep an empty list around after init. Put the list on the stack. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: -
Stephen Boyd authored
Dan Carpenter reports that we don't check the allocation here for failure. Add a failure check and free any previously allocated providers from the clk_provider_list. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Stephen Boyd authored
* clk-rk3368: clk: rockchip: add rk3368 clock controller clk: rockchip: add missing include guards clk: rockchip: add dt-binding header for rk3368 dt-bindings: add documentation of rk3668 clock controller clk: rockchip: define the inverters of rk3066/rk3188 and rk3288 clk: rockchip: fix issues in the mmc-phase clock clk: rockchip: add support for phase inverters clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant clk: rockchip: protect register macros against multipart values clk: rockchip: fix faulty vip parent name on rk3288 clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
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Georgi Djakov authored
Add support for SR2 type pll operations. SR2 is optimized for Time Interval Error (TIE) or absolute jitter. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Stephen Boyd authored
Remove useless ifdefs around function prototypes to silence the following sparse warnings when the configs aren't enabled. drivers/clk/at91/clk-h32mx.c:95:13: warning: symbol 'of_sama5d4_clk_h32mx_setup' was not declared. Should it be static? drivers/clk/at91/clk-utmi.c:159:13: warning: symbol 'of_at91sam9x5_clk_utmi_setup' was not declared. Should it be static? Plus, using __init and extern in function prototypes doesn't do anything, so just drop it throughout this file. Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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- 07 Jul, 2015 5 commits
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Pankaj Dev authored
Incorrect register offset used for sthi407 clockgenC Signed-off-by:
Pankaj Dev <pankaj.dev@st.com> Signed-off-by:
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Georgi Djakov authored
Make const both the array and the strings, so they can be moved to .rodata section. Signed-off-by:
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Matthias Brugger authored
X-Gene clocks implement it's name in the clock private struct. This is a duplication of the name field. We can delete the field and rely on the common implementation to retrieve the name. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Sergej Sawazki authored
The file clk-gpio-gate.c does not only contain the gate clock, but also the mux clock. Rename the file to clk-gpio.c. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by:
Sergej Sawazki <ce3a@gmx.de> Signed-off-by:
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Sergej Sawazki authored
Add a common clock driver for basic gpio controlled clock multiplexers. This driver can be used for devices like 5V41068A or 831721I from IDT or for discrete multiplexer circuits. The 'select' pin selects one of two parent clocks. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by:
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- 06 Jul, 2015 10 commits
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Sergej Sawazki authored
Do not output an error message if requesting gpio failes with EPROBE_DEFER. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by:
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Sergej Sawazki authored
Include export.h for EXPORT_SYMBOL_GPL, no need to include module.h. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by:
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Stephen Boyd authored
* clk-fixes: clk: mediatek: mt8173: Fix enabling of critical clocks drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks drivers: clk: st: Fix flexgen lock init drivers: clk: st: Fix FSYN channel values drivers: clk: st: Remove unused code clk: qcom: Use parent rate when set rate to pixel RCG clock clk: at91: do not leak resources clk: stm32: Fix out-by-one error path in the index lookup clk: iproc: fix bit manipulation arithmetic clk: iproc: fix memory leak from clock name
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Sascha Hauer authored
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by:
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Heiko Stuebner authored
Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by:
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Heiko Stuebner authored
Review for the rk3368 turned up that the clock header was missing include guards. This is also true for the already existing clock binding headers, so add them. Signed-off-by:
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Heiko Stuebner authored
Add the dt-bindings header for the rk3368, that gets shared between the clock controller and the clock references in the dts. Signed-off-by:
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Heiko Stuebner authored
Add the devicetree binding for the cru on the rk3368 which quite similar structured as previous clock controllers. Signed-off-by:
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Heiko Stuebner authored
Both soc series' have inverters on the hsadc and camera interface clock paths. So define them using the newly added inverter type. Signed-off-by:
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Heiko Stuebner authored
The review for the new inverter clock type uncovered some issues (missing headers and name handling) that are also present in the mmc-phase clock type, I got (to much) inspiration from. Fix these there too. Signed-off-by:
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