For reasons only Motorola will ever know they decided to use a
substantially different register layout for the FEC ethernet device on
the 5282 ColdFire silicon.  This defines an appropriate access structure
for it.

The ColdFire 5282 CPU also uses the Motorla FEC ethernet core, allow if
to be selected for that config.

This adds support for the ColdFire 5282 to the ColdFire serial driver.

Only a few small changes, notably the interrupt setup is a little
different.  Also removed some dead code.

Add support for the 5282 ColdFire to the common ColdFire serial
driver header. Also added the additional registers of the 5272,
they are used to setup a more accurate baud rate timers

Rework the m68knommu/ColdFire/5307 Makefile to build the correct
timer code for each of the different ColdFire CPU types.

d_path() can return -ENAMETOOLONG these days. Pass it upstream.

A patch mostly by Will Cohen, adding a parameter to OProfile to
over-ride use of the perfctr hardware. Useful for testing and
a host of other things.

The code that attempts to reset last_task and in_kernel has a race
against samples appearing during the handling of the buffers, that
causes a small number of mis-attribution of samples. Closing the
window is non-obvious, and not worth it, so we just make it smaller.
Even without the patch, there seem to be few such "bad" samples
because its effects are mitigated on a switch into userspace or
a task switch.

My previous fix was incomplete, we could get the same thing happening
on the init-failure path. Fix that.

This code supports the PIT timer of the 5282 ColdFire.

This new timer device is completely different to the previous ColdFire
timer device.

Create a header file to support the PIT timer of the ColdFire 5282 CPU.
This timer is completely different to all previous ColdFire timers.

Add DMA base addresses for the ColdFire 5282 CPU.

Modify the common SIM header for all ColdFire CPU's to incldue the
new 5282 ColdFire defines.

Create header definitions file to support the ColdFire 5282 CPU.
Unfortunately its register layout and setup is quite different
to previous ColdFire CPU family members.

Start up code for the M5282C3 Motorola ColdFire 5282 evaluation board.

New architecture and board for the m68knommu architecture branch, though
it is not very different to most existing ColdFire eval boards.

This creates specific ColdFire/5282 configuration initialization.

Add ColdFire 5282 support to common ColdFire header file.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5206 CPU.  This is used by the architecture timer code for
microsecond accurate time calculations.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5249 CPU.  This is used by the architecture timer code for
microsecond accurate time calculations.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5206e CPU.  This is used by the architecture timer code
for microsecond accurate time calculations.

Obvious strlcpy conversions in arch/*. In fact, mips and mips64 had an
actual bug in sys_sysmips(). Confirmed with Keith Wesolowski.

So here it is, easy split support for md and dm. Neil, the changes over
your version are merely:

- Make a global bio split pool instead of requring device setup of one.
  Will waste 8 * sizeof(struct bio_pair) of RAM, but... For 2.6 at least
  it has to be a core functionality.

- Various style changes to follow the kernel guide lines.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5407 CPU.  This is used by the architecture timer code for
microsecond accurate time calculations.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5272 CPU.  This is used by the architecture timer code for
microsecond accurate time calculations.

Add a function to allow checking if the timer interrupt is pending for
the m68knommu/5307 CPU.  This is used by the architecture timer code for
microsecond accurate time calculations.

This adds offset calculcation to the m68knommu/ColdFire timers.  Allows
microsecond accuracy for gettimeofday and friends.

This patch adds appropriate locking around updates of the xtime
structure for the m68knommu ColdFire architecture timers.

This patch updates the defconfig for the m68knommu architecture.

This patch does a couple of things to the m68knommu common linker
script:
 - adds support for the 5282 ColdFire CPU
 - fixes broken setup for the Dragon Engine board

Add dummy VMALLOC_START and VMALLOC_END defines to m68knommu architectures.
Some code in the proc filesystem breaks without them now.

(i) The prototypes for free_vfsmnt(), alloc_vfsmnt(), do_kern_mount()
    so far occurred in several individual c files.  Now they are in
    <linux/mount.h>.

(ii) do_kern_mount() has a third argument name that is typically a
     constant.  It is called with "rootfs", "nfsd", type->name,
     "capifs", "usbdevfs", "binfmt_misc" etc.  So, it should have a
     prototype that expresses this:

	do_kern_mount(const char *fstype, int flags, const char *name, void *data);

This makes the ugly cast

-       return do_kern_mount(type->name, 0, (char *)type->name, NULL);
+       return do_kern_mount(type->name, 0, type->name, NULL);

go away. Now do_kern_mount() calls type->get_sb(), so also get_sb()
must have a const third argument. That is what the patch below does.

If I am not mistaken, precisely two filesystems do not treat this
argument as a constant, namely afs and cifs. A separate patch
gives some cleanup there.

This fixes some ColdFire 5407 cache bogosity.  Previous code was pushing
all cache lines and the invalidating all of the cache.  The push should
be enough, and now with underlying fixes the the cache setup registers
it is.  Removed the whole invalidate cycle.

Original patch cam from Allessandro Rubini.

Correct the wrong cache setup used on the MOTOROLA 5407 based board.
Specifically it enables precise exception mode and write buffering.

Original patch from Alessendra Rubini.

Correct the wrong cache setup used on the CLEOPATRA 5407 based board.
Specifically it enables precise exception mode and write buffering.

Original patch from Alessendra Rubini.