- 30 Oct, 2019 6 commits
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Jiange Zhao authored
SRIOV VF doesn't support BACO. Only PF with BACO capability can do it. Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Geert Uytterhoeven authored
There is no need to cast a typed pointer to a void pointer when calling a function that accepts the latter. Remove it, as the cast prevents further compiler checks. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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YueHaibing authored
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1221:24: warning: variable adev set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:488:24: warning: variable adev set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:547:24: warning: variable adev set but not used [-Wunused-but-set-variable] It is never used, so can removed it. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Alex Sierra authored
The bitmap in cu_info structure is defined as a 4x4 size array. In Acturus, this matrix is initialized as a 4x2. Based on the 8 shaders. In the gpu cache filling initialization, the access to the bitmap matrix was done as an 8x1 instead of 4x2. Causing an out of bounds memory access error. Due to this, the number of GPU cache entries was inconsistent. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Yong Zhao authored
The KIQ is on the second MEC and its reservation is covered in the latter logic, so no need to reserve its bit twice. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Yong Zhao authored
Given amdkfd.ko has been merged into amdgpu.ko, this switch is no longer useful. Signed-off-by:
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- 28 Oct, 2019 10 commits
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Kyle Mahlkuch authored
During kexec some adapters hit an EEH since they are not properly shut down in the radeon_pci_shutdown() function. Adding radeon_suspend_kms() fixes this issue. Enabled only on PPC because this patch causes issues on some other boards. Signed-off-by:
Kyle Mahlkuch <kmahlkuc@linux.vnet.ibm.com> Signed-off-by:
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YueHaibing authored
Fix sparse warnings: drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2050:5: warning: symbol 'arcturus_i2c_eeprom_control_init' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2068:6: warning: symbol 'arcturus_i2c_eeprom_control_fini' was not declared. Should it be static? Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
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Wambui Karuga authored
Correct the "_LENTH" mispelling in the AMDGPU_MAX_TIMEOUT_PARAM_LENGTH constant. Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
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Wambui Karuga authored
Declare `amdgpu_exp_hw_support` as extern in amdgpu.h to address the following sparse warning: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:118:5: warning: symbol 'amdgpu_exp_hw_support' was not declared. Should it be static? Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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YueHaibing authored
Fix sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:963:6: warning: symbol 'calculate_integer_scaling' was not declared. Should it be static? Reported-by:
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Pelle van Gils authored
The vega10_odn_update_soc_table() function does not allow the SCLK dependent voltage to be set for power-state 7 to a value below the default in pptable. Change the for-loop condition to allow undervolting in the highest state. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205277Signed-off-by:
Pelle van Gils <pelle@vangils.xyz> Signed-off-by:
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chen gong authored
if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu. Platform: Renoir dmesg log information: [ 151.844110 ] amdgpu: [powerplay] SMU is resuming... [ 151.844116 ] amdgpu: [powerplay] dpm has been disabled [ 151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffffffb param 0x1 [ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully! Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Wambui Karuga authored
Remove unnecessary assignment for return value and have the function return the required value directly. Issue found by coccinelle: @@ local idexpression ret; expression e; @@ -ret = +return e; -return ret; Reviewed-by:Wambui Karuga <wambui@karuga.xyz> Signed-off-by:
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zhongshiqi authored
dc.c:583:null check is needed after using kzalloc function Reviewed-by:
zhongshiqi <zhong.shiqi@zte.com.cn> Signed-off-by:
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Chenwandun authored
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: In function dce_aux_configure_timeout: drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: warning: variable timeout set but not used [-Wunused-but-set-variable] Signed-off-by:
Chenwandun <chenwandun@huawei.com> Signed-off-by:
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- 25 Oct, 2019 24 commits
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Andrey Grodzovsky authored
Use ERR_PTR to return back the error happened during amdgpu_ib_schedule. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Problem: When run_job fails and HW fence returned is NULL we still signal the s_fence to avoid hangs but the user has no way of knowing if the actual HW job was ran and finished. Fix: Allow .run_job implementations to return ERR_PTR in the fence pointer returned and then set this error for s_fence->finished fence so whoever wait on this fence can inspect the signaled fence for an error. Signed-off-by:
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chen gong authored
The parameters what SMU_MSG_PowerUpVcn need is 0, not 1 Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Tianci.Yin authored
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by:
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Tianci.Yin authored
update registers: mmCGTT_SPI_CLK_CTRL Reviewed-by:
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Evan Quan authored
For dpm disabled case, it's assumed the only one support clock level is always current clock level. Signed-off-by:
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Evan Quan authored
For Arcturus, clock limit settings on uclk/socclk/fclk domains are not supported. V2: simplify the code to support both SGPU and MGPU cases Signed-off-by:
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Marek Olšák authored
Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
For Arcturus the I2C traffic is done through SMU tables and so we must postpone RAS recovery init to after they are ready which is in amdgpu_device_ip_hw_init_phase2. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Add Arcturus EEPROM/I2C support in generic EEPROM code. Signed-off-by:
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Andrey Grodzovsky authored
The communication is done through SMU table and hence the code is in powerplay. Signed-off-by:
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Andrey Grodzovsky authored
Will be used by Arcturus support for RAS page retirement. Signed-off-by:
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Leo Li authored
[Why] Some LED panel drivers might not like fractional PWM. In such cases, backlight flickering may be observed. [How] Add a DC feature mask to disable fractional PWM, and associate it with the preexisting dc_config flag. The flag is only plumbed through the dmcu firmware, so plumb it through the driver path as well. To disable, add the following to the linux cmdline: amdgpu.dcfeaturemask=0x4 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957Signed-off-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Lukáš Krejčí <lskrejci@gmail.com> Signed-off-by:
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Nirmoy Das authored
Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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James Zhu authored
After VCN2.5 firmware (Version ENC: 1.1 Revision: 11), VCN2.5 encoding can work properly. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Pelloux-prayer, Pierre-eric authored
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481. v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
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chen gong authored
VKexample test hang during Occlusion/SDMA/Varia runs. Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue. Signed-off-by:
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Guchun Chen authored
Easy for maintainance. Signed-off-by:
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Guchun Chen authored
Ras reboot debugfs node allows user one easy control to avoid gpu recovery hang problem and directly reboot system per card basis, after ras uncorrectable error happens. However, it is one common entry, which should get rid of ras_ctrl node and remove ip dependence when inputting by user. So add one new auto_reboot node in ras debugfs dir to achieve this. v2: in commit mssage, add justification why ras reboot debugfs node is needed. v3: use debugfs_create_bool to create debugfs file for boolean value Signed-off-by:
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Philip Yang authored
If device reset/suspend/resume failed for some reason, dqm lock is hold forever and this causes deadlock. Below is a kernel backtrace when application open kfd after suspend/resume failed. Instead of holding dqm lock in pre_reset and releasing dqm lock in post_reset, add dqm->sched_running flag which is modified in dqm->ops.start and dqm->ops.stop. The flag doesn't need lock protection because write/read are all inside dqm lock. For HWS case, map_queues_cpsch and unmap_queues_cpsch checks sched_running flag before sending the updated runlist. v2: For no-HWS case, when device is stopped, don't call load/destroy_mqd for eviction, restore and create queue, and avoid debugfs dump hdqs. Backtrace of dqm lock deadlock: [Thu Oct 17 16:43:37 2019] INFO: task rocminfo:3024 blocked for more than 120 seconds. [Thu Oct 17 16:43:37 2019] Not tainted 5.0.0-rc1-kfd-compute-rocm-dkms-no-npi-1131 #1 [Thu Oct 17 16:43:37 2019] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [Thu Oct 17 16:43:37 2019] rocminfo D 0 3024 2947 0x80000000 [Thu Oct 17 16:43:37 2019] Call Trace: [Thu Oct 17 16:43:37 2019] ? __schedule+0x3d9/0x8a0 [Thu Oct 17 16:43:37 2019] schedule+0x32/0x70 [Thu Oct 17 16:43:37 2019] schedule_preempt_disabled+0xa/0x10 [Thu Oct 17 16:43:37 2019] __mutex_lock.isra.9+0x1e3/0x4e0 [Thu Oct 17 16:43:37 2019] ? __call_srcu+0x264/0x3b0 [Thu Oct 17 16:43:37 2019] ? process_termination_cpsch+0x24/0x2f0 [amdgpu] [Thu Oct 17 16:43:37 2019] process_termination_cpsch+0x24/0x2f0 [amdgpu] [Thu Oct 17 16:43:37 2019] kfd_process_dequeue_from_all_devices+0x42/0x60 [amdgpu] [Thu Oct 17 16:43:37 2019] kfd_process_notifier_release+0x1be/0x220 [amdgpu] [Thu Oct 17 16:43:37 2019] __mmu_notifier_release+0x3e/0xc0 [Thu Oct 17 16:43:37 2019] exit_mmap+0x160/0x1a0 [Thu Oct 17 16:43:37 2019] ? __handle_mm_fault+0xba3/0x1200 [Thu Oct 17 16:43:37 2019] ? exit_robust_list+0x5a/0x110 [Thu Oct 17 16:43:37 2019] mmput+0x4a/0x120 [Thu Oct 17 16:43:37 2019] do_exit+0x284/0xb20 [Thu Oct 17 16:43:37 2019] ? handle_mm_fault+0xfa/0x200 [Thu Oct 17 16:43:37 2019] do_group_exit+0x3a/0xa0 [Thu Oct 17 16:43:37 2019] __x64_sys_exit_group+0x14/0x20 [Thu Oct 17 16:43:37 2019] do_syscall_64+0x4f/0x100 [Thu Oct 17 16:43:37 2019] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Suggested-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Zhan liu authored
[Why] DWB (Display Writeback) flag needs to be enabled as 1, or system will throw out a few warnings when creating dcn20 resource pool. Also, Navi14's dwb setting needs to match Navi10's, which has already been set to 1. [How] Change value of num_dwb from 0 to 1. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Roman Li authored
[Why] Adding psr mask to dc features allows selectively disable/enable psr. Current psr implementation may not work with non-pageflipping application. Until resolved it should be disabled by default. [How] Add dcfeaturemask for psr enablement. Disable by default. To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Evan Quan authored
With this cleanup, the APIs from amdgpu_smu.c will map to ASIC specific ones directly. Those can be shared around all SMU V11/V12 ASICs will be put in smu_v11_0.c and smu_v12_0.c respectively. Signed-off-by:
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