- 30 Aug, 2013 40 commits
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Alex Deucher authored
Similar to DCE4/5, but supports multiple audio pins which can be assigned per afmt block. v2: rework the driver to handle more than one audio pin. v3: try different dto reg v4: properly program dto v5 (ck): change dto programming order v6: program speaker allocation block v7: rebase v8: rebase on Rafał's changes v9: integrated Rafał's comments, update to latest drm_edid_to_speaker_allocation API v10: add missing line break in error message v11: add back audio enabled messages v12: fix copy paste typo in r600_audio_enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Rafał Miłecki <zajec5@gmail.com>
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Rafał Miłecki authored
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds a helper function to extract the speaker allocation data block from the EDID. This data block describes what speakers are present on the display device. v2: update per Ville Syrjälä's comments v3: fix copy/paste typo in memory allocation Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Rafał Miłecki <zajec5@gmail.com>
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Christian König authored
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Our different hardware blocks are actually completely separated, so it doesn't make much sense any more to structure the code by pure chipset generations. Start restructuring the code by separating our the UVD block. v2: updated commit message v3: rebased and restructurized start/stop functions for kv dpm. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Now that we have callbacks for [rw]ptr handling we can remove the special handling for the DMA rings and use the callbacks instead. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Give the ring functions a separate structure and let the asic structure point to the ring specific functions. This simplifies the code and allows us to make changes at only one point. No change in functionality. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Need to swap the data fetched over i2c properly. This is the same fix as the endian fix for aux channel transactions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
According to the internal teams, we never hit the limit for mclk switching on these asics, so we can disable the check. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The LCD has a relatively short vblank time (216us), but the card is able to reclock memory fine in that time. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: normalrawr@gmail.com
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Alex Deucher authored
Disable the UVD block when not in use to save power. The block is not actually powergated on CI, but we switch between UVD DPM (where the uvd clocks are adjusted on demand) and clocks off. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Powergate the UVD block when not in use to save power. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When we PG (powergate) UVD, we need to re-initialize it before we can use it again. v2: rebase on UVD stop fixes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Starting on CIK, multi-media blocks like UVD no longer have special power state. Rather they have their own DPM implementation which adjusts their clocks dynamically when active. When they are not active, the blocks are powergated to save power. v2: add missing pm locks v3: rebase on uvd state selection rework v4: fix inverted logic typo noticed by Christian Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
convert from number of lanes to register setting. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Used for vce power management. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Required for dpm on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Uses a different table format if the board supports EVV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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