- 07 Mar, 2018 28 commits
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Bhawanpreet Lakha authored
HW Engineer's Notes: During switch from vga->extended, if we set the VGA_TEST_ENABLE and then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset VGA_TEST_ENABLE, to leave it in the same state as before. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo (Sunpeng) Li authored
While checking plane states for updates during atomic check, we create dc_plane_states in preparation. These dc states should be freed if something errors. Although the input transfer function is also freed by dc_plane_state_release(), we should free it (on error) under the same scope as where it is created. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Harry Wentland authored
Signed-off-by:
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Eric Yang authored
Before dig fe is enabled, infoframe can't be programmed. So in suspend resume case our infoframe programmming was not going through. This change changes the sequence so that infoframe is programmed after. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Roman Li authored
Fixing null-deref on Vega10 due to regression after 'fix cursor related Pstate hang' change. Added null checks in setting cursor position. Signed-off-by:
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Eric Yang authored
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK If graphics plane go from 1 pipe to hsplit, the cursor updates after mpc programming and unlock. Which means there is a window of time where cursor is enabled on the wrong pipe if it's on the right side of the screen (i.e. case where cursor need to move from pipe 0 to pipe 3 post split). This will cause pstate hang. Solution is to program the cursor while still locked. Signed-off-by:
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Mikita Lipski authored
Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed the wrong memory location. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
There is no need to call drm_mode_set_crtcinfo() again once crtc timing is decided. Otherwise non-native/unsupported timing might get overwritten. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Harry Wentland authored
There's no good place in DC to cover all place where stream signal should be updated. update_stream_signal depends on timing which comes from DM. Signed-off-by:
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Harry Wentland authored
We've got a helper function to call dc_create_stream_for_sink and one other place that calls it directly. Make sure we call the helper functions always since we need to update a bunch of things in stream and don't want to miss that. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by:
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Harry Wentland authored
This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Roman Li authored
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by:
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Jerry (Fangzhi) Zuo authored
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by:
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Shirish S authored
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. This change leads to BUG hit while performing atomic commit on amd driver. As a fix this patch ensures that we disable the CRTC's with NULL FB by returning -EINVAL and hence triggering fall back to the old behavior and turning off the crtc in atomic_remove_fb(). V2: Added error check for plane_state and removed sanity check for crtc. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Michel Dänzer authored
For consistency with other DCE generations. HPD IRQs appear to be working fine. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Harry Wentland authored
There have been many reports of Ellesmere and Baffin systems not being able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN bit from VBIOS table. Windows seems to not have this issue. On some systems we fail to the encoder cap info from VBIOS. In that case we should default to enabling HDMI6G support. This was tested by dwagner on https://bugs.freedesktop.org/show_bug.cgi?id=102820Signed-off-by:
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Shirish S authored
This patch updates the dc's plane state with the parameters set by the user side. This is needed to validate the plane capabilities with the parameters user space wants to set. Signed-off-by:
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Shirish S authored
CZ & ST support uptil a limit 2:1 downscaling, this patch adds validate_plane hook, that shall be used to validate the plane attributes sent by the user space based on dce110 capabilities. Signed-off-by:
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Shirish S authored
amdgpu_dm_atomic_check() is used to validate the entire configuration of planes and crtc's that the user space wants to commit. However amdgpu_dm_atomic_check() depends upon DRM_MODE_ATOMIC_ALLOW_MODESET flag else its mostly dummy. Its not mandatory for the user space to set DRM_MODE_ATOMIC_ALLOW_MODESET, and in general its not set either along with DRM_MODE_ATOMIC_TEST_ONLY. Considering its importantance, this patch defers the allow_modeset check in dm_update_planes_state(), so that there shall be scope to validate the configuration sent from user space, without impacting the population of dc/dm related data structures. Signed-off-by:
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Harry Wentland authored
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Rex Zhu authored
it is required if a platform supports PCIe root complex core voltage reduction. After receiving this notification, SBIOS can apply default PCIe root complex power policy. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Always set the graphics values to the max for the asic type. E.g., some 1 RB chips are actually 1 RB chips, others are actually harvested 2 RB chips. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353Reviewed-by:
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- 05 Mar, 2018 3 commits
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Roman Li authored
Clean fake sink flag after detecting link on downstream port. Fixing display light-up after "hot-unplug&plug again" downstream of an active dongle. Signed-off-by:
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Alex Deucher authored
Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244Acked-by:
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Tom St Denis authored
The read/write pointers on sdma4 devices increment beyond the ring size and should be masked. Tested on my Ryzen 2400G. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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- 01 Mar, 2018 3 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
A few misc fixes for 4.16. * 'drm-fixes-4.16' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: skip ECC for SRIOV in gmc late_init drm/amd/amdgpu: Correct VRAM width for APUs with GMC9 drm/amdgpu: fix&cleanups for wb_clear drm/amdgpu: Correct sdma_v4 get_wptr(v2) drm/amd/powerplay: fix power over limit on Fiji drm/amdgpu:Fixed wrong emit frame size for enc drm/amdgpu: move WB_FREE to correct place drm/amdgpu: only flush hotplug work without DC drm/amd/display: check for ipp before calling cursor operations
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git://people.freedesktop.org/drm-miscDave Airlie authored
Two regression fixes here: a fb format regression on nouveau and a 4.16-rc1 regression with on LVDS with one sun4i device. Plus a sun4i and a virtio-gpu fixes. * tag 'drm-misc-fixes-2018-02-28' of git://people.freedesktop.org/drm-misc: virtio-gpu: fix ioctl and expose the fixed status to userspace. drm/sun4i: Protect the TCON pixel clocks drm/sun4i: Enable the output on the pins (tcon0) drm/nouveau: prefer XBGR2101010 for addfb ioctl
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Dave Airlie authored
Merge tag 'drm-intel-fixes-2018-02-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - 2 display fixes: audio av_enc_map overflow check, and Cannonlake PLL related register offset. - 3 gem fixes: Clear for in-fence out-fence, fix for clearing exec_flags on execbuf failure, and add back global seqno to tracepoints that had been removed recently by other fence related patch. * tag 'drm-intel-fixes-2018-02-28' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Make global seqno known in i915_gem_request_execute tracepoint drm/i915: Clear the in-use marker on execbuf failure drm/i915/cnl: Fix PORT_TX_DW5/7 register address drm/i915/audio: fix check for av_enc_map overflow drm/i915: Fix rsvd2 mask when out-fence is returned
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- 28 Feb, 2018 6 commits
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Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Tom St Denis authored
DDR4 has a 64-bit width not 128-bits. It was reporting twice the width. Tested with my Ryzen 2400G. Signed-off-by:
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Monk Liu authored
fix: should do right shift on wb before clearing cleanups: 1,should memset all wb buffer 2,set max wb number to 128 (total 4KB) is big enough Signed-off-by:
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Emily Deng authored
the original method will change the wptr value in wb. v2: furthur cleanup Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Eric Huang authored
power containment disabled only on Fiji and compute power profile. It violates PCIe spec and may cause power supply failed. Enabling it will fix the issue, even the fix will drop performance of some compute tests. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
Emit frame size should match with corresponding function, uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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