- 03 Sep, 2014 40 commits
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Damien Lespiau authored
Previously, it was possible for the GPU memory accesses to be swizzled to try to optimize the fetches for tiled buffers. This swizzling was on top of what the memory controller in the uncore already does. With broadwell, we drop that GPU side swizzling, and the corresponding initialization in 3 units (GAM, GT, DE). All those bits are reserved, as specs put it: Before Gen8, there was a historical configuration control field to swizzle address bit[6] for in X/Y tiling modes. This was set in three different places: TILECTL[1:0], ARB_MODE[5:4], and DISP_ARB_CTL[14:13]" For Gen8 the swizzle fields are all reserved, and the CPU's memory controller performs all address swizzling modifications. This also means that user space doesn't have to manually swizzle when accessing tiled buffers from the CPU, and so we always return I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which short-circuits the initialization of the registers mentionned above in i915_gem_init_swizzling(). v2: Refine the explanation a bit more (Daniel) v3: Make it BDW+ specific (Steve) Cc: Steve Aarnio <steve.j.aarnio@linux.intel.com> Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> [danvet: Keep the actual code to set the tiling bits for now, in case some bios escaped to the wild that uses this - we'd need it for fastboot.] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
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Damien Lespiau authored
Instead of going through hoops, just put the driver author directly as DRM_AUTHOR() argument. This will also make it consistent when we add Intel to the list. Signed-off-by:
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Jani Nikula authored
Fix assert_panel_unlocked for vlv/chv, and improve it a bit for non-LVDS. Also don't pretend it works for DDI. There's still work to do to get this right for eDP on PCH platforms, but this is a start. v2: WARN_ON(HAS_DDI) Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Vedang Patel authored
The patch introduces fixes for the debugfs attributes emitted by the i915 driver for GEN8. Currently, it is not emitting the correct attributes which include the status of RC6 states. Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df Signed-off-by:
Vedang Patel <vedang.patel@intel.com> Signed-off-by:
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Chris Wilson authored
Rather than describing an object as either "snooped or LLC", we can do better as we should know what machine we are running on! Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Paulo Zanoni authored
On BDW we're seeing a problem that after we runtime resume, the outputs connected to DDI C are not detected: they don't appear in the SDEISR register and GMBUS transactions don't work. They stop working at the moment we call intel_opregion_notify_adapter() during runtime suspend, but they don't go back to work when we call the same function during runtime resume. They only work after we do a modeset and call intel_opregion_notify_encoder(), but this point is already too late. While debugging, I tried to pass PCI_D3hot which is the value that matches the spec, and it seems to have solved the problem. I couldn't find any explanation of why this solves the problem, but there's also no documented explanation - besides our code and git log - of why Haswell should use PCI_D1, so keep this for now in order to keep BDW runtime PM working. Also add a comment to point the fact that there's no spec documenting all the weirdness involved here. Cc: kristen.c.accardi@intel.com Testcase: igt/pm_rpm/drm-resources-equal Testcase: igt/pm_rpm/i2c Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Paulo Zanoni authored
Because CHV uses cherryview_init_clock_gating instead of gen8_init_clock_gating. Signed-off-by:
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Paulo Zanoni authored
Because BDW has WPT, which is equivalent to LPT. This is just like the CPT/PPT case. Signed-off-by:
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Jani Nikula authored
Use the correct mask for the unlock bits. In theory this could have lead to incorrect asserts but this is unlikely in practise. Signed-off-by:
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Thomas Daniel authored
These two functions make no sense in an Logical Ring Context & Execlists world. v2: We got rid of lrc_enabled and centralized everything in the sanitized i915.enable_execlists instead. Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> v3: Rebased. Corrected a typo in comment for i915_switch_context and added a comment that it should not be called in execlist mode. Added WARN_ON if i915_switch_context is called in execlist mode. Moved check for execlist mode out of i915_switch_context and into callers. Added comment in context_reset explaining why nothing is done in execlist mode. Signed-off-by:
Thomas Daniel <thomas.daniel@intel.com> [danvet: Simplify the patch subject so I can understand it.] Signed-off-by:
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Deepak S authored
Programing GT IER interrupts was fumbled while enabling Interrupts for gen8 We forgot to program PM IER interrupt in gen8_gt_irq_postinstall based on the new re-worked interrupt routines. v2: Kill the loop and init GT interrupts individually (Ville) Signed-off-by:
Deepak S <deepak.s@linux.intel.com> Reviewed-by:
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Thomas Daniel authored
A pending commit removes synchronous mode from switch_mm. This breaks execlists because switch_mm will always try to write to the legacy ring buffer. Return immediately from i915_ppgtt_init_gw in execlists mode. No longer check for execlists mode in gen8_ppgtt_enable() because this will no longer be called in execlists mode. Signed-off-by:
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Chris Wilson authored
Be sure to always flush a stuck pageflip even if we couldn't possibly expect one to be there. References: https://bugs.freedesktop.org/show_bug.cgi?id=82612Signed-off-by:
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Michel Thierry authored
Unfortunately, the gem_obj/vma relationship is not symmetrical; a gem_obj can look up for the same vma more than once (where the ppgtt refcount is incremented), but will free the vma only once (i915_gem_free_object). This difference in refcount get/put means that the ppgtt is not removed after the context and vma are destroyed, because sometimes the refcount will never go back to zero. v2: Just move the ppgtt refcount into vma_create. OTC-Jira: VIZ-3719 Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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Ville Syrjälä authored
Less pointless indentation is always nice. There will be a bit more code in this function once the power sequencer locking is fixed. Signed-off-by:
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Ville Syrjälä authored
If we force vdd off warn if someone is still using it. With this change the delayed vdd off work needs to check want_panel_vdd itself to make sure it doesn't try to turn vdd off when someone is using it. Signed-off-by:
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Ville Syrjälä authored
Looks nicer. Not functional change. Signed-off-by:
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Ville Syrjälä authored
Add a comment to explain why we care about the current want_panel_vdd state in intel_dp_aux_ch(). Signed-off-by:
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Ville Syrjälä authored
edp_* are now the lower level functions and intel_edp_* the higher level ones. One should use them in pairs. v2: Don't return void (Jani) Reviewed-by:
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Ville Syrjälä authored
We want to use the higher level vdd on func here. Not a big deal yet (we'd just get the warn when things go awry) but when the locking gets fixed this becomes more important. Signed-off-by:
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Ville Syrjälä authored
Passing the port as a parameter to PANEL_PORT_SELECT_VLV results in neater code. Sadly the PCH port select bits aren't suitable for the same treatment and the resulting macro would be much uglier, so leave those defines as is. Signed-off-by:
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Thomas Daniel authored
A previous commit broke aliasing PPGTT for lrc, resulting in a kernel oops on boot. Add a check so that is full PPGTT is not in use the context is populated with the aliasing PPGTT. Issue: VIZ-4278 Signed-off-by:
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Chris Wilson authored
In the move over to use BIOS connector configs, we lost the ability to force a specific set of connectors on or off. Try to remedy that by dropping back to the old behavior if we detect a hard coded connector config that tries to enable a connector (disabling is easy!). Based on earlier patches by Jesse Barnes. v2: Remove Jesse's patch Reported-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ben Widawsky authored
v2: fix conflict on rebase. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Deepak S authored
We need do forcewake before Disabling RC6, This is what the BIOS expects while going into suspend. v2: updated commit message. (Daniel) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Deepak S <deepak.s@intel.com> Signed-off-by:
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Damien Lespiau authored
Improve the debug message that tells us we've been waiting for a vblank that never arrived. Printing the pipe could lead a "doh!" moment where we've been waiting for a vblank on a pipe that was off for instance. Signed-off-by:
Thomas Wood <thomas.wood@intel.com> [danvet: Polish commit message a bit.] Signed-off-by:
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Damien Lespiau authored
Chris has decided that enough is enough. It's time to fixup dev Vs dev_priv. This is a modest contribution to the crusade. v2: Still use INTEL_INFO(), for the (mythical!) case we want to hardcode the info struct with defines (Chris) Rename the macro argument from 'dev' to 'dev_priv' (Jani) v3: Use names unlikely to be used as macro arguments (Chris) Suggested-by: -
Jani Nikula authored
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Oscar Mateo authored
Since the ringbuffer does not belong per engine anymore, we have to make sure that we are always recording the correct ringbuffer. TODO: This is only a small fix to keep basic error capture working, but we need to add more information for it to be useful (e.g. dump the context being executed). v2: Reorder how the ringbuffer is chosen to clarify the change and rename the variable, both changes suggested by Chris Wilson. Also, add the TODO comment to the code, as suggested by Daniel. Signed-off-by:
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Chris Wilson authored
Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Chris Wilson authored
For cleanliness, i915_error_object_create() was written to handle the NULL pointer in a central location. The macro that wrapped it and passed it a num_pages to use, was not safe. As we now never limit the num_pages to use (we did so at one point to only capture the first page of the context), we can remove the redundant macro and be NULL safe again. Signed-off-by:
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Chris Wilson authored
For stolen pages, since it is verboten to access them directly on many architectures, we have to read them through the GTT aperture. If they are not accessible through the aperture, then we have to abort. This was complicated by commit 8b6124a6 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jan 30 14:38:16 2014 +0000 drm/i915: Don't access snooped pages through the GTT (even for error capture) and the desire to use stolen memory for ringbuffers, contexts and batches in the future. Signed-off-by:
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Jani Nikula authored
Make backlight class sysfs brightness 0 value switch off the backlight for connectors that have the backlight_power callback defined. For eDP, this has the similar caveats regarding power savings as bl_power as only the power sequencer backlight control is switched off. Signed-off-by:
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Jani Nikula authored
This lets the userspace switch off the backlight using the backlight class sysfs bl_power file. The switch is done using the power sequencer; the backlight PWM, and everything else, remains enabled. The display backlight won't draw power, but for maximum power savings the encoder needs to be switched off. Signed-off-by:
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Jani Nikula authored
Make backlight class sysfs bl_power a sub-state of backlight enabled, if a backlight power connector callback is defined. It's up to the connector callback to handle the sub-state, typically in a way that respects panel power sequencing. v2: Post the version that does not oops. *facepalm*. Signed-off-by:
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Jani Nikula authored
Make it possible to change panel power control backlight state without touching the PWM. No functional changes. Signed-off-by:
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Paulo Zanoni authored
The GEN6_PM* registers don't exist on BDW anymore, so when we read this file we trigger unclaimed register errors. The equivalent BDW register for PMs is GEN8_GT_I*R(2), so use it. Testcase: igt/pm_rpm/debugfs-read Signed-off-by:
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Sonika Jindal authored
Primary planes support 180 degree rotation. Expose the feature through rotation drm property. v2: Calculating linear/tiled offsets based on pipe source width and height. Added 180 degree rotation support in ironlake_update_plane. v3: Checking if CRTC is active before issueing update_plane. Added wait for vblank to make sure we dont overtake page flips. Disabling FBC since it does not work with rotated planes. v4: Updated rotation checks for pending flips, fbc disable. Creating rotation property only for Gen4 onwards. Property resetting as part of lastclose. v5: Resetting property in i915_driver_lastclose properly for planes and crtcs. Fixed linear offset calculation that was off by 1 w.r.t width in i9xx_update_plane and ironlake_update_plane. Removed tab based indentation and unnecessary braces in intel_crtc_set_property and intel_update_fbc. FBC and flip related checks should be done only for valid crtcs. v6: Minor nits in FBC disable checks for comments in intel_crtc_set_property and positioning the disable code in intel_update_fbc. v7: In case rotation property on inactive crtc is updated, we return successfully printing debug log as crtc is inactive and only property change is preserved. v8: update_plane is changed to update_primary_plane, crtc->fb is changed to crtc->primary->fb and return value of update_primary_plane is ignored. v9: added rotation property to primary plane instead of crtc. Removing reset of rotation property from lastclose. rotation_property is moved to drm_mode_config, so drm layer will take care of resetting. Adding updation of fbc when rotation is set to 0. Allowing rotation only if value is different than old one. v10: Calling intel_primary_plane_setplane instead of update_primary_plane in set_property(Daniel). v11: Using same set_property function for both primary and sprite, Adding primary plane specific code in the same function (Matt). v12: Removing disabling/ enabling of fbc from set_property because it is done from intel_pipe_set_base. Other formatting v13: we need to call disable_fbc before changing the rotation to 180, disable_fbc from intel_pipe_set_base gets called very late, that will be used to re-enable fbc if rotation is set to 0 (Ville). Testcase: igt/kms_rotation_crc Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by:
Sonika Jindal <sonika.jindal@intel.com> [danvet: Add FIXME to explain why we need the open-coded update_fbc hunk to disable fbc when rotated 180 degree. And make checkpatch happier.] Acked-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Sonika Jindal authored
This unifies how the primary plane functions work with how the sprite functions works, which allows us to reuse them to update primary plane properties. v2: Moving setting of plane members in the end to take care of failure cases and not-visible cases (Matt). Signed-off-by:
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