- 02 Jan, 2020 2 commits
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Masahiro Yamada authored
I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
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Jani Nikula authored
Merge branch 'ib-pinctrl-unreg-mappings' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into drm-intel-next-queued Merge pincntrl to unblock further i915 changes on top by Hans. Signed-off-by:
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- 01 Jan, 2020 3 commits
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Chris Wilson authored
We use the global device inode, shared amongst all files, and not the user's device filp to provide the backing storage for the mmap. The vma->vm_file provides a redundant reference that breaks existing expected behaviour that closing the user's device fd will release the resources bound to it, if a mmap persists. (Even without the vma->vm_file, the mmap will persist past the user's fd as the storage is bound to the device, i.e. our reference is on the object not file.) Fixes: cc662126 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET") Closes: https://gitlab.freedesktop.org/drm/intel/issues/919Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200101141007.755429-1-chris@chris-wilson.co.uk
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Matt Roper authored
The workaround database now indicates we need to disable psdunit clock gating as well. v3: - Rebase on top of other workarounds that have landed. - Restrict cc:stable tag to 5.2+ since that's when ICL was first officially supported. Bspec: 32354 Bspec: 33450 Bspec: 33451 Suggested-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: stable@vger.kernel.org # v5.2+ Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Acked-by:
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Chris Wilson authored
The coarse power gating was disabled as part of commit 2248a283 ("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover from the context corruption; the power gating itself has no direct impact on the RC6 context corruption. However, that recovery scheme was never implemented due to difficult corner cases, and so we no longer need to keep the power gating disabled. Fixes: 2248a283 ("drm/i915/gen8+: Add RC6 CTX corruption WA") Closes: https://gitlab.freedesktop.org/drm/intel/issues/846Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231122708.4025916-1-chris@chris-wilson.co.uk
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- 31 Dec, 2019 3 commits
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Abdiel Janulgue authored
Provide a way to set the PTE within apply_page_range for discontiguous objects in addition to the existing method of just incrementing the pfn for a page range. Fixes: cc662126 ("drm/i915: Introduce DRM_I915_GEM_MMAP_OFFSET") Signed-off-by:
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Matt Roper authored
Our usual i915 convention is to assume that future platforms will follow the same behavior as the latest platform of today. The VDBOX/SFC capabilities described here don't seem like something that should be specific to TGL, so let's future-proof by making the test apply to all gen12+ platforms. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com>
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Chris Wilson authored
A small tweak to flush then invalidate appears to improve the reliability of ppGTT switches on Ivybridge -- but does not improve hsw/vlv bcs reliability. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231120857.4014900-1-chris@chris-wilson.co.uk
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- 30 Dec, 2019 13 commits
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Chris Wilson authored
Do not reset RING_BB_STATE, leaving it to the default state value. This prevents bdw/bsw from getting confused when executing batches from the GGTT. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
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Chris Wilson authored
When cleaning up the mock device, remember to flush the context worker to free the residual GEM contexts before shutting down the device. Closes: https://gitlab.freedesktop.org/drm/intel/issues/802Signed-off-by:
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Chris Wilson authored
Only restore valid resource streamer state from the context image, i.e. avoid restoring if we know the image is invalid. Closes: https://gitlab.freedesktop.org/drm/intel/issues/446Signed-off-by:
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Chris Wilson authored
Mark the GT as wedged so that we are not tempted to use it prior to initialisation. Signed-off-by:
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Chris Wilson authored
Assume that the HW starts off with tag 0 "active" and so avoid using tag 0 for our own first ELSP submission. Signed-off-by:
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Chris Wilson authored
Set up the RING_MI_MODE in new contexts to clear the STOP_RING bit, just in case they find it still set after a reset (as they are the first contexts to be run). Signed-off-by:
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Hans de Goede authored
Currently only the drivers/pinctrl/devicetree.c code allows registering pinctrl-mappings which may later be unregistered, all other mappings are assumed to be permanent. Non-dt platforms may also want to register pinctrl mappings from code which is build as a module, which requires being able to unregister the mapping when the module is unloaded to avoid dangling pointers. To allow unregistering the mappings the devicetree code uses 2 internal functions: pinctrl_register_map and pinctrl_unregister_map. pinctrl_register_map allows the devicetree code to tell the core to not memdup the mappings as it retains ownership of them and pinctrl_unregister_map does the unregistering, note this only works when the mappings where not memdupped. The only code relying on the memdup/shallow-copy done by pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit replaces the __initdata with const, so that the shallow-copy is no longer necessary. After that we can get rid of the internal pinctrl_unregister_map function and just use pinctrl_register_mappings directly everywhere. This commit also renames pinctrl_unregister_map to pinctrl_unregister_mappings so that its naming matches its pinctrl_register_mappings counter-part and exports it. Together these 2 changes will allow non-dt platform code to register pinctrl-mappings from modules without breaking things on module unload (as they can now unregister the mapping on unload). Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20191216205122.1850923-2-hdegoede@redhat.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Chris Wilson authored
In the selftests, we may feed very long lists of blocks to be freed on culmination of the tests. This coupled with kasan and other malloc-tracing can make the kmem_cache_free() operation time consuming, and doing many of those trigger soft lockup warnings. Break the list up with a cond_resched(). Signed-off-by:
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Manasi Navare authored
While clearing the Ports ync mode enable and master select bits we need to clear the register completely instead of using disable masks v3: * Remove reg variable (Matt) v2: * Just write 0 to the reg (Ville) * Rebase Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Fixes: 51528afe ("drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence") Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228031204.10189-3-manasi.d.navare@intel.com
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Manasi Navare authored
Add an extra check before making master slave assignments for tiled displays to make sure we make these assignments only if all tiled connectors are present. If not then initialize the state to defaults so it does a normal non tiled modeset without transcoder port sync. v4: deafulat port sync values in prepare_cleared_state (Ville) v3: * Default master trans to INVALID to avoid pipe mismatch v2: * Rename icl_add_sync_mode_crtcs * Move this function just before .compute_config hook * Check if DP before master slave assignments (Ville) Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Manasi Navare authored
In case of tiled displays, all the tiles are linke dto each other for transcoder port sync. So in intel_atomic_check() we need to make sure that we add all the tiles to the modeset and if one of the tiles needs a full modeset then mark all other tiles for a full modeset. We also need to force modeset for all synced crtcs after fastset check. v6: * Add comments about why we do not call drm_atomic_helper_check_modeset (Matt) * Add FIXME for a corner case where tile info might vanish (Matt) v5: * Rebase v4: * Fix logic for modeset_synced_crtcs (Ville) v3: * Add tile checks only for Gen >11 v2: * Change crtc_state scope, remove tile_grp_id (Ville) * Use intel_connector_needs_modeset() (Ville) * Add modeset_synced_crtcs (Ville) * Make sure synced crtcs are forced full modeset after fastset check (Ville) Suggested-by:
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Manasi Navare authored
In case of tiled displays, if we hotplug just one connector, fbcon currently just selects the preferred mode and if it is tiled mode then that becomes a problem if rest of the tiles are not present. So in the fbdev driver on hotplug when we probe the client modeset, if we dont find all the connectors for all tiles, then on a connector with one tile, just fallback to the first available non tiled mode to display over a single connector. On the hotplug of the consecutive tiled connectors, if the tiled mode no longer exists because of fbcon size limitation, then return no modes for consecutive tiles but retain the non tiled mode on the 0th tile. Use the same logic in case of connected boot case as well. This has been tested with Dell UP328K tiled monitor. v3: * Check Num tiled conns that are connected (Manasi) v2: * Set the modes on consecutive hotplugged tiles to no mode if tiled mode is pruned (Dave) v1: * Just handle the 1st connector hotplug case * v1 Reviewed-by: Dave Airlie <airlied@redhat.com> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5Suggested-by:
Dave Airlie <airlied@redhat.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by:
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Manasi Navare authored
DRM Fb driver expects multiple CRTCs if it sees connector->has_tile is set, but we need to handle tile support and look for multiple CRTCs only for the modes that match the tile size. The other modes should be able to be displayed without tile support or uisng single CRTC. This patch adds the check to match the tile size with requested mode to handle the tile support. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by:
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- 28 Dec, 2019 12 commits
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts tigerlake to tgl where appropriate. Signed-off-by:
Jani Nikula <jani.nikula@linux.intel.com> Acked-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts ivybridge to ivb where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts broadwell to bdw where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts ironlake to ilk where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts icelake to icl where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts cannonlake to cnl where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts skylake to skl where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts haswell to hsw where appropriate. Signed-off-by:
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Lucas De Marchi authored
We are currently using a mix of platform name and acronym to name the functions. Let's prefer the acronym as it should be clear what platform it's about and it's shorter, so it doesn't go over 80 columns in a few cases. This converts pineview to pnv where appropriate. v2: Add missing conversions in intel_pm.c (Matt Roper). While at it, fix missing blank lines between structs that would otherwise trigger checkpatch errors (Lucas) Signed-off-by:
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Lucas De Marchi authored
Drop the intel prefix since all these structs are static and prefer using the 3-letter prefix for each platform. v2: also remove gen from the device info (Ville) Signed-off-by:
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Lukasz Fiedorowicz authored
Debugfs i915_gem_object is extended to enable the IGTs to detect the LMEM's availability and the total size of LMEM. v2: READ_ONCE is used [Chris] v3: %pa is used for printing the resource [Chris] v4: All regions' details added to debugfs [Chris] v5: Macro for_each_mem_region added name is initialized at region init [Chris] Signed-off-by:Lukasz Fiedorowicz <lukasz.fiedorowicz@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
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Chris Wilson authored
In commit d03b224f ("drm/i915/gt: Apply sanitiization just before resume") the GT sanitization was pulled into the resume path as we need to know the backend in order to do a full reset prior to resume. However, it is still imperative that we scrub existing GPU state before clobbering in our early setup, so restore a minimal GPU reset at the start of our init sequence. Fixes: d03b224f ("drm/i915/gt: Apply sanitiization just before resume") Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191228111255.3086901-1-chris@chris-wilson.co.uk
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- 27 Dec, 2019 4 commits
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Matt Roper authored
Although the workaround number and description are the same, the vsunit clock gate disable bit has moved to a new register and location on gen12. Bspec: 52890 Bspec: 52758 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Matt Roper authored
Workaround database indicates we should disable clock gating of both the vsunit and hsunit. Bspec: 33450 Bspec: 33451 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Matt Roper authored
WaDisableDARBFClkGating, now known as Wa_14010480278, has been added to the workaround tables for ICL, EHL, and TGL so we need to extend our platform test accordingly. Bspec: 33450 Bspec: 33451 Bspec: 52890 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Chris Wilson authored
If gt initialisation failed, we are left with no engines to use for coherency testing. Currently we bug out, which makes the actual error, so fail more gracefully instead. Closes: https://gitlab.freedesktop.org/drm/intel/issues/896Signed-off-by:
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- 26 Dec, 2019 3 commits
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Chris Wilson authored
Do not expose incomplete engines to the user after we fail to setup the GT. Fixes: e6ba7648 ("drm/i915: Remove i915->kernel_context") Signed-off-by:
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Chris Wilson authored
Bring sanitization completely underneath the umbrella of intel_gt, and perform it exclusively after suspend and before the next resume. Signed-off-by:
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Chris Wilson authored
In record defaults, if we emit a request we expect a context switck on parking. We need take no further action, so don't even mess with the low level engine->serial where it is not warranted. Signed-off-by:
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