- 24 Sep, 2014 40 commits
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Damien Lespiau authored
Gen9 is different enough (for instance, fetching the memory latency values is different from ILK+) to not take the HAS_PCH_SPLIT() branch, so let's prefer a clean separation. v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
It can be handy to get the number of planes for this pipe, ie including the primary plane to loop over them. Introduce a little function to do so. Reviewed-by:
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Damien Lespiau authored
This can be useful to declare structures around pipes and planes and don't have to go back auditing the code if the next platorm bump that number. Reviewed-by:
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Damien Lespiau authored
Let's put to good use the new PLANE_CTL macros. Reviewed-by:
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Damien Lespiau authored
SKL Uses the same hardware for all planes now, so called "universal" planes. Ie both the primary planes and sprite planes share the same logic. This patch implements the drm_plane vfuncs for "sprites" ie planes that aren't the primary plane. v2: Couple of fixes: - Actually enabled the planes and fix the plane number Reviewed-by:
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Damien Lespiau authored
On Skylake, we use plane1 as primary plane and plane2/3 as sprite planes. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Reviewed-by: -
Damien Lespiau authored
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Damien Lespiau authored
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Damien Lespiau authored
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Satheeshakrishna M authored
This patch implements detection of SPT and SPT-LP PCH devices. v2: Added HAS_PCH_SPT macro Reviewed-by:
Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by:
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Damien Lespiau authored
To accomodate the extra planes, the bit definitions were shuffled around a bit. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v3: Rebase after yet another change int that area (done with wiggle) Reviewed-by: -
Satheeshakrishna M authored
Extending BDW implementation to gen9. Pipe B/C interrupt restoration after exiting LPSP. v2: Fix minor rebasing conflict. Reviewed-by:
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Satheeshakrishna M authored
Extending the BDW backlight implementation to SKL. Reviewed-by:
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Satheeshakrishna M authored
Set gen 9 function pointers for eld write and global resource. Implementation remains same as HSW. v2: Rebase on top of Sonika's untangling of the if/else ladder (Damien) Reviewed-by:
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Satheeshakrishna M authored
Pipe misc programming in gen9 is similar to BDW. Extending the BDW implementation to gen 9. Reviewed-by:
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Damien Lespiau authored
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com Signed-off-by:
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Damien Lespiau authored
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Damien Lespiau authored
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Damien Lespiau authored
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Damien Lespiau authored
gen9 uses very similar memory management to what gen8 has. Just follow the flow. v2: Fix trivial conflict (Damien) Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Damien Lespiau authored
Skylake doesn't use the pre-charge field now, but, instead, we need to specify the total number of SYNC pulses for the SYNC phase (pre-charge + SYNC pattern pules). Let's use the default value (32) for that. v3: increase DP AUX TX timeout as 400us is not to be used on SKL apparently (Jesse). Reviewed-by: -
Damien Lespiau authored
We need to provide a vfunc that will make the code in intel_dp_aux_ch() loop once to start the AUX transaction. The return value (clock divider) is unused on SKL, so just return 1. Reviewed-by:
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Damien Lespiau authored
Temporary plug a BUG() while waiting for a better solution. See: http://lists.freedesktop.org/archives/intel-gfx/2014-January/038132.html However Chris was looking at cleaning-up this as well, so went for the easy intermediate solution instead. Reviewed-by:
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Damien Lespiau authored
Skylake introduces new stolen memory sizes starting at 0xf0 (4MB) and growing by 4MB increments from there. v2: Rebase on top of the early-quirk changes from Ville. v3: Rebase on top of the PCI_IDS/IDS macro rename Reviewed-by:
Thomas Wood <thomas.wood@intel.com> Signed-off-by:
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Damien Lespiau authored
So we can apply the old aux_ctl = dp_ctl + 0x10 rule again. Reviewed-by:
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Damien Lespiau authored
They are similar to Haswell. v2: Rebased on top of drm-intel-nightly v3: Rebased on top of Sonika's DP train defines renaming Reviewed-by:
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Damien Lespiau authored
A couple of things have changed compared to Broadwell: - Entry 9 is used for eDP - No more FDI v2: Update the translation values to latest specs. v3: Rebase on top of the BDW HDMI translation patch v4: Remove the low voltage edp tables, Rebase on top of the patch not writing the HDMI entry on eDP/FDI DDIs (Satheesh, Paulo). v5: Apply the / 2 fix for the number of HDMI entries (Satheesh) v6: Rebase on top of Jani's clean up for the DDI_BUF_TRANS tables v7: Restore the commit message that was mangled by error Reviewed-by: -
Damien Lespiau authored
When the platform doesn't have a FDI link, don't try to read out the state of a potential PCH transcoder. Reviewed-by:
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Damien Lespiau authored
v2: Rebase on top of the intel_crt_present() addition v3: Fix rebase error (we were patching the wrong function) Reviewed-by:
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Damien Lespiau authored
Skylake makes primary planes the same as sprite planes and call the result "universal planes". This commit emulates a primary plane with plane 0, taking the opportunity to redefine primary and sprite registers to be identical now that the underlying hardware is. It also makes sense as plenty of fields have changed. v2: Rebase on top of the vma code. v3: Follow upstream evolution: - Drop return values. - Remove pipe checks since redudant and BUG instead. - Remove tiling checks and BUG instead. - Drop commented out DISP_MODIFY usage. v4: s/plane/primary_plane/ v5: Misc fixes: - Fix the fields we need to clear up - Disable trickle feed - Correctly use PLANE_OFFSET for the panning v6: (Jesse) Use pipe src size when programming plane size. This makes cloned configs work correctly w/o the use of a panel fitter. v7: Rebase on top of Ville's rmw elimination series v8: Remove clearing the trickle feed bit now that we don't do a RMW (Rodrigo, Damien) Add a comment about the stride unit (Rodrigo) Reviewed-by: -
Robert Beckett authored
Fix ARB_MODE register read for gen >= 8 in i915_swizzle_info Reviewed-by:
Robert Beckett <robert.beckett@intel.com> Signed-off-by:
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Damien Lespiau authored
v2: Also align X tiled fbs to 256KB (Thomas) Reviewed-by:
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Imre Deak authored
The following sets the AsyncFlip performance mode for everything above Gen6: commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jan 20 16:11:20 2013 +0000 drm/i915: Disable AsyncFlip performance optimisations Starting from Gen9 the MI_MODE register layout changes and doesn't include the above bit. Reviewed-by:Imre Deak <imre.deak@intel.com> Signed-off-by:
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Damien Lespiau authored
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Damien Lespiau authored
v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by:
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Damien Lespiau authored
v2: Rebased on top of the i915_gpu_error.c extraction. Reviewed-by:
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Daisy Sun authored
Enable FBC feature on Skylake Issue: VIZ-3788 Reviewed-by:
Daisy Sun <daisy.sun@intel.com> Signed-off-by:
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Satheeshakrishna M authored
Adding new macro IS_SKYLAKE for skylake specific implementation. Reviewed-by:
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Damien Lespiau authored
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Damien Lespiau authored
v2: Squash in 2nd patch from Damien for more ids (Daniel) v3: info->has*ring -> info->ring_mask conversion. Also add VEBOX support. v4: Fold in update from Damien v5: Rebase and add GEN_DEFAULT_PIPEOFFSETS v6: Add more PCI ID (Vandana) v7: Rebase and add IVB_CURSOR_OFFSETS v8: Renamed the macro from _PCI_IDS to _IDS for consistency Reviewed-by:
Vandana Kannan <vandana.kannan@intel.com> Signed-off-by:
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