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  1. 28 Jan, 2015 11 commits
  3. 27 Jan, 2015 13 commits
  5. 25 Jan, 2015 4 commits
  7. 22 Jan, 2015 5 commits
  9. 20 Jan, 2015 7 commits
    • Oleksij Rempel's avatar
      ARM: clk: add clk-asm9260 driver · ec6415dc
      Oleksij Rempel authored 
      Provide CLK support for Alphascale ASM9260 SoC.
Signed-off-by: default avatarOleksij Rempel <linux@rempel-privat.de>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      ec6415dc
    • Peter Griffin's avatar
      clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate · edc30077
      Peter Griffin authored 
      Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      edc30077
    • Tang Yuantian's avatar
      clk: ppc-corenet: rename driver to clk-qoriq · 93a17c05
      Tang Yuantian authored 
      Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      93a17c05
    • Tang Yuantian's avatar
      clock: redefine variable clocks_per_pll as a struct member · 57bfd7ee
      Tang Yuantian authored 
      redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      57bfd7ee
    • Michael Turquette's avatar
      Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk-next · 11144283
      Michael Turquette authored 
      - Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.
      11144283
    • Tony Lindgren's avatar
      clk: ti: Initialize clocks for dm816x · 1a34275d
      Tony Lindgren authored 
      The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      1a34275d
    • Tony Lindgren's avatar
      clk: ti: Add support for FAPLL on dm816x · 163152cb
      Tony Lindgren authored 
      On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      163152cb
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