1. 21 Jun, 2017 2 commits
    • Ben Greear's avatar
      ath10k: configure rxnss_override for QCA9984 · cc914a55
      Ben Greear authored
      QCA9984 hardware can do 4x4 at 80Mhz, but only 2x2 at 160Mhz.
      
      First, report this to user-space by setting the max-tx-speed
      and max-rx-speed vht capabilities.
      
      Second, if the peer rx-speed is configured, and if we
      are in 160 or 80+80 mode, and the peer rx-speed matches
      the max speed for 2x2 or 1x1 at 160Mhz (long guard interval),
      then use that info to set the peer_bw_rxnss_override appropriately.
      
      Without this, a 9984 firmware will not use 2x2 ratesets when
      transmitting to peer (it will be stuck at 1x1), because
      the firmware would not have configured the rxnss_override.
      Signed-off-by: default avatarBen Greear <greearb@candelatech.com>
      [sven.eckelmann@openmesh.com: rebase, cleanup, drop 160Mhz workaround cleanup]
      Signed-off-by: default avatarSven Eckelmann <sven.eckelmann@openmesh.com>
      [kvalo@qca.qualcomm.com: use hw_params, rename the title]
      Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
      cc914a55
    • Ben Greear's avatar
      ath10k: use complete VHT chan width for 160MHz workaround · e509e594
      Ben Greear authored
      The ath10k firmware doesn't announce its VHT channel width capabilities in
      the vht_cap information from the "service ready event" arguments. The
      driver must therefore check whether the 160MHz short GI bit is set and
      whether the driver still doesn't set the bits for the 160/80+80 MHz
      capabilities.
      
      The two bits for the channel width are a two bit integer and not two
      separate bits which cannot be parsed without the knowledge of the other
      bit. Using IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ (b10..) as a
      mask for this task doesn't make any sense. The correct mask for the VHT
      channel width should be used instead to make this check more readable.
      Signed-off-by: default avatarBen Greear <greearb@candelatech.com>
      [sven.eckelmann@openmesh.com: separate 160Mhz workaround cleanup, add commit
       message]
      Signed-off-by: default avatarSven Eckelmann <sven.eckelmann@openmesh.com>
      Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
      e509e594
  2. 16 Jun, 2017 3 commits
  3. 01 Jun, 2017 5 commits
  4. 31 May, 2017 1 commit
    • Adrian Chadd's avatar
      ath10k: go back to using dma_alloc_coherent() for firmware scratch memory · 79e68821
      Adrian Chadd authored
      This reverts commit b0578865 ("ath10k: do not use coherent memory for
      allocated device memory chunks") in 2015 which converted this allocation from
      dma_map_coherent() to kzalloc() / dma_map_single().
      
      The current problem manifests when using later model NICs with larger
      (>700KiB) scratch spaces in memory.  Although the kzalloc call
      succeeds, the software IOMMU TLB code (via dma_map_single()) panics
      because it can't find 700KiB of linear physmem bounce buffers for DMA.
      Now, this is a bit of a silly failure mode for the dma map API,
      but it's what we currently have to play with.
      
      In these cases, doing kzalloc() works fine, but the dma_map_single()
      call fails.
      
      After chatting with Linus briefly about this, it indeed should be
      using dma_alloc_coherent() for doing larger device memory allocation
      that requires some kind of physical address mapping.
      
      You're not supposed to be using kzalloc and dma_map_* calls for
      large memory regions, and I'm guessing not for long-held mappings
      either.  Typically dma mappings should be temporary for DMA,
      not long held like these.
      
      Now, since hopefully the major annoying underlying problem has also been
      addressed (ie, ath10k is no longer tears down all of these allocations
      and reallocates them every time the vdevs are brought down) fragmentation
      should stop being such a touchy issue.  If it is though, using
      dma_alloc_coherent() use gets us access to the CMB APIs too relatively
      easily and ideally we would be allocating memory early in boot for
      exactly these reasons.
      Signed-off-by: default avatarAdrian Chadd <adrian@FreeBSD.org>
      Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
      79e68821
  5. 23 May, 2017 6 commits
  6. 19 May, 2017 20 commits
  7. 18 May, 2017 3 commits