- 20 May, 2016 40 commits
-
-
git://github.com/skeggsb/linuxDave Airlie authored
Nothing too exciting here, there's a larger chunk of work that still needs more testing but not likely to get that done today - so - here's the rest of it. Assuming nothing else goes horribly wrong, I should be able to send the rest Monday if it isn't too late.... Changes: - Improvements to power sensor support - Initial attempt at GM108 support - Minor fixes to GR init + ucode - Make use of topology information (provided by the GPU) in various places, should at least fix some fault recovery issues and engine/runlist mapping confusion on newer GPUs. * 'linux-4.7' of git://github.com/skeggsb/linux: (51 commits) drm/nouveau/gr/gf100-: fix race condition in fecs/gpccs ucode drm/nouveau/core: recognise GM108 chipsets drm/nouveau/gr/gm107-: fix touching non-existent ppcs in attrib cb setup drm/nouveau/gr/gk104-: share implementation of ppc exception init drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctx drm/nouveau/bios/pll: check BIT table version before trying to parse it drm/nouveau/bios/pll: prevent oops when limits table can't be parsed drm/nouveau/volt/gk104: round up in gk104_volt_set drm/nouveau/fb/gm200: setup mmu debug buffer registers at init() drm/nouveau/fb/gk20a,gm20b: setup mmu debug buffer registers at init() drm/nouveau/fb/gf100-: allocate mmu debug buffers drm/nouveau/fb: allow chipset-specific actions for oneinit() drm/nouveau/gr/gm200-: fix bad hardcoding of a max-tpcs-per-gpc value drm/nouveau/gr/gm200-: rop count == ltc count drm/nouveau/gr/gm200: modify the mask when copying mmu settings from fb drm/nouveau/gr/gm200: move some code into init_gpc_mmu() hook drm/nouveau/gr/gm200: make generate_main() static drm/nouveau/gr/gf100-: abstract fetching rop count drm/nouveau/gr/gf100-: rename magic_not_rop_nr to screen_tile_row_offset drm/nouveau/gr/gf100-: remove hardcoded idle_timeout values ...
-
Ben Skeggs authored
This is a simplied version of the fix by Roy in fdo#93629. While this doesn't appear to fix the issues for the users in that report, it's a real issue that deserves to be resolved. Reported-by:
Roy Spliet <rspliet@eclipso.eu> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Also removes an XXX; according to nvgpu headers the field is called NV_PGRAPH_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3, so, apparently not some magic we need to figure out :) Signed-off-by: -
Ben Skeggs authored
This was really inconsistent, some implementations could touch PPCs that didn't exist, others neglected to touch ones that did. Signed-off-by: -
Ben Skeggs authored
Matches newer RM. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Karol Herbst authored
We always want a equal or higher voltage than the requested ones, otherwise nouveau undervolts. Signed-off-by:
Karol Herbst <nouveau@karolherbst.de> Signed-off-by:
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Later chipsets require setting this up both in FB and GR, so let's just move the allocation to FB. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Appears to more closely match what RM does. For GM20B, now also copying bit 12 from NV_PFB_MMU_CTRL as upcoming changes will require it. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
These are specified by PTOP on Maxwell GPUs. Signed-off-by: -
Ben Skeggs authored
It appears these don't map to PBDMAs (at least on Kepler, it may or may be valid for Fermi - this hasn't been checked), but to runlists. This drops the NVKM_ENGINE_FIFO data from the entries too, as resetting all of PFIFO is *not* the way to handle such faults. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
These are now specified directly in the MC subdev. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Engine fields have been removed, as they're specified by PTOP. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
With the addition of PTOP-specified reset bits, it makes more sense to move the definitions here rather than in individual subdev implementations. Signed-off-by:
-
