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- 22 Sep, 2016 2 commits
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Andrew Lunn authored
We are soon going to run out of flag bits on 32bit systems. Convert to unsigned long long. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Andrew Lunn authored
There is a device coming soon which places its port registers somewhere different to all other Marvell switches supported so far. Add helper functions for reading/writing port registers, making it easier to handle this new device. Signed-off-by:
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- 06 Sep, 2016 1 commit
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Vivien Didelot authored
Marvell chips are composed of multiple SMI devices. One of them at address 0x1C is called Global2. It provides an extended set of registers, used for interrupt control, EEPROM access, indirect PHY access (to bypass the PHY Polling Unit) and cross-chip related setup. Most chips have it, but some others don't (older ones such as 6060). Now that its related code is isolated in mv88e6xxx_g2_* functions, move it to its own global2.c file, making most of its setup code static. Document each registers in the meantime. Its compilation can be later avoided for chips without such registers. Signed-off-by:
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- 23 Aug, 2016 1 commit
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Andrew Lunn authored
Older chips only support DSA tagging on the CPU port. New devices support both DSA and EDSA. The driver needs to tell the core the tag protocol to use, and configure the switch for what is available. Signed-off-by:
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- 15 Aug, 2016 4 commits
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Vivien Didelot authored
Add mv88e6xxx_phy_page_{read,write} routines and use them to access the SerDes PHY device registers. Signed-off-by: -
Vivien Didelot authored
Old chips use a direct access to the PHY devices registers. Next chips have a PHY Polling Unit (PPU) which needs to be disabled before accessing PHY registers. Newer chips have an indirect access to the PHY devices so that disabling the PPU is not necessary. Introduce a new phy_ops structure in the chip to describe the required PHY access routines. Signed-off-by:
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Vivien Didelot authored
Describe the presence of the Global2 SMI PHY registers, used to indirectly access the internal SMI devices registers on some chips. Also temporarily forward declare mv88e6xxx_g2_smi_phy_{read,write} to use them in mv88e6xxx_mdio_{read,write}_indirect, before getting rid of the later. Signed-off-by: -
Vivien Didelot authored
Add flags to describe the presence of SMI Command and Data registers used to indirectly access internal SMI devices registers when the switch SMI address is not zero. Signed-off-by:
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- 21 Jul, 2016 2 commits
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Vivien Didelot authored
The 6352 family of switches and compatibles provide a 8-bit address and 16-bit data access to an optional EEPROM. Newer chip such as the 6390 family slightly changed the access to 16-bit address and 8-bit data. This commit cleans up the EEPROM access code for 16-bit access and makes it easy to eventually introduce future support for 8-bit access. Here's a list of notable changes brought by this patch: - provide Global2 unlocked helpers for EEPROM commands - remove eeprom_mutex, only reg_lock is necessary for driver functions - eeprom_len is 0 for chip without EEPROM, so return it directly - the Running bit must be 0 before r/w, so wait for Busy *and* Running - remove now unused mv88e6xxx_wait and mv88e6xxx_reg_write - other than that, the logic (in _{get,set}_eeprom16) didn't change Chips with an 8-bit EEPROM access will require to implement the 8-suffixed variant of G2 helpers and the related flag: #define MV88E6XXX_FLAGS_EEPROM8 \ (MV88E6XXX_FLAG_G2_EEPROM_CMD | \ MV88E6XXX_FLAG_G2_EEPROM_ADDR) Signed-off-by: -
Vivien Didelot authored
Only reg_lock is necessary now and phy_mutex is dead. Remove it. Signed-off-by:
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- 20 Jul, 2016 9 commits
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Vivien Didelot authored
All Marvell switch chips from (88E6060 to 88E6390) have a ATU Control register containing bits 11:4 to configure an ATU Age Time quotient. However the coefficient used to calculate the ATU Age Time vary with the models. E.g. 88E6060, 88E6352 and 88E6390 use respectively 16, 15 and 3.75 seconds. Add a age_time_coeff to the info structure to handle this and a Global 1 helper to set the default age time of 5 minutes in the setup code. Signed-off-by:
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Vivien Didelot authored
Add capability flags to describe the presence of Ingress Rate Limit unit registers and an helper function to clear it. In the meantime, fix a few harmless issues: - 6185 and 6095 don't have such registers (reserved) - the previous code didn't wait for the IRL operation to complete Signed-off-by:
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Vivien Didelot authored
Add flags and helpers to describe the presence of Priority Override Table (POT) related registers and simplify the setup of Global 2. Signed-off-by:
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Vivien Didelot authored
Add flags to describe the presence of Cross-chip Port VLAN Table (PVT) related registers and simplify the setup of Global 2. Signed-off-by:
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Vivien Didelot authored
Switches such as 88E6185 as 3 Switch MAC registers in Global 1. Newer chips such as 88E6352 have freed these registers in favor of an indirect access in a Switch MAC/WoL/WoF register in Global 2. Explicit this difference with G1 and G2 helpers and flags. Also, note that this indirect access is a single-register which doesn't require to wait for the operation to complete (like Switch MAC, Trunk Mapping, etc.), in contrary to multi-registers indirect accesses with several operations and a busy bit. Signed-off-by:
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Vivien Didelot authored
Some switches provide a Rsvd2CPU mechanism used to choose which of the 16 reserved multicast destination addresses matching 01:80:c2:00:00:0x should be considered as MGMT and thus forwarded to the CPU port. Other switches extend this mechanism to also configure as MGMT the additional 16 reserved multicast addresses matching 01:80:c2:00:00:2x. This mechanism is exposed via two registers in Global 2, and an Rsvd2CPU enable bit in the management register. Newer chip (such as 88E6390) has replaced these registers with a new indirect MGMT mechanism in Global 1. The patch adds two MV88E6XXX_FLAG_G2_MGMT_EN_{0,2}X flags to describe the presence of these Global 2 registers. If 88E6390 support is added, a MV88E6XXX_FLAG_G1_MGMT_CTRL flag will be needed to setup Rsvd2CPU. Note: all switches still support in parallel the ATU Load operation with an MGMT Entry State to forward such frames in a less convenient way. Signed-off-by: -
Vivien Didelot authored
The Trunk Mask and Trunk Mapping registers are two Global 2 indirect accesses to trunking configuration. Add helpers for these tables and simplify the Global 2 setup. Signed-off-by:
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Vivien Didelot authored
Separate the setup of Global 1 and Global 2 internal SMI devices and add a flag to describe the presence of this second registers set. Also rearrange the G1 setup in the registers order. Signed-off-by:
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Vivien Didelot authored
All 88E6xxx Marvell switches (even the old not supported yet 88E6060) have at least an ATU, per-port STP states and VLAN map, to run basic switch functions such as Spanning Tree and port based VLANs. Get rid of the related MV88E6XXX_FLAG_{ATU,PORTSTATE,VLANTABLE} flags, as they are defaults to every chip. This enables STP on 6185 and removes many inconsistencies on others. Signed-off-by:
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- 25 Jun, 2016 2 commits
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Vivien Didelot authored
With the upcoming support for cross-chip operations, it will be hard to distinguish portions of code supporting a single-chip or a switch fabric of interconnected chips. Make the code clearer now, by renaming the mv88e6xxx_priv_state chip structure to mv88e6xxx_chip. This patch brings no functional changes. Signed-off-by:
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Vivien Didelot authored
With the upcoming support for cross-chip operations and other mv88e6xxx enhancements, new files will be added. Similarly to mlxsw or b53, move mv88e6xxx files into their own folder. In the meantime, update the MAINTAINERS entry to please checkpatch.pl, by replacing the invalid 88E6352 entry with 88E6XXX, maintained by Andrew and myself. Signed-off-by:
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- 21 Jun, 2016 3 commits
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Vivien Didelot authored
When the SMI address of the switch chip is zero, the chip assumes to be the only one on the SMI master bus and thus responds to all its known SMI devices addresses (port registers, Global2, etc.) When its SMI address is not zero, some chips (e.g. 88E6352) use an indirect access through two SMI Command and Data registers. Other models (e.g. 88E6060) using less than 16 internal SMI addresses always use a direct access. Add a capability flag to describe chips supporting the (indirect) Multi-chip Addressing Mode, and a low-level API to access the registers via SMI. Other accesses (like Ethernet management frames) may be added later. Signed-off-by:
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Vivien Didelot authored
The switch ID is located at address 0x3 of every Port Registers bank. But not all Marvell switches have their Port Registers SMI Addresses starting at 0x10. 88E6060 starts at 0x8 and 88E6390 starts at 0x0. Add this data in the info structure and use it in the detection code. Signed-off-by:
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Vivien Didelot authored
The chip smi_mutex mutex is used to protect the access to the internal switch registers, not only the Multi-chip Addressing Mode, as commented. Since we will isolate SMI-specific pieces of code, avoid the confusion now by renaming smi_mutex to reg_lock. No functional changes here. Signed-off-by:
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- 04 Jun, 2016 1 commit
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Andrew Lunn authored
Have the switch driver register its own MDIO bus. This allows for an mdio property in the device tree, with child nodes for phys, which can be referenced via phandles, etc. Signed-off-by:
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- 16 May, 2016 1 commit
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Vivien Didelot authored
Now that the bridge code defers the switchdev port state setting, there is no need to defer the port STP state change within the mv88e6xxx code. Thus get rid of the driver's bridge work code. This also fixes a race condition where the DSA layer assumes that the bridge code already set the unbridged port's STP state to Disabled before restoring the Forwarding state. As a consequence, this also fixes the FDB flush for the unbridged port which now correctly occurs during the Forwarding to Disabled transition. Fixes: 0bc05d58 ("switchdev: allow caller to explicitly request attr_set as deferred") Reported-by:
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- 11 May, 2016 3 commits
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Andrew Lunn authored
A switch can export an attached EEPROM using the standard ethtool API. However the switch itself cannot determine the size of the EEPROM, and multiple sizes are allowed. Thus a device tree property is supported to indicate the length of the EEPROM. Parse this property during device probe, and implement a callback function to retrieve it. Signed-off-by:
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Andrew Lunn authored
Resetting the switch is something the driver does, not the framework. So move the parsing of this property into the driver. There are no in kernel users of this property, so moving it does not break anything. There is however a board which will make use of this property making its way into the kernel. Signed-off-by:
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Vivien Didelot authored
Some switch models have a STU (per VLAN port state database). Add a new capability flag to switches info, instead of checking their family. Also if the 6165 family has an STU, it must have a VTU, so add the MV88E6XXX_FLAG_VTU to its family flags. Signed-off-by:
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- 09 May, 2016 11 commits
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Vivien Didelot authored
Now that all drivers support the same set of functions and the same setup code, drop every model-specific DSA switch driver and replace them with a common mv88e6xxx driver. This merges the info tables into one, removes the function exports, the model-specific files, and update the defconfigs. Signed-off-by:
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Vivien Didelot authored
Provide a shared mv88e6xxx_setup function to the drivers. Signed-off-by:
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Vivien Didelot authored
Every driver is calling mv88e6xxx_setup_global after mv88e6xxx_setup_common. Call the former in the latter. Signed-off-by:
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Vivien Didelot authored
Add a MV88E6XXX_FLAG_PPU_ACTIVE flag to describe how to reset the switch, and merge the reset call to the common setup code. Signed-off-by:
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Vivien Didelot authored
Add a MV88E6XXX_FLAG_ATU flag to identify switch models with an Address Translation Unit. Signed-off-by:
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Vivien Didelot authored
Add a MV88E6XXX_FLAG_VTU flag to indentify switch models with a VLAN Table Unit. Signed-off-by:
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Vivien Didelot authored
Add MV88E6XXX_FLAG_PORTSTATE and MV88E6XXX_FLAG_VLANTABLE flags to identify switch models with required 802.1D operations. Signed-off-by:
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Vivien Didelot authored
Add a MV88E6XXX_FLAG_EEE flag to describe switch models featuring Energy Efficient Ethernet. Use it to conditionally support such access in the common code. Signed-off-by:
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Vivien Didelot authored
Some switch models have a dedicated register for Switch MAC/WoF/WoL. This register, when present, is used to indirectly set the switch MAC address, instead of a direct write to 3 global registers. Identify this feature and share a common mv88e6xxx_set_addr function. Signed-off-by:
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Vivien Didelot authored
Add MV88E6XXX_FLAG_TEMP and MV88E6XXX_FLAG_TEMP_LIMIT flags to describe switch models featuring a temperature access. Use them to centralize the access to the temperature feature. Signed-off-by:
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Vivien Didelot authored
Add a MV88E6XXX_FLAG_EEPROM flag to describe switch models featuring an EEPROM and distribute the EEPROM access routines to all models. Signed-off-by:
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