1. 30 May, 2014 40 commits
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Rework SLB switching code · d8d164a9
      Alexander Graf authored
      On LPAR guest systems Linux enables the shadow SLB to indicate to the
      hypervisor a number of SLB entries that always have to be available.
      
      Today we go through this shadow SLB and disable all ESID's valid bits.
      However, pHyp doesn't like this approach very much and honors us with
      fancy machine checks.
      
      Fortunately the shadow SLB descriptor also has an entry that indicates
      the number of valid entries following. During the lifetime of a guest
      we can just swap that value to 0 and don't have to worry about the
      SLB restoration magic.
      
      While we're touching the code, let's also make it more readable (get
      rid of rldicl), allow it to deal with a dynamic number of bolted
      SLB entries and only do shadow SLB swizzling on LPAR systems.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      d8d164a9
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Use SLB entry 0 · 207438d4
      Alexander Graf authored
      We didn't make use of SLB entry 0 because ... of no good reason. SLB entry 0
      will always be used by the Linux linear SLB entry, so the fact that slbia
      does not invalidate it doesn't matter as we overwrite SLB 0 on exit anyway.
      
      Just enable use of SLB entry 0 for our shadow SLB code.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      207438d4
    • Paul Mackerras's avatar
      KVM: PPC: Book3S HV: Fix machine check delivery to guest · 000a25dd
      Paul Mackerras authored
      The code that delivered a machine check to the guest after handling
      it in real mode failed to load up r11 before calling kvmppc_msr_interrupt,
      which needs the old MSR value in r11 so it can see the transactional
      state there.  This adds the missing load.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      000a25dd
    • Paul Mackerras's avatar
      KVM: PPC: Book3S HV: Work around POWER8 performance monitor bugs · 9bc01a9b
      Paul Mackerras authored
      This adds workarounds for two hardware bugs in the POWER8 performance
      monitor unit (PMU), both related to interrupt generation.  The effect
      of these bugs is that PMU interrupts can get lost, leading to tools
      such as perf reporting fewer counts and samples than they should.
      
      The first bug relates to the PMAO (perf. mon. alert occurred) bit in
      MMCR0; setting it should cause an interrupt, but doesn't.  The other
      bug relates to the PMAE (perf. mon. alert enable) bit in MMCR0.
      Setting PMAE when a counter is negative and counter negative
      conditions are enabled to cause alerts should cause an alert, but
      doesn't.
      
      The workaround for the first bug is to create conditions where a
      counter will overflow, whenever we are about to restore a MMCR0
      value that has PMAO set (and PMAO_SYNC clear).  The workaround for
      the second bug is to freeze all counters using MMCR2 before reading
      MMCR0.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      9bc01a9b
    • Paul Mackerras's avatar
      KVM: PPC: Book3S HV: Make sure we don't miss dirty pages · 6c576e74
      Paul Mackerras authored
      Current, when testing whether a page is dirty (when constructing the
      bitmap for the KVM_GET_DIRTY_LOG ioctl), we test the C (changed) bit
      in the HPT entries mapping the page, and if it is 0, we consider the
      page to be clean.  However, the Power ISA doesn't require processors
      to set the C bit to 1 immediately when writing to a page, and in fact
      allows them to delay the writeback of the C bit until they receive a
      TLB invalidation for the page.  Thus it is possible that the page
      could be dirty and we miss it.
      
      Now, if there are vcpus running, this is not serious since the
      collection of the dirty log is racy already - some vcpu could dirty
      the page just after we check it.  But if there are no vcpus running we
      should return definitive results, in case we are in the final phase of
      migrating the guest.
      
      Also, if the permission bits in the HPTE don't allow writing, then we
      know that no CPU can set C.  If the HPTE was previously writable and
      the page was modified, any C bit writeback would have been flushed out
      by the tlbie that we did when changing the HPTE to read-only.
      
      Otherwise we need to do a TLB invalidation even if the C bit is 0, and
      then check the C bit.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      6c576e74
    • Alexey Kardashevskiy's avatar
      KVM: PPC: Book3S HV: Fix dirty map for hugepages · 687414be
      Alexey Kardashevskiy authored
      The dirty map that we construct for the KVM_GET_DIRTY_LOG ioctl has
      one bit per system page (4K/64K).  Currently, we only set one bit in
      the map for each HPT entry with the Change bit set, even if the HPT is
      for a large page (e.g., 16MB).  Userspace then considers only the
      first system page dirty, though in fact the guest may have modified
      anywhere in the large page.
      
      To fix this, we make kvm_test_clear_dirty() return the actual number
      of pages that are dirty (and rename it to kvm_test_clear_dirty_npages()
      to emphasize that that's what it returns).  In kvmppc_hv_get_dirty_log()
      we then set that many bits in the dirty map.
      Signed-off-by: default avatarAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      687414be
    • Paul Mackerras's avatar
      KVM: PPC: Book3S HV: Put huge-page HPTEs in rmap chain for base address · 1066f772
      Paul Mackerras authored
      Currently, when a huge page is faulted in for a guest, we select the
      rmap chain to insert the HPTE into based on the guest physical address
      that the guest tried to access.  Since there is an rmap chain for each
      system page, there are many rmap chains for the area covered by a huge
      page (e.g. 256 for 16MB pages when PAGE_SIZE = 64kB), and the huge-page
      HPTE could end up in any one of them.
      
      For consistency, and to make the huge-page HPTEs easier to find, we now
      put huge-page HPTEs in the rmap chain corresponding to the base address
      of the huge page.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      1066f772
    • Paul Mackerras's avatar
      KVM: PPC: Book3S HV: Fix check for running inside guest in global_invalidates() · 55765483
      Paul Mackerras authored
      The global_invalidates() function contains a check that is intended
      to tell whether we are currently executing in the context of a hypercall
      issued by the guest.  The reason is that the optimization of using a
      local TLB invalidate instruction is only valid in that context.  The
      check was testing local_paca->kvm_hstate.kvm_vcore, which gets set
      when entering the guest but no longer gets cleared when exiting the
      guest.  To fix this, we use the kvm_vcpu field instead, which does
      get cleared when exiting the guest, by the kvmppc_release_hwthread()
      calls inside kvmppc_run_core().
      
      The effect of having the check wrong was that when kvmppc_do_h_remove()
      got called from htab_write() on the destination machine during a
      migration, it cleared the current cpu's bit in kvm->arch.need_tlb_flush.
      This meant that when the guest started running in the destination VM,
      it may miss out on doing a complete TLB flush, and therefore may end
      up using stale TLB entries from a previous guest that used the same
      LPID value.
      
      This should make migration more reliable.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      55765483
    • Paul Mackerras's avatar
      KVM: PPC: Book3S: Move KVM_REG_PPC_WORT to an unused register number · e1d8a96d
      Paul Mackerras authored
      Commit b005255e ("KVM: PPC: Book3S HV: Context-switch new POWER8
      SPRs") added a definition of KVM_REG_PPC_WORT with the same register
      number as the existing KVM_REG_PPC_VRSAVE (though in fact the
      definitions are not identical because of the different register sizes.)
      
      For clarity, this moves KVM_REG_PPC_WORT to the next unused number,
      and also adds it to api.txt.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      e1d8a96d
    • Paul Mackerras's avatar
      KVM: PPC: Book3S: Add ONE_REG register names that were missed · 2f9c6943
      Paul Mackerras authored
      Commit 3b783474 ("KVM: PPC: Book3S HV: Reserve POWER8 space in get/set_one_reg") added definitions for several KVM_REG_PPC_* symbols
      but missed adding some to api.txt.  This adds them.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      2f9c6943
    • Alexander Graf's avatar
      KVM: PPC: Add CAP to indicate hcall fixes · f2e91042
      Alexander Graf authored
      We worked around some nasty KVM magic page hcall breakages:
      
        1) NX bit not honored, so ignore NX when we detect it
        2) LE guests swizzle hypercall instruction
      
      Without these fixes in place, there's no way it would make sense to expose kvm
      hypercalls to a guest. Chances are immensely high it would trip over and break.
      
      So add a new CAP that gives user space a hint that we have workarounds for the
      bugs above in place. It can use those as hint to disable PV hypercalls when
      the guest CPU is anything POWER7 or higher and the host does not have fixes
      in place.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f2e91042
    • Alexander Graf's avatar
      KVM: PPC: MPIC: Reset IRQ source private members · aae65596
      Alexander Graf authored
      When we reset the in-kernel MPIC controller, we forget to reset some hidden
      state such as destmask and output. This state is usually set when the guest
      writes to the IDR register for a specific IRQ line.
      
      To make sure we stay in sync and don't forget hidden state, treat reset of
      the IDR register as a simple write of the IDR register. That automatically
      updates all the hidden state as well.
      Reported-by: default avatarPaul Janzen <pcj@pauljanzen.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      aae65596
    • Alexander Graf's avatar
      KVM: PPC: Graciously fail broken LE hypercalls · 42188365
      Alexander Graf authored
      There are LE Linux guests out there that don't handle hypercalls correctly.
      Instead of interpreting the instruction stream from device tree as big endian
      they assume it's a little endian instruction stream and fail.
      
      When we see an illegal instruction from such a byte reversed instruction stream,
      bail out graciously and just declare every hcall as error.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      42188365
    • Alexander Graf's avatar
      PPC: ePAPR: Fix hypercall on LE guest · 235959be
      Alexander Graf authored
      We get an array of instructions from the hypervisor via device tree that
      we write into a buffer that gets executed whenever we want to make an
      ePAPR compliant hypercall.
      
      However, the hypervisor passes us these instructions in BE order which
      we have to manually convert to LE when we want to run them in LE mode.
      
      With this fixup in place, I can successfully run LE kernels with KVM
      PV enabled on PR KVM.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      235959be
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: Remove open coded make_dsisr in alignment handler · ddca156a
      Aneesh Kumar K.V authored
      Use make_dsisr instead of open coding it. This also have
      the added benefit of handling alignment interrupt on additional
      instructions.
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      ddca156a
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: Always use the saved DAR value · 7310f3a5
      Aneesh Kumar K.V authored
      Although it's optional, IBM POWER cpus always had DAR value set on
      alignment interrupt. So don't try to compute these values.
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      7310f3a5
    • Alexander Graf's avatar
      PPC: KVM: Make NX bit available with magic page · 5c165aec
      Alexander Graf authored
      Because old kernels enable the magic page and then choke on NXed trampoline
      code we have to disable NX by default in KVM when we use the magic page.
      
      However, since commit b18db0b8 we have successfully fixed that and can now
      leave NX enabled, so tell the hypervisor about this.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      5c165aec
    • Alexander Graf's avatar
      KVM: PPC: Disable NX for old magic page using guests · f3383cf8
      Alexander Graf authored
      Old guests try to use the magic page, but map their trampoline code inside
      of an NX region.
      
      Since we can't fix those old kernels, try to detect whether the guest is sane
      or not. If not, just disable NX functionality in KVM so that old guests at
      least work at all. For newer guests, add a bit that we can set to keep NX
      functionality available.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f3383cf8
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest · 1f365bb0
      Aneesh Kumar K.V authored
      On recent IBM Power CPUs, while the hashed page table is looked up using
      the page size from the segmentation hardware (i.e. the SLB), it is
      possible to have the HPT entry indicate a larger page size.  Thus for
      example it is possible to put a 16MB page in a 64kB segment, but since
      the hash lookup is done using a 64kB page size, it may be necessary to
      put multiple entries in the HPT for a single 16MB page.  This
      capability is called mixed page-size segment (MPSS).  With MPSS,
      there are two relevant page sizes: the base page size, which is the
      size used in searching the HPT, and the actual page size, which is the
      size indicated in the HPT entry. [ Note that the actual page size is
      always >= base page size ].
      
      We use "ibm,segment-page-sizes" device tree node to advertise
      the MPSS support to PAPR guest. The penc encoding indicates whether
      we support a specific combination of base page size and actual
      page size in the same segment. We also use the penc value in the
      LP encoding of HPTE entry.
      
      This patch exposes MPSS support to KVM guest by advertising the
      feature via "ibm,segment-page-sizes". It also adds the necessary changes
      to decode the base page size and the actual page size correctly from the
      HPTE entry.
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      1f365bb0
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: HV: Prefer CMA region for hash page table allocation · 792fc497
      Aneesh Kumar K.V authored
      Today when KVM tries to reserve memory for the hash page table it
      allocates from the normal page allocator first. If that fails it
      falls back to CMA's reserved region. One of the side effects of
      this is that we could end up exhausting the page allocator and
      get linux into OOM conditions while we still have plenty of space
      available in CMA.
      
      This patch addresses this issue by first trying hash page table
      allocation from CMA's reserved region before falling back to the normal
      page allocator. So if we run out of memory, we really are out of memory.
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      792fc497
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Expose TM registers · 9916d57e
      Alexander Graf authored
      POWER8 introduces transactional memory which brings along a number of new
      registers and MSR bits.
      
      Implementing all of those is a pretty big headache, so for now let's at least
      emulate enough to make Linux's context switching code happy.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      9916d57e
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Expose EBB registers · 2e23f544
      Alexander Graf authored
      POWER8 introduces a new facility called the "Event Based Branch" facility.
      It contains of a few registers that indicate where a guest should branch to
      when a defined event occurs and it's in PR mode.
      
      We don't want to really enable EBB as it will create a big mess with !PR guest
      mode while hardware is in PR and we don't really emulate the PMU anyway.
      
      So instead, let's just leave it at emulation of all its registers.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      2e23f544
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Expose TAR facility to guest · e14e7a1e
      Alexander Graf authored
      POWER8 implements a new register called TAR. This register has to be
      enabled in FSCR and then from KVM's point of view is mere storage.
      
      This patch enables the guest to use TAR.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      e14e7a1e
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR · 616dff86
      Alexander Graf authored
      POWER8 introduced a new interrupt type called "Facility unavailable interrupt"
      which contains its status message in a new register called FSCR.
      
      Handle these exits and try to emulate instructions for unhandled facilities.
      Follow-on patches enable KVM to expose specific facilities into the guest.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      616dff86
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Emulate TIR register · a5948fa0
      Alexander Graf authored
      In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
      Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
      per core, we can just always expose 0 here.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      a5948fa0
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Ignore PMU SPRs · f8f6eb0d
      Alexander Graf authored
      When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
      that we don't emulate. Just ignore accesses to them.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f8f6eb0d
    • Alexander Graf's avatar
      KVM: PPC: Book3S: Move little endian conflict to HV KVM · f24bc1ed
      Alexander Graf authored
      With the previous patches applied, we can now successfully use PR KVM on
      little endian hosts which means we can now allow users to select it.
      
      However, HV KVM still needs some work, so let's keep the kconfig conflict
      on that one.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      f24bc1ed
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Do dcbz32 patching with big endian instructions · cd087eef
      Alexander Graf authored
      When the host CPU we're running on doesn't support dcbz32 itself, but the
      guest wants to have dcbz only clear 32 bytes of data, we loop through every
      executable mapped page to search for dcbz instructions and patch them with
      a special privileged instruction that we emulate as dcbz32.
      
      The only guests that want to see dcbz act as 32byte are book3s_32 guests, so
      we don't have to worry about little endian instruction ordering. So let's
      just always search for big endian dcbz instructions, also when we're on a
      little endian host.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      cd087eef
    • Alexander Graf's avatar
      KVM: PPC: Make shared struct aka magic page guest endian · 5deb8e7a
      Alexander Graf authored
      The shared (magic) page is a data structure that contains often used
      supervisor privileged SPRs accessible via memory to the user to reduce
      the number of exits we have to take to read/write them.
      
      When we actually share this structure with the guest we have to maintain
      it in guest endianness, because some of the patch tricks only work with
      native endian load/store operations.
      
      Since we only share the structure with either host or guest in little
      endian on book3s_64 pr mode, we don't have to worry about booke or book3s hv.
      
      For booke, the shared struct stays big endian. For book3s_64 hv we maintain
      the struct in host native endian, since it never gets shared with the guest.
      
      For book3s_64 pr we introduce a variable that tells us which endianness the
      shared struct is in and route every access to it through helper inline
      functions that evaluate this variable.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      5deb8e7a
    • Alexander Graf's avatar
      KVM: PPC: PR: Fill pvinfo hcall instructions in big endian · 2743103f
      Alexander Graf authored
      We expose a blob of hypercall instructions to user space that it gives to
      the guest via device tree again. That blob should contain a stream of
      instructions necessary to do a hypercall in big endian, as it just gets
      passed into the guest and old guests use them straight away.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      2743103f
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: PAPR: Access RTAS in big endian · b59d9d26
      Alexander Graf authored
      When the guest does an RTAS hypercall it keeps all RTAS variables inside a
      big endian data structure.
      
      To make sure we don't have to bother about endianness inside the actual RTAS
      handlers, let's just convert the whole structure to host endian before we
      call our RTAS handlers and back to big endian when we return to the guest.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      b59d9d26
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: PAPR: Access HTAB in big endian · 1692aa3f
      Alexander Graf authored
      The HTAB on PPC is always in big endian. When we access it via hypercalls
      on behalf of the guest and we're running on a little endian host, we need
      to make sure we swap the bits accordingly.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      1692aa3f
    • Alexander Graf's avatar
      KVM: PPC: Book3S PR: Default to big endian guest · 94810ba4
      Alexander Graf authored
      The default MSR when user space does not define anything should be identical
      on little and big endian hosts, so remove MSR_LE from it.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      94810ba4
    • Alexander Graf's avatar
      KVM: PPC: Book3S_64 PR: Access shadow slb in big endian · 14a7d41d
      Alexander Graf authored
      The "shadow SLB" in the PACA is shared with the hypervisor, so it has to
      be big endian. We access the shadow SLB during world switch, so let's make
      sure we access it in big endian even when we're on a little endian host.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      14a7d41d
    • Alexander Graf's avatar
      KVM: PPC: Book3S_64 PR: Access HTAB in big endian · 4e509af9
      Alexander Graf authored
      The HTAB is always big endian. We access the guest's HTAB using
      copy_from/to_user, but don't yet take care of the fact that we might
      be running on an LE host.
      
      Wrap all accesses to the guest HTAB with big endian accessors.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      4e509af9
    • Alexander Graf's avatar
      KVM: PPC: Book3S_32: PR: Access HTAB in big endian · 860540bc
      Alexander Graf authored
      The HTAB is always big endian. We access the guest's HTAB using
      copy_from/to_user, but don't yet take care of the fact that we might
      be running on an LE host.
      
      Wrap all accesses to the guest HTAB with big endian accessors.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      860540bc
    • Alexander Graf's avatar
      KVM: PPC: Book3S: PR: Fix C/R bit setting · 740f834e
      Alexander Graf authored
      Commit 9308ab8e made C/R HTAB updates go byte-wise into the target HTAB.
      However, it didn't update the guest's copy of the HTAB, but instead the
      host local copy of it.
      
      Write to the guest's HTAB instead.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      CC: Paul Mackerras <paulus@samba.org>
      Acked-by: default avatarPaul Mackerras <paulus@samba.org>
      740f834e
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: PR: Fix WARN_ON with debug options on · 7562c4fd
      Aneesh Kumar K.V authored
      With debug option "sleep inside atomic section checking" enabled we get
      the below WARN_ON during a PR KVM boot. This is because upstream now
      have PREEMPT_COUNT enabled even if we have preempt disabled. Fix the
      warning by adding preempt_disable/enable around floating point and altivec
      enable.
      
      WARNING: at arch/powerpc/kernel/process.c:156
      Modules linked in: kvm_pr kvm
      CPU: 1 PID: 3990 Comm: qemu-system-ppc Tainted: G        W     3.15.0-rc1+ #4
      task: c0000000eb85b3a0 ti: c0000000ec59c000 task.ti: c0000000ec59c000
      NIP: c000000000015c84 LR: d000000003334644 CTR: c000000000015c00
      REGS: c0000000ec59f140 TRAP: 0700   Tainted: G        W      (3.15.0-rc1+)
      MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI>  CR: 42000024  XER: 20000000
      CFAR: c000000000015c24 SOFTE: 1
      GPR00: d000000003334644 c0000000ec59f3c0 c000000000e2fa40 c0000000e2f80000
      GPR04: 0000000000000800 0000000000002000 0000000000000001 8000000000000000
      GPR08: 0000000000000001 0000000000000001 0000000000002000 c000000000015c00
      GPR12: d00000000333da18 c00000000fb80900 0000000000000000 0000000000000000
      GPR16: 0000000000000000 0000000000000000 0000000000000000 00003fffce4e0fa1
      GPR20: 0000000000000010 0000000000000001 0000000000000002 00000000100b9a38
      GPR24: 0000000000000002 0000000000000000 0000000000000000 0000000000000013
      GPR28: 0000000000000000 c0000000eb85b3a0 0000000000002000 c0000000e2f80000
      NIP [c000000000015c84] .enable_kernel_fp+0x84/0x90
      LR [d000000003334644] .kvmppc_handle_ext+0x134/0x190 [kvm_pr]
      Call Trace:
      [c0000000ec59f3c0] [0000000000000010] 0x10 (unreliable)
      [c0000000ec59f430] [d000000003334644] .kvmppc_handle_ext+0x134/0x190 [kvm_pr]
      [c0000000ec59f4c0] [d00000000324b380] .kvmppc_set_msr+0x30/0x50 [kvm]
      [c0000000ec59f530] [d000000003337cac] .kvmppc_core_emulate_op_pr+0x16c/0x5e0 [kvm_pr]
      [c0000000ec59f5f0] [d00000000324a944] .kvmppc_emulate_instruction+0x284/0xa80 [kvm]
      [c0000000ec59f6c0] [d000000003336888] .kvmppc_handle_exit_pr+0x488/0xb70 [kvm_pr]
      [c0000000ec59f790] [d000000003338d34] kvm_start_lightweight+0xcc/0xdc [kvm_pr]
      [c0000000ec59f960] [d000000003336288] .kvmppc_vcpu_run_pr+0xc8/0x190 [kvm_pr]
      [c0000000ec59f9f0] [d00000000324c880] .kvmppc_vcpu_run+0x30/0x50 [kvm]
      [c0000000ec59fa60] [d000000003249e74] .kvm_arch_vcpu_ioctl_run+0x54/0x1b0 [kvm]
      [c0000000ec59faf0] [d000000003244948] .kvm_vcpu_ioctl+0x478/0x760 [kvm]
      [c0000000ec59fcb0] [c000000000224e34] .do_vfs_ioctl+0x4d4/0x790
      [c0000000ec59fd90] [c000000000225148] .SyS_ioctl+0x58/0xb0
      [c0000000ec59fe30] [c00000000000a1e4] syscall_exit+0x0/0x98
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      7562c4fd
    • Aneesh Kumar K.V's avatar
      KVM: PPC: BOOK3S: PR: Enable Little Endian PR guest · e5ee5422
      Aneesh Kumar K.V authored
      This patch make sure we inherit the LE bit correctly in different case
      so that we can run Little Endian distro in PR mode
      Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      e5ee5422
    • Alexander Graf's avatar
      KVM: PPC: E500: Add dcbtls emulation · 8f20a3ab
      Alexander Graf authored
      The dcbtls instruction is able to lock data inside the L1 cache.
      
      We don't want to give the guest actual access to hardware cache locks,
      as that could influence other VMs on the same system. But we can tell
      the guest that its locking attempt failed.
      
      By implementing the instruction we at least don't give the guest a
      program exception which it definitely does not expect.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      8f20a3ab