- 31 Oct, 2019 1 commit
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Luhua Xu authored
As to set_cs takes effect immediately, power spi is needed when setup spi. Cc: Mark Brown <broonie@kernel.org> Signed-off-by:
Luhua Xu <luhua.xu@mediatek.com> Link: https://lore.kernel.org/r/1572426234-30019-1-git-send-email-luhua.xu@mediatek.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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- 30 Oct, 2019 4 commits
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Linus Walleij authored
This driver does not use any symbols from the legacy GPIO header so drop the include. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191030073624.23974-1-linus.walleij@linaro.orgSigned-off-by:
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Linus Walleij authored
The DW driver does not use the legacy GPIO header so drop it from the spi-dw.h include. Signed-off-by:
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Linus Walleij authored
This converts the TXX9 SPI driver to use GPIO descriptors to control the GPIO chip selects. As the driver was clearly (ab)using the device tree "reg" property to offset into the global GPIO chip we have to add a hack to counter the hack: add a 1-to-1 chip select to GPIO offset mapping for all 16 lines on the TXX9 GPIO chip. The details are described in a largeish comment in the patch. We do not need to set up the GPIO as output any more since the core will take care of this, as well as it will handle the polarity inversion semantics. Cc: Atsushi Nemoto <atsushi.nemoto@sord.co.jp> Signed-off-by:
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Jarkko Nikula authored
Committed version of the commit b9fc2d20 ("spi: dw: Move runtime PM enable/disable from common to platform driver part") does not include by some reason changes to drivers/spi/spi-dw.c that were part of the original patch sent to the mailing list. Complete the code move by doing those changes now. Fixes: b9fc2d20 ("spi: dw: Move runtime PM enable/disable from common to platform driver part") Cc: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20191030113137.15459-1-jarkko.nikula@linux.intel.comSigned-off-by:
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- 28 Oct, 2019 2 commits
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Lingling Xu authored
When rebooting system, the PMIC watchdog time loading may not be loaded correctly when another system is feeding the PMIC watchdog, since we did not check the watchdog busy status before loading time values. Thus we should set the BIT_WDG_NEW bit before loading time values, that can support multiple loads without checking busy status to make sure the time values can be loaded successfully to avoid this potential issue. Signed-off-by:
Lingling Xu <ling_ling.xu@unisoc.com> Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/5655318a7252c9ea518c2f7950a61228ab8f42bf.1572257085.git.baolin.wang@linaro.orgSigned-off-by:
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Lingling Xu authored
When rebooting the system, we should lock the watchdog after configuration to make sure the watchdog can reboot the system successfully. Signed-off-by:
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- 25 Oct, 2019 1 commit
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Andy Shevchenko authored
The current conditional for PCI ID matching is hard to read. Introduce couple of temporary variables to increase readability of the code. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20191021103625.4250-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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- 24 Oct, 2019 2 commits
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Alvaro Gamez Machado authored
This core supports either 8, 16 or 32 bits as word width. This value is only settable on instantiation, and thus we need to support any of them by means of the device tree. Signed-off-by:
Alvaro Gamez Machado <alvaro.gamez@hazent.com> Link: https://lore.kernel.org/r/20191024110757.25820-3-alvaro.gamez@hazent.comSigned-off-by:
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Alvaro Gamez Machado authored
This property is used to set the number of bits per transfer (bits_per_word). Xilinx' IP core allows either 8, 16 or 32, and is non changeable on runtime, only when instantiating the core. Signed-off-by:
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- 23 Oct, 2019 2 commits
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Andy Shevchenko authored
Two spelling mistakes are being fixed. Signed-off-by:
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Alexandru Ardelean authored
This change documents the CS setup, host & inactive times. They were omitted when the fields were added, and were caught by one of the build bots. Fixes: 25093bde ("spi: implement SW control for CS times") Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20191023070046.12478-1-alexandru.ardelean@analog.comSigned-off-by:
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- 22 Oct, 2019 2 commits
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Jarkko Nikula authored
Intel(R) Programmable Services Engine (Intel(R) PSE) SPI controllers in Intel Elkhart Lake have two Chip Select signals instead of one. Reported-by:
Raymond Tan <raymond.tan@intel.com> Signed-off-by:
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Raymond Tan authored
Implement pm_runtime hooks at pci driver. Signed-off-by:
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- 18 Oct, 2019 12 commits
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Gregory CLEMENT authored
Thanks to the recent change in this driver, it is now possible to prevent using the CS0 with GPIO during setup. It then allows to remove the special handling of this case in the cs_activate() and cs_deactivate() functions. Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20191017141846.7523-8-gregory.clement@bootlin.comSigned-off-by:
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Gregory CLEMENT authored
In the previous implementation of this driver, the index of the GPIO used as CS was linked to the offset of the CS register used to configure the transfer. With this new implementation the first CS register not used by internal CS is associated to all the GPIO CS. It allows to not be anymore limited to have only 4 CS managed, now it is possible to have in the same time until 3 internal CS and no more limit for the CS GPIO. Signed-off-by:
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Gregory CLEMENT authored
This driver is now only used through the device tree. Simplify code by explicitly depend on device tree. Signed-off-by:
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Gregory CLEMENT authored
Since the conversion to GPIO descriptor, the GPIO used as chip select, can be directly access from the spi_device struct. So there is no need to keep the field npcs_pin. Signed-off-by:
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Gregory CLEMENT authored
Instead of setting up the GPIO configuration for the whole controller, do it at CS level. It will allow to mix internal CS and GPIO CS, which is not possible with the current implementation. Signed-off-by:
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Gregory CLEMENT authored
Until a few years ago, this driver was only used with CS GPIO. The only exception is CS0 on AT91RM9200 which has to use internal CS. A limitation of the internal CS is that they don't support CS High. So by using the CS GPIO the CS high configuration was available except for the particular case CS0 on RM9200. When the support for the internal chip-select was added, the check of the CS high support was not updated. Due to this the driver accepts this configuration for all the SPI controller v2 (used by all SoCs excepting the AT91RM9200) whereas the hardware doesn't support it for infernal CS. This patch fixes the test to match the hardware capabilities. Fixes: 48203034 ("spi: atmel: add support for the internal chip-select of the spi controller") Cc: <stable@vger.kernel.org> Signed-off-by:
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Gregory CLEMENT authored
Since CSAAT functionality support has been added. Some comments become wrong. Fix them to match the current driver behavior. Signed-off-by:
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Andy Shevchenko authored
There is nothing in use from of_device.h. The definitions and macros are available thru mod_devicetable.h and of.h. Signed-off-by:
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Andy Shevchenko authored
Convert to use device_get_match_data() instead of open coded variant. While here, switch of_property_read_bool() to device_property_read_bool(). Signed-off-by:
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Andy Shevchenko authored
This is preparatory patch before converting to use device_get_match_data() API. Signed-off-by:
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Andy Shevchenko authored
Sort the headers in alphabetic order in order to ease the maintenance for this part. Signed-off-by:
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Andy Shevchenko authored
There is no need to keep a pointer to the platform device. Currently there are no users of it directly, and if there will be in the future we may restore it from pointer to the struct device. Convert all users at the same time. Cc: Russell King <linux@armlinux.org.uk> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Signed-off-by:
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- 15 Oct, 2019 14 commits
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Alexandru Ardelean authored
For many places in the spi drivers, using the new `spi_transfer_delay` helper is straightforward. It's just replacing: ``` if (t->delay_usecs) udelay(t->delay_usecs); ``` with `spi_transfer_delay(t)` which handles both `delay_usecs` and the new `delay` field. This change replaces in all places (in the spi drivers) where this change is simple. Signed-off-by: -
Alexandru Ardelean authored
The AXI SPI engine driver uses the `delay_usecs` field from `spi_transfer` to configure delays, which the controller will execute. This change extends the logic to also include the `delay` value, in case it is used (instead if `delay_usecs`). Signed-off-by:
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Alexandru Ardelean authored
The driver errors out if `delay_usecs` is non-zero. This error condition should be extended to the new `delay` field, to account for when it will be used. Signed-off-by:
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Alexandru Ardelean authored
The WARN_ON macro prints a warning in syslog if `delay_usecs` is non-zero. However, with the new intermediate `delay`, the warning should also be printed. Signed-off-by:
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Alexandru Ardelean authored
The way the max delay is computed for this controller, it looks like it is searching for the max delay from an SPI message a using that. No idea if this is valid. But this change should support both `delay_usecs` and the new `delay` data which is of `spi_delay` type. Signed-off-by:
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Alexandru Ardelean authored
This change implements CS control for setup, hold & inactive delays. The `cs_setup` delay is completely new, and can help with cases where asserting the CS, also brings the device out of power-sleep, where there needs to be a longer (than usual), before transferring data. The `cs_hold` time can overlap with the `delay` (or `delay_usecs`) from an SPI transfer. The main difference is that `cs_hold` implies that CS will be de-asserted. The `cs_inactive` delay does not have a clear use-case yet. It has been implemented mostly because the `spi_set_cs_timing()` function implements it. To some degree, this could overlap or replace `cs_change_delay`, but this will require more consideration/investigation in the future. All these delays have been added to the `spi_controller` struct, as they would typically be configured by calling `spi_set_cs_timing()` after an `spi_setup()` call. Software-mode for CS control, implies that the `set_cs_timing()` hook has not been provided for the `spi_controller` object. Signed-off-by:
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Alexandru Ardelean authored
The initial version of `spi_set_cs_timing()` was implemented with consideration only for clock-cycles as delay. For cases like `CS setup` time, it's sometimes needed that micro-seconds (or nano-seconds) are required, or sometimes even longer delays, for cases where the device needs a little longer to start transferring that after CS is asserted. Signed-off-by:
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Alexandru Ardelean authored
The `delay` field has type `struct spi_delay`. This allows users to specify nano-second or clock-cycle delays (if needed). Converting to use `delay` is straightforward: it's just assigning the value to `delay.value` and hard-coding the `delay.unit` to `SPI_DELAY_UNIT_USECS`. This keeps the uapi for spidev un-changed. Changing it can be part of another changeset and discussion. Signed-off-by:
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Alexandru Ardelean authored
This change replaces the use of the `delay_usecs` field with the new `delay` field. The code/test still uses micro-seconds, but they are now configured and used via the `struct spi_delay` format of the `delay` field. Signed-off-by:
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Alexandru Ardelean authored
This conversion to the spi_transfer_delay_exec() helper is not straightforward, as it seems that when a delay is present, the controller issues a command, and then a delay is followed. This change adds support for the new `delay` field which is of type `spi_delay` and keeps backwards compatibility with the old `delay_usecs` field. Signed-off-by:
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Alexandru Ardelean authored
The tegra114 driver has a weird/separate `tegra_spi_transfer_delay()` function that does 2 delays: one mdelay() and one udelay(). This was introduced via commit f4fade12 ("spi/tegra114: Correct support for cs_change"). There doesn't seem to be a mention in that commit message to suggest a specific need/use-case for having the 2 delay calls. For the most part, udelay() should be sufficient. This change replaces it with the new `spi_transfer_delay_exec()`, which should do the same thing. Signed-off-by:
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Alexandru Ardelean authored
The change introduces the `delay` field to the `spi_transfer` struct as an `struct spi_delay` type. This intends to eventually replace `delay_usecs`. But, since there are many users of `delay_usecs`, this needs some intermediate work. A helper called `spi_transfer_delay_exec()` is also added, which maintains backwards compatibility with `delay_usecs`, by assigning the value to `delay` if non-zero. This should maintain backwards compatibility with current users of `udelay_usecs`. Signed-off-by:
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Alexandru Ardelean authored
This change does a conversion from the `word_delay_usecs` -> `word_delay` for the `spi_device` struct. This allows users to specify inter-word delays in other unit types (nano-seconds or clock cycles), depending on how users want. The Atmel SPI driver is the only current user of the `word_delay_usecs` field (from the `spi_device` struct). So, it needed a slight conversion to use the `word_delay` as an `spi_delay` struct. In SPI core, the only required mechanism is to update the `word_delay` information per `spi_transfer`. This requires a bit more logic than before, because it needs that both delays be converted to a common unit (nano-seconds) for comparison. Signed-off-by:
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Alexandru Ardelean authored
The `word_delay` field had it's type changed to `struct spi_delay`. This allows users to specify nano-second or clock-cycle delays (if needed). Converting to use `word_delay` is straightforward: it's just assigning the value to `word_delay.value` and hard-coding the `word_delay.unit` to `SPI_DELAY_UNIT_USECS` This keeps the uapi for spidev un-changed. Changing it can be part of another changeset and discussion. Signed-off-by:
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