- 12 Oct, 2007 40 commits
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Paolo Ornati authored
Seagate Barracuda ST380817AS has troubles with NCQ. For example, unpacking a tarball on an XFS filesystem gives this: ata1.00: exception Emask 0x0 SAct 0x1 SErr 0x0 action 0x2 frozen ata1.00: cmd 61/40:00:29:a3:98/00:00:00:00:00/40 tag 0 cdb 0x0 data 32768 out res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) More info here: http://lkml.org/lkml/2007/1/21/76 Blacklist it! Signed-off-by:Paolo Ornati <ornati@fastwebnet.it> Signed-off-by:
Tejun Heo <htejun@gmail.com> Signed-off-by:
Jeff Garzik <jeff@garzik.org>
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Jeff Garzik authored
Let's see what explodes. Signed-off-by:Jeff Garzik <jgarzik@redhat.com>
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Alan Cox authored
Some controller variants snoop the ATAPI length value for Packet transfers to do state machine and FIFO management. Thus we want to set it properly, even for cases where it is otherwise meaningless. Signed-off-by:
Alan Cox <alan@redhat.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Alan Cox authored
Correct handling of SRST reset sequences. After an SRST it is undefined whether the drive has gone back to PIO0. In order to talk safely we should talk slowly and carefully until we know. Thus when we do the reset if the controller has a pio setup method we call it to flip back to PIO 0 and a known state. After the reset completes the identify will then be done at the safe speed and the drive/controller will pick suitable faster modes and reconfigure the controller to these timings. As a side effect it means we force the controller to PIO 0 as we bring it up which fixes funnies on a few systems where the BIOS firmware leaves us in an interesting choice of modes, or embedded boxes with no firmware which come up in random states. For smart controllers there is nothing to do - they know about this internally. Signed-off-by:
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Matthew Garrett authored
Modern laptops with hotswap bays still tend to utilise a PATA interface on a SATA bridge, generally with the host controller in some legacy emulation mode rather than AHCI. This means that the existing hotplug code in libata is unable to work. The ACPI specification states that these devices can send notifications when hotswapped, which avoids the need to obtain notification from the controller. This patch uses the existing libata-acpi code and simply registers a notification in order to trigger a rescan whenever the firmware signals an event. Signed-off-by:
Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by:
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Alan Cox authored
This is useful when debugging, handling problem systems, or for distributions just to get the system installed so it can be sorted out later. This is a bit smarter than the old IDE one and lets you do libata.dma=0 Disable all PATA DMA like old IDE libata.dma=1 Disk DMA only libata.dma=2 ATAPI DMA only libata.dma=4 CF DMA only (or combinations thereof - 0,1,3 being the useful ones I suspect) (I've split CF as it seems to be a seperate case of pain and suffering different to the others and caused by assorted PIO wired adapters etc) Signed-off-by:
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Peer Chen authored
Signed-off-by:
Peer Chen <peerchen@gmail.com> Signed-off-by:
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Robert Hancock authored
This adds human-readable decoding of the ATA status and error registers (similar to what drivers/ide does) as well as the SATA Serror register to libata error handling output. This prevents the need to pore through standards documents to figure out the meaning of the bits in these registers when looking at error reports. Some bits that drivers/ide decoded are not decoded here, since the bits are either command-dependent or obsolete, and properly parsing them would add too much complexity. Signed-off-by:
Robert Hancock <hancockr@shaw.ca> [edited slightly to make output a bit more symmetric] Signed-off-by:
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Tejun Heo authored
Of course some controllers lie about PMP support. Black list them. Signed-off-by:
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Tejun Heo authored
Private pi.flags area is full and we need more private flags. Move host private flags over to pi.private_data. During initialization, these flags are copied to hpriv->flags. Signed-off-by:
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Tejun Heo authored
Implement AHCI PMP support. ahci only supports command based switching. Also, for some reason, NCQ over PMP doesn't work now. Other than that, everything works. Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744. Signed-off-by:
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Tejun Heo authored
As DEV_RST (hardreset) sometimes fail to recover the controller (especially after PMP DMA CS errata). In such cases, perform PORT_RST prior to DEV_RST. Signed-off-by:
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Tejun Heo authored
Implement PMP support. sil24 supports full FIS-switching. However, it has a PMP DMA CS errata which requires port-wide resetting if commands are outstanding to three or more devices when an error occurs on one of them. ATAPI commands often result in CHECK SENSE and it's crucial to not reset them before fetching sense data. Unfortunately, ATAPI CHECK SENSE causes a lot of problem if command is outstanding to any other device usually resulting in port-wide reset. So, sata_sil24 implements sil24_qc_defer() which guarantees ATAPI command is run by itself. Signed-off-by:
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Tejun Heo authored
Implement sata_pmp_qc_defer_cmd_switch() - standard qc_defer for command switching PMP support. Signed-off-by:
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Tejun Heo authored
Extend ata_acpi_associate_sata_port() such that it can handle PMP and call it when PMP is attached and detached. Build breakage when !CONFIG_ATA_ACPI was spotted and fixed by Petr Vandrovec. Signed-off-by:
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Tejun Heo authored
Hook PMP support into libata and enable it. Connect SCR and probing functions, and update ata_dev_classify() to detect PMP. Signed-off-by:
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Tejun Heo authored
Implement Port Multiplier support. To support PMP, a LLDD has to supply ops->pmp_read() and pmp_write(). If non-null, ->pmp_attach and ->pmp_detach are called on PMP attach and detach, respectively. ->pmp_read/write() can be called while the port is frozen, so they must be implemented by polling. This patch supplies several helpers to ease ->pmp_read/write() implementation. Also, irq_handler and error_handler must be PMP aware. Most of PMP aware EH can be done by calling ata_pmp_do_eh() with appropriate methods. PMP EH uses separate set of reset methods and this patch implements standard prereset, hardreset and postreset methods. This patch only implements PMP support. The next patch will integrate PMP into the reset of libata and thus enable PMP support. Signed-off-by:
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Tejun Heo authored
PMP always requires SRST to be enabled. Also, hardreset reports classification code from the first device when PMP is attached, not from the PMP. Update ata_eh_reset() such that followup softreset is performed if the controller is PMP capable and the host link is being reset. Signed-off-by:
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Alan Cox authored
Restore the support for handling drives that report one sector too many (ie SCSI not ATA style). This worked before the HPA update but was removed in that process. Signed-off-by:
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Jeff Garzik authored
Reported by Andreas Messer. Signed-off-by: -
Alan Cox authored
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David Milburn authored
Blacklist HITACHI HDS7250SASUN500G and HITACHI HDS7225SBSUN250G drives using wildcard matching. Signed-off-by David Milburn <dmilburn@redhat.com> Signed-off-by: -
Tejun Heo authored
* The firmware version of ST3160812AS is "3.ADJ" no "3.AD". * Add several entries from various sources. Signed-off-by:
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Dave Jones authored
'noacpi' isn't a standalone parameter, give it its prefix. Signed-off-by:
Dave Jones <davej@redhat.com> Signed-off-by:
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Alan Cox authored
I've been doing an audit of this driver to try and find out why we have problems with some Clevo boxes that use it. Didn't get anywhere other than to discover all the bug reporters I have use vmware, which may or may not be chance. In the process however I did find out our MWDMA2 performance was a bit low and code review showed the MWDMA0/2 timings are reversed due to a thinko in the table ordering Signed-off-by:
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Alan Cox authored
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Jeff Garzik authored
AHCI spec says host-reset bit may only be set when the ahci-enable bit is also set. Noticed by Peer Chen <peerchen@gmail.com> Signed-off-by: -
Satyam Sharma authored
Little fixlets, that the build started erroring / warning about: drivers/ata/pata_scc.c: In function 'scc_bmdma_status': drivers/ata/pata_scc.c:734: error: structure has no member named 'active_tag' drivers/ata/pata_scc.c: In function 'scc_pata_prereset': drivers/ata/pata_scc.c:866: warning: passing arg 1 of 'ata_std_prereset' from incompatible pointer type drivers/ata/pata_scc.c: In function 'scc_error_handler': drivers/ata/pata_scc.c:908: warning: passing arg 2 of 'ata_bmdma_drive_eh' from incompatible pointer type drivers/ata/pata_scc.c:908: warning: passing arg 3 of 'ata_bmdma_drive_eh' from incompatible pointer type drivers/ata/pata_scc.c:908: warning: passing arg 5 of 'ata_bmdma_drive_eh' from incompatible pointer type make[2]: *** [drivers/ata/pata_scc.o] Error 1 Signed-off-by:
Satyam Sharma <satyam@infradead.org> Cc: Alan Cox <alan@redhat.com> Cc: Mel Gorman <mel@skynet.ie> Signed-off-by:
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Tejun Heo authored
The SATA_PATA_SHARING register doesn't have anything to do with the SATA part of the controller. It indicates whether an extern SATA PHY is attached to the PATA part of the controller and if so how it is wired. As the PATA part is driven by pata_via, sata_via has no reason to care about that. Also, pata_via should work fine under all configurations. This patch removes unnecessary attach failures. It seems recent via chipsets are defaulting to different values or are actually connected to SATA PHY triggering this more often. Signed-off-by:
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Tejun Heo authored
In ata_set_max_sectors(), the highest nibble in LBA28 mode was missing. This made drives sized between 8G and 128G with HPA turned on to be resized to under 8G. Fix it. Signed-off-by:
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Tejun Heo authored
AN serves multiple purposes. For ATAPI, it's used for media change notification. For PMP, for downstream PHY status change notification. Implement sata_async_notification() which demultiplexes AN. To avoid unnecessary port events, ATAPI AN is not enabled if PMP is attached but SNTF is not available. Signed-off-by:
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Tejun Heo authored
Some pseudo devices fail PM commands unnecessarily aborting system suspend. Implement ATA_HORKAGE_SKIP_PM which makes libata skip PM commands for these devices. Signed-off-by:
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Tejun Heo authored
If PMP itself becomes inaccessible while trying to link a downstream link, spending time to recover the downstream link doesn't make any sense. Make EH skip retry and fail fast if -ERESTART is received. Signed-off-by:
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Tejun Heo authored
Implement ATA_LFLAG_DISABLED. The flag indicates the link is disabled due to EH recovery failure. While a link is disabled, no EH action is taken on the link and suspend/resume become noop too. This will be used by PMP links to manage failed links. Signed-off-by:
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Tejun Heo authored
Some PMP links are connected to internal pseudo devices which may come and go depending on situation. There's no reason to try hard to recover them. ATA_LFLAG_NO_RETRY tells EH to not retry if the device attached to the link fails. Signed-off-by:
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Tejun Heo authored
Some links on some PMPs locks up on SRST and/or report incorrect device signature. Implement ATA_LFLAG_NO_SRST, ASSUME_ATA and ASSUME_SEMB to handle these quirky links. NO_SRST makes EH avoid SRST. ASSUME_ATA and SEMB forces class code to ATA and SEMB_UNSUP respectively. Note that SEMB isn't currently supported yet so the _UNSUP variant is used. Signed-off-by:
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Tejun Heo authored
Implement ap->nr_active_links (the number of links with active qcs), ap->excl_link (pointer to link which can be used by ->qc_defer and is cleared when a qc with ATA_QCFLAG_CLEAR_EXCL completes), and ata_link_active(). These can be used by ->qc_defer() to implement proper command exclusion. This set of helpers seem enough for both sil24 (ATAPI exclusion needed) and cmd-switching PMP. Signed-off-by:
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Tejun Heo authored
Controllers which support PMP have various restrictions on which combinations of commands are allowed to what number of devices concurrently. This patch implements ops->qc_defer() which determines whether a qc can be issued at the moment or should be deferred. If the function returns ATA_DEFER_LINK, the qc will be deferred until a qc completes on the link. If ATA_DEFER_PORT, until a qc completes on any link. The defer conditions are advisory and in general ATA_DEFER_LINK can be considered as lower priority deferring than ATA_DEFER_PORT. ops->qc_defer() replaces fixed ata_scmd_need_defer(). For standard NCQ/non-NCQ exclusion, ata_std_qc_defer() is implemented. ahci and sata_sil24 are converted to use ata_std_qc_defer(). ops->qc_defer() is heavier than the original mechanism because full qc is prepped before determining to defer it, but various information is needed to determine defer conditinos and fully translating a qc is the only way to supply such information in generic manner. IMHO, this shouldn't cause any noticeable performance issues as * for most cases deferring occurs rarely (except for NCQ-aware cmd-switching PMP) * translation itself isn't that expensive * once deferred the command won't be repeated until another command completes which usually is a very long time cpu-wise. Signed-off-by:
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Tejun Heo authored
Make a number of functions from libata-core.c and libata-eh.c global to libata (drivers/ata/libata.h). These will be used by PMP. Signed-off-by:
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Tejun Heo authored
Consider newly found class code while revalidating. PMP resetting always results in valid class code and issuing PMP commands to ATA/ATAPI device isn't very attractive. Add @new_class to ata_dev_revalidate() and check class code for revalidation. Signed-off-by:
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