1. 15 Dec, 2014 2 commits
    • Imre Deak's avatar
      drm/i915: sanitize RPS resetting during GPU reset · dbea3cea
      Imre Deak authored
      Atm, we don't disable RPS interrupts and related work items before
      resetting the GPU. This may interfere with the following GPU
      initialization and cause RPS interrupts to show up in PM_IIR too early
      before calling gen6_enable_rps_interrupts() (triggering a WARN there).
      
      Solve this by disabling RPS interrupts and flushing any related work
      items before resetting the GPU.
      
      v2:
      - split out the common parts of the gt suspend and the new gt reset
        functions (Paulo)
      v3:
      - remove the check for UMS, it's a NOP nowadays (Daniel)
      Reported-by: default avatarHe, Shuang <shuang.he@intel.com>
      Testcase: igt/gem_reset_stats/ban-render
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      dbea3cea
    • Imre Deak's avatar
      drm/i915: move RPS PM_IER enabling to gen6_enable_rps_interrupts · 78e68d36
      Imre Deak authored
      Paulo noticed that we don't enable RPS interrupts via PM_IER in
      gen6_enable_rps_interrupts(). This wasn't a problem so far, since the
      only place we disabled RPS interrupts was during system/runtime suspend
      and after that we reenable all interrupts in the IRQ pre/postinstall
      hooks.
      
      In the next patch we'll disable/reenable RPS interrupts during GPU reset
      too, but not call IRQ uninstall, pre/postinstall hooks, so there the
      above wouldn't work. The logical place for programming PM_IER is
      gen6_enable_rps_interrupts() and this also makes the function more
      symmetric with gen6_disable_rps_interrupts(), so move the programming
      there from the postinstall hooks.
      
      Note that these changes don't affect the ILK RPS interrupt code, which
      could be sanitized in a similar way. But that can be done as a
      follow-up.
      
      Credits-to: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      78e68d36
  2. 11 Dec, 2014 2 commits
    • Imre Deak's avatar
      drm/i915: vlv: fix IRQ masking when uninstalling interrupts · c352d1ba
      Imre Deak authored
      irq_mask should include all IRQ bits that we want to mask, but atm we
      set it incorrectly to the inverse of this. If the mask is used
      subsequently to enable/disable some IRQ bits, we may unintentionally
      unmask unrelated IRQs. I can't see any way that this can lead to a real
      problem in the current -nightly code, since the first place the mask
      will be used next (after a suspend/resume cycle) is in
      valleyview_irq_postinstall(), but the mask is reset there to its proper
      value.
      
      This causes a problem in the upstream kernel though, where - due to another
      issue - the mask is used in the above way to disable only the display IRQs.
      This other issue is fixed by:
      
      commit 950eabaf
      Author: Imre Deak <imre.deak@intel.com>
      Date:   Mon Sep 8 15:21:09 2014 +0300
      
          drm/i915: vlv: fix display IRQ enable/disable
      
      Interestingly, even with the above two bugs, we shouldn't in theory have
      any real problems (arguably a famous last sentence:). That's because
      even if we unmask something unintentionally via the VLV_IMR/VLV_IER
      register the master IRQ masking bit in VLV_MASTER_IER is still set and
      should prevent all i915 interrupts. According to my testing on an ASUS
      T100 with DSI output this isn't the case at least with the
      MIPIA_INTERRUPT. Leaving this one unmasked in IMR/IER, while having
      VLV_MASTER_IER set to 0 may lead to a lockup during system suspend as
      shown in the bugzilla ticket below. This fix should get rid of the
      problem reported there in upstream and older kernels.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85920
      Cc: stable@vger.kernel.org (v3.15+)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      c352d1ba
    • Jesse Barnes's avatar
      drm/i915: save/restore GMBUS freq across suspend/resume on gen4 · 9f49c376
      Jesse Barnes authored
      Should probably just init this in the GMbus code all the time, based on
      the cdclk and HPLL like we do on newer platforms.  Ville has code for
      that in a rework branch, but until then we can fix this bug fairly
      easily.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76301Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Tested-by: default avatarNikolay <mar.kolya@gmail.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      9f49c376
  3. 10 Dec, 2014 4 commits
  4. 08 Dec, 2014 1 commit
  5. 05 Dec, 2014 3 commits
  6. 03 Dec, 2014 18 commits
  7. 02 Dec, 2014 10 commits
    • Laurent Pinchart's avatar
      drm: rcar-du: Fix NULL encoder pointer dereference · 4fcd01d0
      Laurent Pinchart authored
      The DRM connector's encoder pointer is managed internally by the DRM
      core and set to NULL when the DRM connector is disconnected from the
      CRTC it was attached to. This results in a NULL pointer dereference in
      the HDMI connector functions when trying to call the associated slave
      encoder's operations.
      
      Fix this by retrieving the slave encoder pointer from the R-Car
      connector structure instead of the DRM connector structure.
      Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      4fcd01d0
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2014-11-21-fixed' of... · 26045b53
      Dave Airlie authored
      Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next
      
      drm-intel-next-2014-11-21:
      - infoframe tracking (for fastboot) from Jesse
      - start of the dri1/ums support removal
      - vlv forcewake timeout fixes (Imre)
      - bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom
        O'Rourke)
      - on-demand pinning for execlist contexts
      - vlv/chv backlight improvements (Ville)
      - gen8+ render ctx w/a work from various people
      - skl edp programming (Satheeshakrishna et al.)
      - psr docbook (Rodrigo)
      - piles of little fixes and improvements all over, as usual
      
      * tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits)
        drm/i915: Don't pin LRC in GGTT when dumping in debugfs
        drm/i915: Update DRIVER_DATE to 20141121
        drm/i915/g4x: fix g4x infoframe readout
        drm/i915: Only call mod_timer() if not already pending
        drm/i915: Don't rely upon encoder->type for infoframe hw state readout
        drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave
        drm/i915: Use ggtt error obj capture helper for gen8 semaphores
        drm/i915: vlv: increase timeout when setting idle GPU freq
        drm/i915: vlv: fix cdclk setting during modeset while suspended
        drm/i915: Dump hdmi pipe_config state
        drm/i915: Gen9 shadowed registers
        drm/i915/skl: Gen9 multi-engine forcewake
        drm/i915: Read power well status before other registers for drpc info
        drm/i915: Pin tiled objects for L-shaped configs
        drm/i915: Update ring freq for full gpu freq range
        drm/i915: change initial rps frequency for gen8
        drm/i915: Keep min freq above floor on HSW/BDW
        drm/i915: Use efficient frequency for HSW/BDW
        drm/i915: Can i915_gem_init_ioctl
        drm/i915: Sanitize ->lastclose
        ...
      26045b53
    • Thomas Daniel's avatar
      drm/i915: Don't pin LRC in GGTT when dumping in debugfs · 064ca1d2
      Thomas Daniel authored
      LRC object does not need to be mapped into the GGTT when dumping. A side-effect
      of this patch is that a compiler warning goes away (not checking return value
      of i915_gem_obj_ggtt_pin).
      
      v2: Broke out individual context dumping into a new function as the indentation
      was getting a bit crazy.  Added notification of contexts with no gem object for
      debugging purposes.  Removed unnecessary pin_pages and unpin_pages, replaced
      with explicit get_pages for the context object as there may be no backing store
      allocated at this time (Comment for get_pages says "Ensure that the associated
      pages are gathered from the backing storage and pinned into our object").
      Improved error checking - get_pages and get_page are checked for failure.
      Signed-off-by: default avatarThomas Daniel <thomas.daniel@intel.com>
      [danvet: Align paramter continuation lines properly. Also add some
      braces to the nested loops again for readability.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      064ca1d2
    • Dave Airlie's avatar
      Merge branch 'linux-3.19' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next · 1a92b7a2
      Dave Airlie authored
      - Tegra K1 voltage support, and coherency improvements
      - GM204 support (modesetting, still waiting on NVIDIA for signed fw to
      proceed further), and a lot of bios/i2c/devinit adjustments needed to
      support it
      - GT21x memory reclocking work
      - Various other bits and pieces, most of which are prep-work for a
      couple of bigger projects I didn't get finished in time
      
      * 'linux-3.19' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (73 commits)
        drm/nv50/kms: drop requirement that framebuffer bos be contig up-front
        drm/nv50/kms: directly use cursor image from userspace buffer
        drm/nouveau/kms: when pinning display-related buffers, force contig vram
        drm/nouveau: teach nouveau_bo_pin() how to force a contig vram allocation
        drm/nouveau/volt: add support for GK20A
        drm/nouveau/platform: add GPU speedo information to nouveau platform
        drm/nouveau/volt: allow non-bios voltage scaling
        drm/gf100-/gr: return non-fatal error code when fw not present
        drm/nouveau/devinit: bump priv ring timeouts before executing scripts
        drm/nouveau/bios: translate ramcfg strap through M0203
        drm/nouveau/fb: make use of M0203 routines for ram type determination
        drm/nouveau/bios: add parsing of BIT M(v2) +0x03 table
        drm/nouveau/core: allow vbios parsing without knowing chipset type
        drm/nouveau/lib: add null backend
        drm/nouveau/device: store revision
        drm/nouveau/core: add some forgotten subdevs to disable mask
        drm/gk20a/clk: fix max VCO value
        drm/nouveau: we need pin_refcnt for nouveau_bo_placement_set()
        drm/nv50-/kms: add some evo tracing ability for debugging
        drm/nv50/kms: use sclass() instead of trial-and-error
        ...
      1a92b7a2
    • Ben Skeggs's avatar
      drm/nv50/kms: drop requirement that framebuffer bos be contig up-front · 9f6d2ce3
      Ben Skeggs authored
      We'll move them at pin() time if necessary.
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      9f6d2ce3
    • Ben Skeggs's avatar
      drm/nv50/kms: directly use cursor image from userspace buffer · 5a560252
      Ben Skeggs authored
      Preparation for transition to planes, which use framebuffers for the
      cursor image.  We've always done copies from the userspace buffer up
      until now for legacy reasons, there's no good reason to do so on the
      chipsets this code covers.
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      5a560252
    • Ben Skeggs's avatar
    • Ben Skeggs's avatar
      drm/nouveau: teach nouveau_bo_pin() how to force a contig vram allocation · ad76b3f7
      Ben Skeggs authored
      We have the ability to move buffers around in the kernel if necessary,
      and should probably use it rather than failing if userspace passes us
      a non-contig buffer for a plane.
      
      The NOUVEAU_GEM_TILE_NONCONTIG flag from userspace will become a mere
      initial placement hint once all the relevant paths have been updated.
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      ad76b3f7
    • Vince Hsu's avatar
      drm/nouveau/volt: add support for GK20A · ef1df1bc
      Vince Hsu authored
      The voltage value are calculated by the hardware characterized
      result.
      Signed-off-by: default avatarVince Hsu <vinceh@nvidia.com>
      Reviewed-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
      Acked-by: default avatarMartin Peres <martin.peres@free.fr>
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      ef1df1bc
    • Vince Hsu's avatar
      drm/nouveau/platform: add GPU speedo information to nouveau platform · 37025602
      Vince Hsu authored
      For GK20A we need the GPU speedo value to calculate voltage levels.
      Signed-off-by: default avatarVince Hsu <vinceh@nvidia.com>
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      37025602