- 19 Dec, 2015 1 commit
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https://git.linaro.org/people/john.stultz/linuxThomas Gleixner authored
Get the core time(keeping) updates from John Stultz - NTP robustness tweaks - Another signed overflow nailed down - More y2038 changes - Stop alarmtimer after resume - MAINTAINERS update - Selftest fixes
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- 17 Dec, 2015 4 commits
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John Stultz authored
Thus its been occasionally noted that users have seen confusing warnings like: Adjusting tsc more than 11% (5941981 vs 7759439) We try to limit the maximum total adjustment to 11% (10% tick adjustment + 0.5% frequency adjustment). But this is done by bounding the requested adjustment values, and the internal steering that is done by tracking the error from what was requested and what was applied, does not have any such limits. This is usually not problematic, but in some cases has a risk that an adjustment could cause the clocksource mult value to overflow, so its an indication things are outside of what is expected. It ends up most of the reports of this 11% warning are on systems using chrony, which utilizes the adjtimex() ADJ_TICK interface (which allows a +-10% adjustment). The original rational for ADJ_TICK unclear to me but my assumption it was originally added to allow broken systems to get a big constant correction at boot (see adjtimex userspace package for an example) which would allow the system to work w/ ntpd's 0.5% adjustment limit. Chrony uses ADJ_TICK to make very aggressive short term corrections (usually right at startup). Which push us close enough to the max bound that a few late ticks can cause the internal steering to push past the max adjust value (tripping the warning). Thus this patch adds some extra logic to enforce the max adjustment cap in the internal steering. Note: This has the potential to slow corrections when the ADJ_TICK value is furthest away from the default value. So it would be good to get some testing from folks using chrony, to make sure we don't cause any troubles there. Cc: Miroslav Lichvar <mlichvar@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Prarit Bhargava <prarit@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Tested-by: Miroslav Lichvar <mlichvar@redhat.com> Reported-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
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DengChao authored
The function "second_overflow" uses "unsign long" as its input parameter type which will overflow after year 2106 on 32bit systems. Thus this patch replaces it with time64_t type. While the 64-bit division is expensive, "next_ntp_leap_sec" has been calculated already, so we can just re-use it in the TIME_INS/DEL cases, allowing one expensive division per leapsecond instead of re-doing the divsion once a second after the leap flag has been set. Signed-off-by: DengChao <chao.deng@linaro.org> [jstultz: Tweaked commit message] Signed-off-by: John Stultz <john.stultz@linaro.org>
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DengChao authored
The type of static variant "time_reftime" and the call of get_seconds in ntp are both not y2038 safe. So change the type of time_reftime to time64_t and replace get_seconds with __ktime_get_real_seconds. The local variant "secs" in ntp_update_offset represents seconds between now and last ntp adjustment, it seems impossible that this time will last more than 68 years, so keep its type as "long". Reviewed-by: John Stultz <john.stultz@linaro.org> Signed-off-by: DengChao <chao.deng@linaro.org> [jstultz: Tweaked commit message] Signed-off-by: John Stultz <john.stultz@linaro.org>
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DengChao authored
In order to fix Y2038 issues in the ntp code we will need replace get_seconds() with ktime_get_real_seconds() but as the ntp code uses the timekeeping lock which is also used by ktime_get_real_seconds(), we need a version without locking. Add a new function __ktime_get_real_seconds() in timekeeping to do this. Reviewed-by: John Stultz <john.stultz@linaro.org> Signed-off-by: DengChao <chao.deng@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
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- 16 Dec, 2015 9 commits
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Yoshinori Sato authored
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Yoshinori Sato authored
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Yoshinori Sato authored
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Yoshinori Sato authored
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Yoshinori Sato authored
Counter overflow detection use for overflow interrupt Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Vladimir Zapolskiy authored
If by some reason timerclk is not available, both clockevent and clocksource initializations correctly exit, but output of errno to kernel log buffer may be confusing: lpc32xx_clk_init: failed to map system control block registers lpc32xx_clocksource_init: clock get failed (4294966779) lpc32xx_clockevent_init: clock get failed (4294966779) Use signed integer output in the correspondent pr_err() string formats: lpc32xx_clocksource_init: clock get failed (-517) lpc32xx_clockevent_init: clock get failed (-517) Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Grygorii Strashko authored
Now the System stall is observed on TI AM437x based board (am437x-gp-evm) during resuming from System suspend when ARM Global timer is selected as clocksource device (CPUIdle not enabled) - SysRq are working, but nothing else. The reason of stall is that ARM Global timer loses its contexts during System suspend: GT_CONTROL.TIMER_ENABLE = 0 (unbanked) GT_COUNTERx = 0 Hence, update ARM Global timer driver to reflect above behaviour - re-enable ARM Global timer on resume (GT_CONTROL.TIMER_ENABLE = 1) if not enabled. CC: Arnd Bergmann <arnd@arndb.de> Cc: John Stultz <john.stultz@linaro.org> Cc: Felipe Balbi <balbi@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Jisheng Zhang authored
Let's assume the counter value is 0xf0000000, the pistachio clocksource read cycles function should return ~0x0fffffff but actually it returns 0xffffffff0fffffff. That occurs because: ~(cycle_t)value is different from (cycle_t)~value. unsigned long val = ~(unsigned long)0xf0000000; 40049a: 48 b8 ff ff ff 0f ff movabs $0xffffffff0fffffff,%rax unsigned long val = (unsigned long)~0xf0000000; 40049a: 48 c7 45 f8 ff ff ff movq $0xfffffff,-0x8(%rbp) We fix this issue by calculating bitwise-not counter, then cast to cycle_t. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Jisheng Zhang authored
Use the relaxed version to improve performance. we measured time of 4096 rounds of gt_compare_set() spent on Marvell BG2Q: before the patch: 3690648ns on average after the patch: 1083023ns on average improved by 70%! Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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- 15 Dec, 2015 26 commits
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Jisheng Zhang authored
It seems gcc can automatically inline apbt_writel() for us, but apbt_real isn't inlined. This patch makes them inline to get a trivial performance improvement: 4096 rounds of __apbt_read_clocksource() call spend time on Marvell BG4CT platform: before the patch 1275240ns on average after the patch 1263240ns on average so we get 1% performance improvement. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Jisheng Zhang authored
It's safe to use the relaxed version. From another side, the relaxed io accessor macros are available on all architectures now, so we can use the relaxed versions to get a trivial system performance improvement, we measured time the following functions spent on Marvell BG4CT: 4096 rounds of __apbt_read_clocksource() call: before the patch: 1263240ns on average after the patch: 1250080ns on average improved by 1% 4096 rounds of apbt_eoi() call: before the patch: 1290960ns on average after the patch: 1248240ns on average 4096 rounds of apbt_next_event() call: before the patch: 3333660ns on average after the patch: 1322040ns on average improved by 60%! Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Jisheng Zhang authored
On Marvell BG4CT platform, we observed the __apbt_read_clocksource() return wrong value: Let's assume the APBTMR_N_CURRENT_VALUE value is 0xf0000000, we got 0xffffffff0fffffff, but it should be 0xfffffff. This issue should be common on all 64bit platforms. We fix the issue by letting aptb_readl() return u32. apbt_writel() is also updated to write u32 val rather than unsigned long. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The current code to initialize, register and read the clocksource is already factored out in mmio.c via the clocksource_mmio_init function. Factor out the code with the clocksource_mmio_init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Add the COMPILE_TEST option so the drivers can be compiled on different architecture with the 'allyesconfig' kernel configuration. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
For the sake of consistency, let rename all ctrl_out/in calls to the write/read calls so we have the same API consistent with the other architectures hence open the door for the increasing of the test compilation coverage. The unsigned long coercive cast is removed because all variables are set to the right type "void __iomem *". Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The current Kconfig option is the H8300 arch option. In order to comply to the current rule, let's create a specific option for the timer8 and select it from the arch's Kconfig. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The current code to initialize, register and read the clocksource is already factored out in mmio.c via the clocksource_mmio_init function. The only difference is the readl vs readl_relaxed. Factor out the code with the clocksource_mmio_init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Daniel Lezcano authored
The lock in the timer16_clocksource_read is not needed, remove it. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The function irq_of_parse_and_map returns zero in case of failure. Fix the return code test to check against zero. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The fields are not used in the code, remove them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The macros are no longer used in the code, remove them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The headers are not needed, remove them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The current code retrieves the rate value when the timer is enabled which occurs each time a timer is re-armed. Except if the clock frequency has changed magically I don't see why this should be done each time. Retrieve the clock rate value at init time only. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The time framawork takes care of disabling the interrupts and takes a lock to prevent races. Remove the legacy code in the driver taking care of the races. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The current code assumes the interrupt function is re-entrant. That is not correct. An interrupt handler is never invoked concurrently. The interrupt line is masked on all processors. Remove the chewing flags in the code. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The value returned in case of error for the 'irq_of_parse_and_map' function is zero in case of error. Fix the check in the init code. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Specify the delta as parameter for the timer8_clock_event_start function instead of using a macro to tell PERIODIC or ONESHOT. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
Some macros are unused, delete them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
The dev_warn is using the platform driver which was removed in the previous patch. Let's replace dev_warn by pr_warn. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Yoshinori Sato authored
Remove some legacy code and replace it by the clksrc-of code. Do some cleanup and code consolidation. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Jisheng Zhang authored
Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD platforms. And after this patch, udelay() will be unaffected by CPU frequency changes. Note: Although in case there are several possible delay timers, we may not select the "best" delay timer. Take one Marvell Berlin platform for example: we have arch timer and dw-apb timer. The arch timer freq is 25MHZ while the dw-apb timer freq is 100MHZ, current selection would choose the dw-apb timer. But the dw apb timer is on the APB bus while arch timer sits in CPU, the cost of accessing the apb timer is higher than the arch timer. We could introduce "rating" concept to delay timer, but this approach "brings a lot of complexity and workarounds in the code for a small benefit" as pointed out by Daniel. Later, Arnd pointed out "However, we could argue that this actually doesn't matter at all, because the entire point of the ndelay()/ udelay()/mdelay() functions is to waste CPU cycles doing not much at all, so we can just as well waste them reading the timer register than spinning on the CPU reading the arch timer more often.", so we just simply register the dw apb base delay timer. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Daniel Lezcano authored
In order to compile on all arch without error with 'allyesconfig' make sure the platform selected the GENERIC_CLOCKEVENTS. Without this patch the new added drivers will prevent the kernel to compile on PARISC. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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