- 04 Sep, 2019 7 commits
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190904135918.25352-8-yuehaibing@huawei.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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YueHaibing authored
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by:
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- 03 Sep, 2019 4 commits
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Colin Ian King authored
There is a spelling mistake in a dev_warning message. Fix it. Also break line to clear up checkpatch warning. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20190903122812.3986-1-colin.king@canonical.comSigned-off-by:
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Vladimir Oltean authored
When the driver is working in TCFQ/EOQ mode (i.e. interacts with the SPI controller's FIFOs directly) the following sequence of operations happens: - The first byte of the tx buffer gets pushed to the TX FIFO (dspi->len gets decremented). This triggers the train of interrupts that handle the rest of the bytes. - The dspi_interrupt handles a TX confirmation event. It reads the newly available byte from the RX FIFO, checks the dspi->len exit condition, and if there's more to be done, it kicks off the next interrupt in the train by writing the next byte to the TX FIFO. Now the problem is that the wait queue is woken up one byte too early, because dspi->len becomes 0 as soon as the byte has been pushed into the TX FIFO. Its interrupt has not yet been processed and the RX byte has not been put from the FIFO into the buffer. Depending on the timing of the wait queue wakeup vs the handling of the last dspi_interrupt, it can happen that the main SPI message pump thread has already returned back into the spi_device driver. When the rx buffer is on stack (which it can be, because in this mode, the DSPI doesn't do DMA), the last interrupt will perform a memory write into an rx buffer that has been freed. This manifests as stack corruption. The solution is to only wake up the wait queue when dspi_rxtx says so, i.e. after it has processed the last TX confirmation interrupt and collected the last RX byte. Fixes: c55be305 ("spi: spi-fsl-dspi: Use poll mode in case the platform IRQ is missing") Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20190903105708.32273-1-olteanv@gmail.comSigned-off-by:
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Keiji Hayashibara authored
Introduce new polling mode for short size transfer. Either the estimated transfer time is estimated to exceed 200us, or polling loop actually exceeds 200us, it switches to irq mode. Signed-off-by:
Keiji Hayashibara <hayashibara.keiji@socionext.com> Link: https://lore.kernel.org/r/1567488661-11428-4-git-send-email-hayashibara.keiji@socionext.comSigned-off-by:
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Keiji Hayashibara authored
This commit removed if() because priv->is_save_param is always true. Signed-off-by:
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- 02 Sep, 2019 1 commit
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Alexander Sverdlin authored
The actual device name of the SPI controller being registered on EP93xx is "spi0" (as seen by gpiod_find_lookup_table()). This patch fixes all relevant lookup tables and the following failure (seen on EDB9302): ep93xx-spi ep93xx-spi.0: failed to register SPI master ep93xx-spi: probe of ep93xx-spi.0 failed with error -22 Fixes: 1dfbf334 ("spi: ep93xx: Convert to use CS GPIO descriptors") Cc: stable@vger.kernel.org Signed-off-by:
Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Lukasz Majewski <lukma@denx.de> Link: https://lore.kernel.org/r/20190831180402.10008-1-alexander.sverdlin@gmail.comSigned-off-by:
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- 30 Aug, 2019 3 commits
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Rayagonda Kokatanur authored
The spi-nor controller defaults to BSPI mode, hence switch back to its default mode after MSPI operations (write or erase) are completed. Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by:
Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/1567139325-7912-1-git-send-email-rayagonda.kokatanur@broadcom.comSigned-off-by:
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Tomer Maimon authored
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20190828142513.228556-3-tmaimon77@gmail.comSigned-off-by:
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Tomer Maimon authored
Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI master controller using SPI-MEM interface. Signed-off-by:
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- 28 Aug, 2019 2 commits
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Linus Walleij authored
This converts the BCM2835 SPI master driver to use GPIO descriptors for chip select handling. The BCM2835 driver was relying on the core to drive the CS high/low so very small changes were needed for this part. If it managed to request the CS from the device tree node, all is pretty straight forward. However for native GPIOs this driver has a quite unorthodox loopback to request some GPIOs from the SoC GPIO chip by looking it up from the device tree using gpiochip_find() and then offseting hard into its numberspace. This has been augmented a bit by using gpiochip_request_own_desc() but this code really needs to be verified. If "native CS" is actually an SoC GPIO, why is it even done this way? Should this GPIO not just be defined in the device tree like any other CS GPIO? I'm confused. Cc: Lukas Wunner <lukas@wunner.de> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Chris Boot <bootc@bootc.net> Signed-off-by:
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Linus Walleij authored
This converts the Freescale SPI master driver to use GPIO descriptors for chip select handling. The Freescale (fsl) driver has a lot of quirks to look up "gpios" rather than "cs-gpios" from the device tree. After the prior patch that will make gpiolib return the GPIO descriptor for "gpios" in response to a request for "cs-gpios", this code can be cut down quite a bit. The driver has custom handling of chip select rather than using the core (which may be possible but not done in this patch) so it still needs to refer directly to spi->cs_gpiod to set the chip select. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by:
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- 23 Aug, 2019 6 commits
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Vladimir Oltean authored
On platforms like LS1021A which use TCFQ mode, an interrupt needs to be processed after each byte is TXed/RXed. I tried to make the DSPI implementation on this SoC operate in other, more efficient modes (EOQ, DMA) but it looks like it simply isn't possible. Therefore allow the driver to operate in poll mode, to ease a bit of this absurd amount of IRQ load generated in TCFQ mode. Doing so reduces both the net time it takes to transmit a SPI message, as well as the inter-frame jitter that occurs while doing so. Signed-off-by:
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Vladimir Oltean authored
dspi->devtype_data is under the total control of the driver. Therefore, a bad value is a driver bug and checking it at runtime (and during an ISR, at that!) is pointless. The second "else if" check is only for clarity (instead of a broader "else") in case other transfer modes are added in the future. But the printing is dead code and can be removed. Signed-off-by:
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Vladimir Oltean authored
The DSPI interrupt can be shared between two controllers at least on the LX2160A. In that case, the driver for one controller might misbehave and consume the other's interrupt. Fix this by actually checking if any of the bits in the status register have been asserted. Fixes: 13aed239 ("spi: spi-fsl-dspi: use IRQF_SHARED mode to request IRQ") Signed-off-by:
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Vladimir Oltean authored
If the entire function depends on the SPI status register having the interrupt bits asserted, then just check it and exit early if those bits aren't set (such as in the case of the shared IRQ being triggered for the other peripheral). Cosmetic patch. Signed-off-by:
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Mark Brown authored
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Vladimir Oltean authored
The DSPI interrupt can be shared between two controllers at least on the LX2160A. In that case, the driver for one controller might misbehave and consume the other's interrupt. Fix this by actually checking if any of the bits in the status register have been asserted. Fixes: 13aed239 ("spi: spi-fsl-dspi: use IRQF_SHARED mode to request IRQ") Signed-off-by:
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- 22 Aug, 2019 2 commits
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Ashish Kumar authored
There are 2 version of QSPI-IP, according to which controller registers sets can be big endian or little endian.There are some other minor changes like RX fifo depth etc. The big endian version uses driver compatible "fsl,ls1021a-qspi" and little endian version uses driver compatible "fsl,ls2080a-qspi" Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by:
Rob Herring <robh@kernel.org> Acked-by:
Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/1565691791-26167-1-git-send-email-Ashish.Kumar@nxp.comSigned-off-by:
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Ashish Kumar authored
Add example for adding flash entry on various boards' dts using flash manufacture spansion/cypress. Signed-off-by:
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- 20 Aug, 2019 14 commits
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Vladimir Oltean authored
The two functions are loosely coupled through dspi->waitq, but logically, dspi_transfer_one_message depends on dspi_interrupt in order to complete. Move its definition above it so the I/O functions are grouped closer together. Signed-off-by:
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Vladimir Oltean authored
mask of -> mask off at and -> and Signed-off-by:
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Vladimir Oltean authored
This patch puts variable declaration in the reverse order of their length for cosmetic purposes. Signed-off-by:
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Vladimir Oltean authored
This adapts the spi-fsl-dspi driver to the API changes introduced in commit 8caab75f ("spi: Generalize SPI "master" to "controller""). Signed-off-by:
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Vladimir Oltean authored
Introduced in commit 9298bc72 ("spi: spi-fsl-dspi: Remove spi-bitbang") for less than obvious reasons, this assignment is confusing and serves no purpose. Signed-off-by:
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Vladimir Oltean authored
There is no code path for reaching 'return ret;' without it first being assigned to an error code. Therefore the initialization with 0 is pointless. Signed-off-by:
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Vladimir Oltean authored
There is no point in surrounding an entire function block in an if condition. Rather, exit early if the condition is false. Signed-off-by:
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Vladimir Oltean authored
These are macros that accept 0 or 1 as argument (a boolean value). Their use encourages the abuse of complex ternary operations inside their argument list, which detracts from the code readability. Replace these with simple if-else statements. Signed-off-by:
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Vladimir Oltean authored
This patch adds the field definitions for the SPI_SR register. The SPI status register is write-1-to-clear and this value is written at init time. Signed-off-by:
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Vladimir Oltean authored
Switch to using more idiomatic register field definitions, which makes it easier to look them up in the datasheet. Cosmetic patch. Signed-off-by:
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Vladimir Oltean authored
This is a cosmetic patch. Signed-off-by:
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Vladimir Oltean authored
This is a cosmetic patch that changes nothing except makes sure the code is aligned to the same column, which makes it easier to the eye. Signed-off-by:
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Manivannan Sadhasivam authored
The number of CS lines is mentioned as 2 in the spi-controller binding but however in the example, 4 cs-gpios are used. Hence fix that to mention 4. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20190820115000.32041-1-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Axel Lin authored
Use devm_spi_register_controller to fix missing spi_unregister_controller when unload module. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20190818095113.2397-1-axel.lin@ingics.comSigned-off-by:
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- 12 Aug, 2019 1 commit
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Jarkko Nikula authored
Add support for Intel(R) Programmable Services Engine (Intel(R) PSE) SPI controller in Intel Elkhart Lake when interface is assigned to the host processor. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20190812101344.3975-1-jarkko.nikula@linux.intel.comSigned-off-by:
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