- 18 Nov, 2016 9 commits
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git://github.com/hisilicon/linux-hisiOlof Johansson authored
ARM64: DT: Hisilicon SoC DT updates for 4.10 - Correct the hardware pin number of the usb node on the Hip06 - Add the Hisilicon Hip07 D05 board dts binding - Add the initial dts for the Hip07 D05 board - Fix the warning for the node without reg propery on the Hip06 - Fix the sas am max transmissions quirk property on the Hip06 - Disable the sas0 and sas2 on D03 board - Add refclk node for SAS on the Hip06 * tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisi: add refclk node to hip06 dts files for SAS arm64: dts: hisi: disable sas0 and sas2 for d03 arm64: dts: hisi: fix hip06 sas am-max-trans quirk arm64: dts: hip06: Fix no reg property warning arm64: dts: hisilicon: Add initial dts for Hip07 D05 board Documentation: arm64: Add Hisilicon Hip07 D05 dts binding arm64: dts: hip06: Correct hardware pin number of usb node Signed-off-by:
Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB. * tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings Signed-off-by:
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Olof Johansson authored
Merge tag 'qcom-arm64-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Qualcomm ARM64 Updates for v4.10 * Add Hexagon SMD/PIL nodes * Add DB820c PMIC pins * Fixup APQ8016 voltage ranges * Add various MSM8996 nodes to support SMD/SMEM/SMP2P * Add support for Huawei Nexus 6P (Angler) * Add support for LG Nexus 5x (Bullhead) * tag 'qcom-arm64-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support dt-bindings: qcom: Add msm899(2/4) bindings arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support arm64: dts: msm8996: Add SMP2P and APCS nodes arm64: dts: msm8996: Add SMEM DT nodes arm64: dts: msm8996: Add reserve-memory nodes arm64: dts: msm8996: Add SMEM reserve-memory node arm64: dts: apq8016-sbc: add analog audio support with multicodec arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges dts: arm64: db820c: add pmic pins specific dts file arm64: dts: qcom: msm8916: Add Hexagon PIL node arm64: dts: qcom: msm8916: Add Hexagon SMD edge Signed-off-by:
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Olof Johansson authored
Merge branch 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into next/dt64 * 'clk-qcom-8994' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
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Olof Johansson authored
Merge tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 64bit devicetree changes including the px5 evaluation board a fix for wrong i2c registers on rk3368 a new nvmem cell and power-domain on rk3399 as well as moving mmc frequency properties to the more generic max-frequency one. * tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399 arm64: dts: rockchip: add sdmmc support for px5-evb arm64: dts: rockchip: Add more properties for emmc on px5-evb arm64: dts: rockchip: Add PX5 Evaluation board arm64: dts: rockchip: add powerdomain for typec on rk3399 arm64: dts: rockchip: fix i2c resource error of rk3368 Signed-off-by:
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Olof Johansson authored
Merge tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Finally, I am really pleased to announce adding support for Exynos5433 ARMv8 SoC along with two boards. A lot of Samsung people contributed into this but the final work and commits were done by Chanwoo Choi. This means that for v4.10 we got: 1. Exynos5433 DTSI. 2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones. * tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC Signed-off-by:
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Olof Johansson authored
Merge tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64 UniPhier ARM64 SoC DT updates for v4.10 - Switch CPU enable-method from spin-table to PSCI - Add OPP tables to support generic cpufreq driver - Misc fixes * tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: make compatible of syscon nodes SoC-specific arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC arm64: dts: uniphier: increase register region size of sysctrl node arm64: dts: uniphier: switch over to PSCI enable method Signed-off-by:
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Olof Johansson authored
Linux 4.9-rc3 * tag 'v4.9-rc3': (292 commits) Linux 4.9-rc3 x86/smpboot: Init apic mapping before usage ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region() ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method() ACPICA: Dispatcher: Fix order issue of method termination ARC: module: print pretty section names ARC: module: elide loop to save reference to .eh_frame ARC: mm: retire ARC_DBG_TLB_MISS_COUNT... ARC: build: retire old toggles ARC: boot log: refactor cpu name/release printing ARC: boot log: remove awkward space comma from MMU line ARC: boot log: don't assume SWAPE instruction support ARC: boot log: refactor printing abt features not captured in BCRs ARCv2: boot log: print IOC exists as well as enabled status ubifs: Fix regression in ubifs_readdir() ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap() MAINTAINERS: Add entry for genwqe driver VMCI: Doorbell create and destroy fixes GenWQE: Fix bad page access during abort of resource allocation vme: vme_get_size potentially returning incorrect value on failure ...
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Olof Johansson authored
Merge tag 'renesas-arm64-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Renesas ARM64 Based SoC DT Updates for v4.10 Enablement: * Enable On-board eMMC * Enable SDHI 0 & 3 with UHS * Add SYS-DMAC controller nodes to r8a7796 SoC * Populate EXTALR on r8a7796/salvator-x board; used by watchdog * Add DU LVDS output endpoint on r8a7795/salvator-x board * Add bias setting for USB1 pins on r8a7795/salvator-x board Clean-Up: * Remove FCP SoC-specific compatible strings * tag 'renesas-arm64-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: renesas: r8a7796: add SYS-DMAC controller nodes arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pins arm64: dts: r8a7796: salvator: enable on board eMMC arm64: dts: r8a7795: salvator: enable on-board eMMC arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3 arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3 arm64: dts: r8a7796: add SDHI nodes arm64: dts: r8a7795: Remove FCP SoC-specific compatible strings dt-bindings: media: renesas-fcp: Remove SoC-specific compatible strings arm64: dts: r8a7795: salvator-x: Add DU LVDS output endpoint arm64: dts: r8a7796: salvator-x: Populate EXTALR arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3 Signed-off-by:
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- 15 Nov, 2016 9 commits
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John Garry authored
We will only maintain 1 dts for D03 and there are 50MHz and 66MHz versions of D03: so we expect UEFI to update refclk rate in the fdt at boot time. Signed-off-by:
John Garry <john.garry@huawei.com> Reviewed-by:
Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by:
Wei Xu <xuwei5@hisilicon.com>
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John Garry authored
The SAS nodes sas0 and sas2 are not available on d03, so disable them. Signed-off-by:
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John Garry authored
The string for the am max transmissions quirk property is not correct -> fix it. Signed-off-by:
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Kefeng Wang authored
Warning (unit_address_vs_reg): Node /soc/ethernet@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@1 has a unit name, but no reg property Fix warning when build with W=1. Cc: Kejian Yan <yankejian@huawei.com> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Signed-off-by:
Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by:
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Kefeng Wang authored
Adding initial dt file for Hip07 D05 board, it is with dual socket and each socket has two SCCLs(supper cpu cluster), one SCCL contains four clusters and each cluster has quard Cortex-A72. Since each SCCL has their own DDR controller, it could be treated as a separate numa node. Thus, there are four numa nodes(one node with sixteen core) on Hip07 SoC. Signed-off-by:
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Kefeng Wang authored
This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip07 D05 board. Signed-off-by:
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Kefeng Wang authored
The ohci/ehci hardware pin number should be 640/641, correct them. Fixes: commit aa8d3e74 ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board") Signed-off-by:
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Hongtao Jia authored
Also add nodes and properties for thermal management support. Signed-off-by:
Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Hongtao Jia authored
Also add nodes and properties for thermal management support. Signed-off-by:
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- 13 Nov, 2016 8 commits
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Bastian Köcher authored
Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support. The device tree is based on the Google 3.10 kernel tree. The device can be booted into the initrd with only one CPU running. Signed-off-by:
Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: removed Kconfig, defconfig, move from Huawei to qcom dir] Signed-off-by:
Jeremy McNicoll <jeremymc@redhat.com> Tested-by:
Michael Scott <michael.scott@linaro.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Jeremy McNicoll authored
Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jeremy McNicoll authored
Initial device tree support for Qualcomm MSM8992 SoC and LG Bullhead / Google Nexus 5X support. Signed-off-by:
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spjoshi@codeaurora.org authored
Add SMP2P and APCS DT nodes required for Qualcomm ADSP Peripheral Image Loader. Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Sarangdhar Joshi <spjoshi@codeaurora.org> Signed-off-by:
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Bjorn Andersson authored
Add SMEM and TCSR DT nodes on MSM8996. Signed-off-by:
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spjoshi@codeaurora.org authored
Add reserve-memory nodes required for Qualcomm Peripheral Image Loaders Acked-by:
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spjoshi@codeaurora.org authored
Add DT node to carveout memory for shared memory region. Reviewed-by:
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Srinivas Kandagatla authored
This patch add support to Analog audio both Playback and Capture via msm8916 WCD muti codec. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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- 10 Nov, 2016 4 commits
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Bastian Köcher authored
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Rajendra Nayak authored
pm8994 has 22 gpios, so add the missing interrupts entry for one of the gpios Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Archit Taneja authored
On the APQ8016 SBC, the LDO2 PM8916 regulator feeds 1.2V to the following: - VDDA_1P2_MIPI_DSI and VDDA_MIPI_CSI pins on APQ8016. - VCCCAD pins on the LPDDR3 chip. - VDDPX_1 pins on APQ8016. The LDO6 regulator feeds 1.8V to: - VDAA_MIPI_DSI0_PLL pin on APQ8016. - QFPROM_BLOW_VDD pin on PM8916. - The AVDD, A2VDD and DVDD pins on ADV7533 bridge. The LDO17 regulator feeds 3.3V to: - The V3P3 pin on ADV7533 bridge. Currently, the regulator min/max voltages for all the LDOs are set to the range of what the PMIC supports. Set the ranges for L2, L6 and L17 to what we need, i.e. 1.2V, 1.8V and 3.3V respectively. Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
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Jeremy McNicoll authored
Signed-off-by:
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- 09 Nov, 2016 1 commit
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Jaehoon Chung authored
In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- 05 Nov, 2016 5 commits
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Masahiro Yamada authored
These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org>
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Masahiro Yamada authored
Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by:
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Masahiro Yamada authored
The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: -
Masahiro Yamada authored
At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by:
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- 04 Nov, 2016 4 commits
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Ulrich Hecht authored
Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Yoshihiro Shimoda authored
Since this board doesn't mount pull-up/down registers for USB1_{OVC,PWEN} pins, we should enable bias setting to pull these pins up/down. Signed-off-by:Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
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