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- 02 Oct, 2008 4 commits
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Victor Gallardo authored
Basic functionality for the AMCC Arches eval Board. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Victor Gallardo authored
The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Victor Gallardo authored
Add support for the phy types found on the Arches and other PowerPC 460 based boards. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Matthias Fuchs authored
This patch allows the 4xx (conventional) PCI bridge to be disabled via the device tree. This is needed for 4xx PCI adapter hardware. Use the PCI node's status property to disable the PCI bridge. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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- 30 Sep, 2008 3 commits
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Josh Boyer authored
The PowerPC 405EZ SoC has some differences in the interrupt layout and handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into a single interrupt. Also, due to the possibility for interrupt coalescing, the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in the ICINTSTAT SDR. This sets the proper MAL feature bits for 405EZ boards, and adds a common shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR are added to the proper header file as well. This has been adapted from code originally written by Stefan Roese. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
There are some PowerPC SoCs that do odd things with the MAL handling. In order to accommodate them, we need to introduce a feature mechanism that is similar to the existing emac_has_feature function. This adds a feature variable to the mal_instance structure, and adds a mal_has_feature function. Two features are defined and are guarded by Kconfig options that are selected by the affected platforms. MAL_FTR_CLEAR_ICINSTAT is used for platforms that need to clear the interrupt bits in the ICINTSTAT SDR for txeob/rxeob. This is common on MAL implementations that have interrupt coalescing. MAL_FTR_COMMON_ERR_INT is used for platforms that have SERR, TXDE, and RXDE OR'd into a single interrupt bit. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Some PowerPC 40x chips have errata that force us not to use the integrated flow control. We have the feature defined, but it currently can't be used because it is never added to EMAC_FTRS_POSSIBLE. This adds a Kconfig option for affected platforms to select and puts the feature in the EMAC_FTRS_POSSIBLE list. This is set for PowerPC 405EZ platforms as well. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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- 21 Sep, 2008 2 commits
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Paul Mackerras authored
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- 19 Sep, 2008 2 commits
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Becky Bruce authored
We're currently passing NULL, and really shouldn't be. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-By: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- 18 Sep, 2008 1 commit
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Kumar Gala authored
arch/powerpc/kernel/sysfs.c:197:7: warning: "CONFIG_6xx" is not defined arch/powerpc/kernel/sysfs.c:141: warning: 'run_on_cpu' defined but not used Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- 17 Sep, 2008 1 commit
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Timur Tabi authored
Add the fsl,playback-dma and fsl,capture-dma properties to the Freescale MPC8610 HPCD device tree. These properties connect the SSI nodes to the DMA nodes for the DMA channels that the SSI should use. Also update the ssi.txt documentation. These properties will be needed when the ASoC V2 version of the Freescale MPC8610 device drivers are merged into the mainline. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- 16 Sep, 2008 11 commits
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Jochen Friedrich authored
The CPM1 GPIO library code uses the non thread-safe clrbits32/setbits32 macros. This patch protects them with a spinlock. Based on the CPM2 patch from Laurent Pinchart <laurentp@cse-semaphore.com>, commit 639d6445. Signed-off-by: Jochen Friedrich <jochen@scram.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Martyn Welch authored
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the basic board support for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
This is just a parallel of a5dc66e2 applied to the sbc8560 board. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Some architectures (like powerpc) provide status information on the exact type of invalid exception. This is pretty straight forward as we already report invalid exceptions via FP_SET_EXCEPTION. We add new flags (FP_EX_INVALID_*) the architecture code can define if it wants the exact invalid exception reported. We had to split out the INF/INF and 0/0 cases for divide to allow reporting the two invalid forms properly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: David S. Miller <davem@davemloft.net>
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Kumar Gala authored
Fix warnings of the form: arch/powerpc/math-emu/fsubs.c:15: warning: 'R_f1' may be used uninitialized in this function arch/powerpc/math-emu/fsubs.c:15: warning: 'R_f0' may be used uninitialized in this function Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Becky Bruce authored
This fixes a build warning when PHYS_64BIT is enabled, and removes an unnecessary cast to phys_addr_t (the variable being cast is already a phys_addr_t) Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
This patch adds the localbus node, moves the bcsr node into the localbus node, and adds the flash node. Also enable MTD support in the defconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
With the change to device tree based setup we no longer need the explicit Kconfig options for each SCC{1,4} or SMC{1,2} port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
Supported SMC1 (serial console), SCC3 Ethernet (10Mbps hdx). Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- 15 Sep, 2008 16 commits
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Martin Langer authored
Some 74xx cores by Freescale are using the configuration field instead of the major revision field for their revision number. This corrects the wrong behaviour for those ppc cores including my one. There is a reference document at Freecale. It describes the PVR register. This is based on that pdf. You can find the document at: http://www.freescale.com/files/archives/doc/support_info/PPCPVR.pdfSigned-off-by: Martin Langer <martin-langer@gmx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
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David Gibson authored
There is a small bug in the handling of 16G hugepages recently added to the kernel. This doesn't cause a crash or other user-visible problems, but it does mean that more levels of pagetable are allocated than makes sense for 16G pages. The hugepage pagetables for the 16G pages are allocated much lower in the pagetable tree than they should be, with the intervening levels allocated with full pmd and pud pages which will only ever have one entry filled in. This corrects this problem, at the same time cleaning up the handling of which level 64k versus 16M hugepage pagetables are allocated at. The new way of formatting the tests should be more robust against changes in pagetable structure, or any newly added hugepage sizes. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Sebastien Dugue authored
The radix trees used by interrupt controllers for their irq reverse mapping (currently only the XICS found on pSeries) have a complex locking scheme dating back to before the advent of the lockless radix tree. This takes advantage of the lockless radix tree and of the fact that the items of the tree are pointers to a static array (irq_map) elements which can never go under us to simplify the locking. Concurrency between readers and writers is handled by the intrinsic properties of the lockless radix tree. Concurrency between writers is handled with a global mutex. Signed-off-by: Sebastien Dugue <sebastien.dugue@bull.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Sebastien Dugue authored
irq_radix_revmap() currently serves 2 purposes, irq mapping lookup and insertion which happen in interrupt and process context respectively. Separate the function into its 2 components, one for lookup only and one for insertion only. Fix the only user of the revmap tree (XICS) to use the new functions. Also, move the insertion into the radix tree of those irqs that were requested before it was initialized at said tree initialization. Mutual exclusion between the tree initialization and readers/writers is handled via a state variable (revmap_trees_allocated) set to 1 when the tree has been initialized and set to 2 after the already requested irqs have been inserted in the tree by the init path. This state is checked before any reader or writer access just like we used to check for tree.gfp_mask != 0 before. Finally, now that we're not any longer inserting nodes into the radix-tree in interrupt context, turn the GFP_ATOMIC allocations into GFP_KERNEL ones. Signed-off-by: Sebastien Dugue <sebastien.dugue@bull.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Becky Bruce authored
It's the size of the hardware PTE; make that clear in the name. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Thiemo Seufer authored
Those two are required on my fresh gcc 4.3.1. Signed-off-by: Thiemo Seufer <ths@linutronix.de> Signed-off-by: Sebastian Siewior <bigeasy@linutronix.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Christoph Hellwig authored
sys32_pause is a useless copy of the generic sys_pause. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as a position-independent executable (PIE) when it is set. This involves processing the dynamic relocations in the image in the early stages of booting, even if the kernel is being run at the address it is linked at, since the linker does not necessarily fill in words in the image for which there are dynamic relocations. (In fact the linker does fill in such words for 64-bit executables, though not for 32-bit executables, so in principle we could avoid calling relocate() entirely when we're running a 64-bit kernel at the linked address.) The dynamic relocations are processed by a new function relocate(addr), where the addr parameter is the virtual address where the image will be run. In fact we call it twice; once before calling prom_init, and again when starting the main kernel. This means that reloc_offset() returns 0 in prom_init (since it has been relocated to the address it is running at), which necessitated a few adjustments. This also changes __va and __pa to use an equivalent definition that is simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are constants (for 64-bit) whereas PHYSICAL_START is a variable (and KERNELBASE ideally should be too, but isn't yet). With this, relocatable kernels still copy themselves down to physical address 0 and run there. Signed-off-by: Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
This changes the way that the exception prologs transfer control to the handlers in 64-bit kernels with the aim of making it possible to have the prologs separate from the main body of the kernel. Now, instead of computing the address of the handler by taking the top 32 bits of the paca address (to get the 0xc0000000........ part) and ORing in something in the bottom 16 bits, we get the base address of the kernel by doing a load from the paca and add an offset. This also replaces an mfmsr and an ori to compute the MSR value for the handler with a load from the paca. That makes it unnecessary to have a separate version of EXCEPTION_PROLOG_PSERIES that forces 64-bit mode. We can no longer use a direct branches in the exception prolog code, which means that the SLB miss handlers can't branch directly to .slb_miss_realmode any more. Instead we have to compute the address and do an indirect branch. This is conditional on CONFIG_RELOCATABLE; for non-relocatable kernels we use a direct branch as before. (A later change will allow CONFIG_RELOCATABLE to be set on 64-bit powerpc.) Since the secondary CPUs on pSeries start execution in the first 0x100 bytes of real memory and then have to get to wherever the kernel is, we can't use a direct branch to get there. Instead this changes __secondary_hold_spinloop from a flag to a function pointer. When it is set to a non-NULL value, the secondary CPUs jump to the function pointed to by that value. Finally this eliminates one code difference between 32-bit and 64-bit by making __secondary_hold be the text address of the secondary CPU spinloop rather than a function descriptor for it. Signed-off-by: Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
This rearranges head_64.S so that we have all the first-level exception prologs together starting at 0x100, followed by all the second-level handlers that are invoked from the first-level prologs, followed by other code. This doesn't make any functional change but will make following changes for relocatable kernel support easier. Signed-off-by: Paul Mackerras <paulus@samba.org>
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Chandru authored
Kdump kernel needs to use only those memory regions that it is allowed to use (crashkernel, rtas, tce, etc.). Each of these regions have their own sizes and are currently added under 'linux,usable-memory' property under each memory@xxx node of the device tree. The ibm,dynamic-memory property of ibm,dynamic-reconfiguration-memory node (on POWER6) now stores in it the representation for most of the logical memory blocks with the size of each memory block being a constant (lmb_size). If one or more or part of the above mentioned regions lie under one of the lmb from ibm,dynamic-memory property, there is a need to identify those regions within the given lmb. This makes the kernel recognize a new 'linux,drconf-usable-memory' property added by kexec-tools. Each entry in this property is of the form of a count followed by that many (base, size) pairs for the above mentioned regions. The number of cells in the count value is given by the #size-cells property of the root node. Signed-off-by: Chandru Siddalingappa <chandru@in.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Nathan Fontenot authored
The return code from invocation of the notifier for pSeries_reconfig_chain during update of the device tree is not checked. This causes writes to /proc/ppc64/ofdt to update memory properties (i.e. ibm,dyamic-reconfiguration-memory) to always return success, instead of the result of the notifier chain. This happens specifically when we remove/add memory from the device tree on machines using memory specified in the ibm,dynamic-reconfiguration-memory property of the device tree. Signed-off-by: Nathan Fontenot <nfont@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Mark Nelson authored
This new copy_4K_page() function was originally tuned for the best performance on the Cell processor, but after testing on more 64bit powerpc chips it was found that with a small modification it either matched the performance offered by the current mainline version or bettered it by a small amount. It was found that on a Cell-based QS22 blade the amount of system time measured when compiling a 2.6.26 pseries_defconfig decreased by 4%. Using the same test, a 4-way 970MP machine saw a decrease of 2% in system time. No noticeable change was seen on Power4, Power5 or Power6. The 4096 byte page is copied in thirty-two 128 byte strides. An initial setup loop executes dcbt instructions for the whole source page and dcbz instructions for the whole destination page. To do this, the cache line size is retrieved from ppc64_caches. A new CPU feature bit, CPU_FTR_CP_USE_DCBTZ, (introduced in the previous patch) is used to make the modification to this new copy routine - on Power4, 970 and Cell the feature bit is set so the setup loop is executed, but on all other 64bit chips the setup loop is nop'ed out. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Mark Nelson authored
Add a new CPU feature bit, CPU_FTR_CP_USE_DCBTZ, to be added to the 64bit powerpc chips that benefit from having dcbt and dcbz instructions used in their memory copy routines. This will be used in a subsequent patch that updates copy_4K_page(). The new bit is added to Cell, PPC970 and Power4 because they show better performance with the new copy_4K_page() when dcbt and dcbz instructions are used. Signed-off-by: Mark Nelson <markn@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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roel kluin authored
Evidently MACIO_FLAG_SCCA_ON was meant. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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