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  1. 19 Apr, 2016 1 commit
  2. 30 Jan, 2016 1 commit
  3. 29 Jan, 2016 2 commits
    • Geliang Tang's avatar
      clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h · 5fd9c05c
      Geliang Tang authored
      to_clk_*(_hw) macros have been repeatedly defined in many places.
      This patch moves all the to_clk_*(_hw) definitions in the common
      clock framework to public header clk-provider.h, and drop the local
      definitions.
      Signed-off-by: default avatarGeliang Tang <geliangtang@163.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      5fd9c05c
    • Heiko Stuebner's avatar
      clk-divider: make sure read-only dividers do not write to their register · 50359819
      Heiko Stuebner authored
      Commit e6d5e7d9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
      the special ops struct for read-only clocks and instead opted to handle
      them inside the regular ops.
      
      On the rk3368 this results in breakage as aclkm now gets set a value.
      While it is the same divider value, the A53 core still doesn't like it,
      which can result in the cpu ending up in a hang.
      The reason being that "ACLKENMasserts one clock cycle before the rising
      edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
      is asserted.
      
      To fix this, reintroduce the read-only ops but do include the round_rate
      callback. That way no writes that may be unsafe are done to the divider
      register in any case.
      
      The Rockchip use of the clk_divider_ops is adapted to this split again,
      as is the nxp, lpc18xx-ccu driver that was included since the original
      commit. On lpc18xx-ccu the divider seems to always be read-only
      so only uses the new ops now.
      
      Fixes: e6d5e7d9 ("clk-divider: Fix READ_ONLY when divider > 1")
      Reported-by: default avatarZhang Qing <zhangqing@rock-chips.com>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      50359819
  4. 01 Dec, 2015 1 commit
    • Stephen Boyd's avatar
      clk: divider: Cap table divider values to 'width' member · fab88ca7
      Stephen Boyd authored
      When we use a clk divider with a divider table, we limit the
      maximum divider value in divider_get_val() to the
      div_mask(width), but when we calculate the divider in
      divider_round_rate() we don't consider that the maximum divider
      may be limited by the width. Pass the width along to
      _get_table_maxdiv() so that we only return the maximum divider
      that is valid. This is useful for clocks that want to share the
      same divider table while limiting the available dividers to some
      subset of the table depending on the width of the bitfield.
      
      Cc: Rajendra Nayak <rnayak@codeaurora.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      fab88ca7
  5. 16 Sep, 2015 1 commit
    • Brian Norris's avatar
      clk: divider: handle integer overflow when dividing large clock rates · 9556f9da
      Brian Norris authored
      On 32-bit architectures, 'unsigned long' (the type used to hold clock
      rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in,
      e.g., commit b11d282d "clk: divider: fix rate calculation for
      fractional rates") can yield an integer overflow on clock rates that are
      not (by themselves) too large to fit in 32 bits, because it performs
      addition before the division. See for example:
      
        DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G
                                             = OVERFLOW / 1.5G
      
      This patch fixes such cases by always promoting the dividend to 64-bits
      (unsigned long long) before doing the division. While this patch does
      not resolve the issue with large clock rates across the common clock
      framework nor address the problems with doing full 64-bit arithmetic on
      a 32-bit architecture, it does fix some issues seen when using clock
      dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an
      ARMv7 Brahma B15 SoC.
      Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
      Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      9556f9da
  6. 24 Aug, 2015 2 commits
  7. 28 Jul, 2015 2 commits
    • Stephen Boyd's avatar
      clk: basic-type: Silence warnings about lock imbalances · 661e2180
      Stephen Boyd authored
      The basic clock types use conditional locking for the register
      accessor spinlocks. Add __acquire() and __release() markings in
      the right locations so that sparse isn't tripped up on the
      conditional locking.
      
      drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
      drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
      drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
      drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
      drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block
      
      Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      661e2180
    • Jim Quinlan's avatar
      clk: allow a clk divider with max divisor when zero · afe76c8f
      Jim Quinlan authored
      This commit allows certain Broadcom STB clock dividers to be used with
      clk-divider.c.  It allows for a clock whose field value is the equal
      to the divisor, execpt when the field value is zero, in which case the
      divisor is 2^width.  For example, consider a divisor clock with a two
      bit field:
      
      value		divisor
      0		4
      1		1
      2		2
      3		3
      Signed-off-by: default avatarJim Quinlan <jim2101024@gmail.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      afe76c8f
  8. 14 May, 2015 1 commit
  9. 09 Mar, 2015 3 commits
  10. 06 Mar, 2015 1 commit
  11. 27 Jan, 2015 1 commit
  12. 17 Jan, 2015 1 commit
  13. 17 Nov, 2014 1 commit
    • James Hogan's avatar
      clk-divider: Fix READ_ONLY when divider > 1 · e6d5e7d9
      James Hogan authored
      Commit 79c6ab50 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
      v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
      recalc_rate() and round_rate() clock callbacks to be omitted.
      
      However using this flag has the unfortunate side effect of causing the
      clock recalculation code when a clock rate change is attempted to always
      treat it as a pass-through clock, i.e. with a fixed divide of 1, which
      may not be the case. Child clock rates are then recalculated using the
      wrong parent rate.
      
      Therefore instead of dropping the recalc_rate() and round_rate()
      callbacks, alter clk_divider_bestdiv() to always report the current
      divider as the best divider so that it is never altered.
      
      For me the read only clock was the system clock, which divided the PLL
      rate by 2, from which both the UART and the SPI clocks were divided.
      Initial setting of the UART rate set it correctly, but when the SPI
      clock was set, the other child clocks were miscalculated. The UART clock
      was recalculated using the PLL rate as the parent rate, resulting in a
      UART new_rate of double what it should be, and a UART which spewed forth
      garbage when the rate changes were propagated.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Thomas Abraham <thomas.ab@samsung.com>
      Cc: Tomasz Figa <t.figa@samsung.com>
      Cc: Max Schwarz <max.schwarz@online.de>
      Cc: <stable@vger.kernel.org> # v3.16+
      Acked-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      e6d5e7d9
  14. 28 May, 2014 1 commit
    • Tomasz Figa's avatar
      clk: divider: Fix overflow in clk_divider_bestdiv · 3c17296f
      Tomasz Figa authored
      Commit c686078 ("clk: divider: Add round to closest divider") introduced
      a helper function to check whether given divisor is the best one instead
      of direct check. However due to int type used instead of unsigned long
      for passing calculated rates to this function in certain cases an
      overflow could occur, for example when trying to obtain maximum possible
      clock rate by calling clk_round_rate(..., UINT_MAX).
      
      This patch fixes this issue by changing the type of rate, now and best
      arguments of the function to unsigned long, which is the type that
      should be used for clock rates.
      Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
      Acked-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      3c17296f
  15. 23 May, 2014 2 commits
  16. 30 Apr, 2014 3 commits
  17. 27 Feb, 2014 1 commit
    • Tomi Valkeinen's avatar
      clk: divider: fix rate calculation for fractional rates · b11d282d
      Tomi Valkeinen authored
      clk-divider.c does not calculate the rates consistently at the moment.
      
      As an example, on OMAP3 we have a clock divider with a source clock of
      864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:
      
      6: 144000000
      7: 123428571.428571...
      8: 108000000
      
      Calling clk_round_rate() with the rate in the first column will give the
      rate in the second column:
      
      144000000 -> 144000000
      143999999 -> 123428571
      123428572 -> 123428571
      123428571 -> 108000000
      
      Note how clk_round_rate() returns 123428571 for rates from 123428572 to
      143999999, which is mathematically correct, but when clk_round_rate() is
      called with 123428571, the returned value is surprisingly 108000000.
      
      This means that the following code works a bit oddly:
      
      rate = clk_round_rate(clk, 123428572);
      clk_set_rate(clk, rate);
      
      As clk_set_rate() also does clock rate rounding, the result is that the
      clock is set to the rate of 108000000, not 123428571 returned by the
      clk_round_rate.
      
      This patch changes the clk-divider.c to use DIV_ROUND_UP when
      calculating the rate. This gives the following behavior which fixes the
      inconsistency:
      
      144000000 -> 144000000
      143999999 -> 123428572
      123428572 -> 123428572
      123428571 -> 108000000
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      b11d282d
  18. 08 Jan, 2014 1 commit
    • James Hogan's avatar
      clk: clk-divider: fix divisor > 255 bug · 778037e1
      James Hogan authored
      Commit 6d9252bd (clk: Add support for power of two type dividers)
      merged in v3.6 added the _get_val function to convert a divisor value to
      a register field value depending on the flags. However it used the type
      u8 for the div field, causing divisors larger than 255 to be masked
      and the resultant clock rate to be too high.
      
      E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
      to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
      was masked to 238 (0xee) resulting in a frequency of 103.26KHz.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      778037e1
  19. 28 Aug, 2013 1 commit
  20. 16 Aug, 2013 1 commit
  21. 16 Jun, 2013 1 commit
  22. 10 Jun, 2013 1 commit
    • Shawn Guo's avatar
      clk: divider: do not propagate rate change request when unnecessary · 081c9025
      Shawn Guo authored
      If the current rate of parent clock is sufficient to provide child a
      requested rate with a proper divider setting, the rate change request
      should not be propagated.  Instead, changing the divider setting is good
      enough to get child clock run at the requested rate.
      
      On an imx6q clock configuration illustrated below,
      
        ahb --> ipg --> ipg_per
        132M    66M     66M
      
      calling clk_set_rate(ipg_per, 22M) with the current
      clk_divider_bestdiv() implementation will result in the rate change up
      to ahb level like the following, because of the unnecessary/incorrect
      rate change propagation.
      
        ahb --> ipg --> ipg_per
        66M     22M     22M
      
      Fix the problem by trying to see if the requested rate can be achieved
      by simply changing the divider value, and in that case return the
      divider immediately from function clk_divider_bestdiv() as the best
      one, so that all those unnecessary rate change propagation can be saved.
      Reported-by: default avatarAnson Huang <b20788@freescale.com>
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      081c9025
  23. 03 Apr, 2013 1 commit
  24. 18 Jan, 2013 1 commit
    • James Hogan's avatar
      clk-divider: fix macros · 1a3cd184
      James Hogan authored
      The macro is_power_of_two() in clk-divider.c was defined as !(i & ~i)
      which is always true.  Instead use is_power_of_2() from log2.h.
      
      Also add brackets around the macro arguments in div_mask to avoid any
      future operator precedence problems.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Joe Perches <joe@perches.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      [mturquette@linaro.org: use log2.h per Joe Perches; update changelog]
      1a3cd184
  25. 11 Jul, 2012 3 commits
    • Rajendra Nayak's avatar
      clk: Add CLK_IS_BASIC flag to identify basic clocks · f7d8caad
      Rajendra Nayak authored
      Most platforms end up using a mix of basic clock types and
      some which use clk_hw_foo struct for filling in custom platform
      information when the clocks don't fit into basic types supported.
      
      In platform code, its useful to know if a clock is using a basic
      type or clk_hw_foo, which helps platforms know if they can
      safely use to_clk_hw_foo to derive the clk_hw_foo pointer from
      clk_hw.
      
      Mark all basic clocks with a CLK_IS_BASIC flag.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      f7d8caad
    • Rajendra Nayak's avatar
      clk: Add support for rate table based dividers · 357c3f0a
      Rajendra Nayak authored
      Some divider clks do not have any obvious relationship
      between the divider and the value programmed in the
      register. For instance, say a value of 1 could signify divide
      by 6 and a value of 2 could signify divide by 4 etc.
      Also there are dividers where not all values possible
      based on the bitfield width are valid. For instance
      a 3 bit wide bitfield can be used to program a value
      from 0 to 7. However its possible that only 0 to 4
      are valid values.
      
      All these cases need the platform code to pass a simple
      table of divider/value tuple, so the framework knows
      the exact value to be written based on the divider
      calculation and can also do better error checking.
      
      This patch adds support for such rate table based
      dividers and as part of the support adds a new
      registration function 'clk_register_divider_table()'
      and a new macro for static definition
      'DEFINE_CLK_DIVIDER_TABLE'.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      357c3f0a
    • Rajendra Nayak's avatar
      clk: Add support for power of two type dividers · 6d9252bd
      Rajendra Nayak authored
      Quite often dividers and the value programmed in the
      register have a relation of 'power of two', something like
      value	div
      0	1
      1	2
      2	4
      3	8...
      
      Add support for such dividers as part of clk-divider.
      
      The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used
      to define such clocks.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      6d9252bd
  26. 02 May, 2012 1 commit
    • Saravana Kannan's avatar
      clk: Use a separate struct for holding init data. · 0197b3ea
      Saravana Kannan authored
      Create a struct clk_init_data to hold all data that needs to be passed from
      the platfrom specific driver to the common clock framework during clock
      registration. Add a pointer to this struct inside clk_hw.
      
      This has several advantages:
      * Completely hides struct clk from many clock platform drivers and static
        clock initialization code that don't care for static initialization of
        the struct clks.
      * For platforms that want to do complete static initialization, it removed
        the need to directly mess with the struct clk's fields while still
        allowing to statically allocate struct clk. This keeps the code more
        future proof even if they include clk-private.h.
      * Simplifies the generic clk_register() function and allows adding optional
        fields in the future without modifying the function signature.
      * Simplifies the static initialization of clocks on all platforms by
        removing the need for forward delcarations or convoluted macros.
      Signed-off-by: default avatarSaravana Kannan <skannan@codeaurora.org>
      [mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Arnd Bergman <arnd.bergmann@linaro.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Shawn Guo <shawn.guo@freescale.com>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Jamie Iles <jamie@jamieiles.com>
      Cc: Richard Zhao <richard.zhao@linaro.org>
      Cc: Saravana Kannan <skannan@codeaurora.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: Linus Walleij <linus.walleij@stericsson.com>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Cc: Amit Kucheria <amit.kucheria@linaro.org>
      Cc: Deepak Saxena <dsaxena@linaro.org>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      0197b3ea
  27. 24 Apr, 2012 4 commits