- 28 Apr, 2020 33 commits
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Huang Rui authored
This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Huang Rui authored
Add a function to check tmz capability with kernel parameter and ASIC type. v2: use a per device tmz variable instead of global amdgpu_tmz. v3: refine the comments for the function. (Luben) v4: add amdgpu_tmz.c/h for future use. Signed-off-by:
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Huang Rui authored
This patch to add amdgpu_tmz structure which stores all tmz related fields. Signed-off-by:
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Huang Rui authored
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel module. Nomally, by default, it should be auto (rely on the hardware capability). But right now, it need to set "off" to avoid breaking other developers' work because it's not totally completed. Will set "auto" till the feature is stable and completely verified. v2: add "auto" option for future use. Signed-off-by:
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Alex Deucher authored
Define the TMZ (encryption) bit in the page table entry (PTE) for Raven and newer asics. Signed-off-by:
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Luben Tuikov authored
Add a flag to the command submission IOCTL structure which when present indicates that this command submission should be treated as secure. The kernel driver uses this flag to determine whether the engine should be transitioned to secure or unsecure, or the work can be submitted to a secure queue depending on the IP. v3: the flag is now at command submission IOCTL Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Alex Deucher authored
Add a flag to the GEM_CREATE ioctl to create encrypted buffers. Buffers with this flag set will be created with the TMZ bit set in the PTEs or engines accessing them. This is required in order to properly access the data from the engines. Signed-off-by:
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Aric Cyr authored
Update firmware blobs Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Aric Cyr authored
[Why] Current locking scheme for cursor can result in a flip missing its vsync, deferring it for one or more vsyncs. Result is a potential for stuttering when cursor is moved. [How] Use cursor update lock so that flips are not blocked while cursor is being programmed. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Krunoslav Kovac authored
[Why&How] modules/color calculates various colour operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. We would hack it with some DCN checks, but a better approach is to abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities, Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] Add set backlight to hw sequencer, dmu communication will be handled in hw sequencer for new asics. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] For debugging, it can be useful to be able to modify the dummy p-state latency, this will make it easier to do so. Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] Add panel cntl instance when calling set backlight. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd. [How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead. Signed-off-by:
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Sung Lee authored
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Fixes the following scenario: - Flip has been prepared sometime during the frame, update pending - Cursor update happens right when VUPDATE would happen - OPTC lock acquired, VUPDATE is blocked until next frame - Flip is delayed potentially infinitely With the igt@kms_cursor_legacy cursor-vs-flip-legacy test we can observe nearly *13* frames of delay for some flips on Navi. [How] Apply the Raven workaround generically. When close enough to VUPDATE block cursor updates from occurring from the dc_stream_set_cursor_* helpers. This could perhaps be a little smarter by checking if there were pending updates or flips earlier in the frame on the HUBP side before applying the delay, but this should be fine for now. This fixes the kms_cursor_legacy test. Signed-off-by:
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Sung Lee authored
[WHY & HOW] Viewport limit was set to 16 pixels due to an issue with MPO on small viewports. This restriction does not apply and the viewport limit can now be lowered. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Sung Lee authored
[WHY & HOW] If building scaling parameters fails, validation should also fail. Signed-off-by:
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Dmytro Laktyushkin authored
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Check before programming the register since it isn't present on all IPs using this code. Signed-off-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Joshua Aberback authored
Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
[Why] Some include paths don't need to have relative paths And some types missing [How] make some changes to headers and modify include path Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The new metadata offset is located at the end of the firmware binary without any additional padding. Firmware state is currently larger than 1024 bytes so new firmware state will hang when trying to access any data above 1024 bytes. [How] Specify the correct offset based on legacy vs new loading method. Signed-off-by:
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Sung Lee authored
[WHY] If mode is not supported, pipe split should not be disabled. This may cause more modes to fail. [HOW] Check for mode support before disabling pipe split. This commit was previously reverted as it was thought to have problems, but those issues have been resolved. Signed-off-by:
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Aric Cyr authored
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Marek Olšák authored
This fixes GPU hangs due to cache coherency issues. Bump the driver version. Split out from the original patch. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Marek Olšák authored
This fixes GPU hangs due to cache coherency issues. v2: Split the version bump to a separate patch Signed-off-by:
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Marek Olšák authored
DCC_INDEPENDENT_128B is needed for displayble DCC on gfx10. SCANOUT is not needed by the kernel, but Mesa uses it. Signed-off-by:
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James Zhu authored
Wait for tiles off after unpause to fix transcode timeout issue. It is a work around. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Tiecheng Zhou authored
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to soc15_asic_reset (for V320 usecase, Vega10 asic), in which: 1) soc15_asic_reset_method calls to pp_get_asic_baco_capability (pm_en) 2) soc15_asic_baco_reset calls to pp_set_asic_baco_state (pm_en) pm_en is used in the above two cases while it has not yet been initialized So avoid using pm_en in the above two functions for V320 passthrough. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
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Tiecheng Zhou authored
This reverts commit c5207876. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Reviewed-by:
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Joseph Greathouse authored
In order to surface the ASIC revision to user level, we want to put it into the HSA topology. This can be because different ASIC revisions may require user-level software to do different things (e.g. patch code for things that are changed in later hardware revisions). The ASIC revision from the hardware is maximum of 4 bits at this time, so put it into 4 of the open bits in the HSA capability. Then user-level software can use this capability information to know -- for each ASIC -- what revision-based things must be done. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- 27 Apr, 2020 7 commits
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Jason Yan authored
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:602:28-33: WARNING: conversion to bool not needed here Reviewed-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Jason Yan authored
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c:455:70-75: WARNING: conversion to bool not needed here Reviewed-by:
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Jason Yan authored
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3004:68-73: WARNING: conversion to bool not needed here Reviewed-by:
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Guchun Chen authored
Due to hardware bug that when RSMU UMC index is disabled, clear EccErrCnt at the first UMC instance will clean up all other EccErrCnt registes from other instances at the same time. This will break the correctable error count log in EccErrCnt register once querying it. So decouple both to make error count query workable. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Guchun Chen authored
This makes consistent with other regsiters' access in this module. Signed-off-by:
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Evan Quan authored
CG/PG ungate is already performed in ip_suspend_phase1. Otherwise, the CG/PG ungate will be performed twice. That will cause gfxoff disablement is performed twice also on runpm enter while gfxoff enablemnt once on rump exit. That will put gfxoff into disabled state. Signed-off-by:
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Evan Quan authored
This sequence change should be safe as what did in ip_suspend_phase1 is to suspend DCE only. And this is a prerequisite for coming redundant cg/pg ungate dropping. Signed-off-by:
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