- 04 Jun, 2018 8 commits
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Stephen Boyd authored
Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk-debugfs-simple' into clk-next * clk-imx7d: clk: imx7d: reset parent for mipi csi root clk: imx7d: fix mipi dphy div parent * clk-hisi-stub: clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB * clk-mvebu: clk: mvebu: use correct bit for 98DX3236 NAND * clk-imx6-epit: clk: imx6: add EPIT clock support * clk-debugfs-simple: clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions
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Stephen Boyd authored
* clk-imx6sx: clk: imx6sl: correct ocram_podf clock type clk: imx6sx: disable unnecessary clocks during clock initialization clk: imx6sx: add missing lvds2 clock to the clock tree * clk-imx7d-enet: ARM: dts: imx7: correct enet ipg clock clk: imx7d: correct enet clock CCGR registers clk: imx7d: correct enet phy ref clock gates * clk-aspeed-24: clk: aspeed: Add 24MHz fixed clock
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Stephen Boyd authored
Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next * clk-allwinner: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU * clk-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper * clk-tegra: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers * clk-berlin: clk: berlin: switch to SPDX license identifier * clk-qcom-mmagic: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled clk: qcom: Register the gdscs before the clocks clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
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Stephen Boyd authored
Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next * clk-hisi-usb: clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC * clk-silent-bulk: clk: bulk: silently error out on EPROBE_DEFER * clk-mtk-hdmi: clk: mediatek: correct the clocks for MT2701 HDMI PHY module * clk-mtk-mali: clk: mediatek: add g3dsys support for MT2701 and MT7623 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add g3dsys bindings * clk-imx6ul-ccosr: clk: imx: Add new clo01 and clo2 controlled by CCOSR
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Stephen Boyd authored
Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10' and 'clk-aspeed' into clk-next * clk-stm32mp1: clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()' clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock clk: stm32mp1: remove ck_apb_dbg clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: add missing static * clk-samsung: clk: samsung: simplify getting .drvdata * clk-uniphier-mpeg: clk: uniphier: add LD11/LD20 stream demux system clock * clk-stratix10: clk: socfpga: stratix10: suppress unbinding platform's clock driver clk: socfpga: stratix10: use platform driver APIs * clk-aspeed: clk:aspeed: Fix reset bits for PCI/VGA and PECI clk: aspeed: Support second reset register
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Stephen Boyd authored
Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and 'clk-qcom-rcg-fix' into clk-next * clk-qcom-rpmh: dt-bindings: clock: Introduce QCOM RPMh clock bindings * clk-npcm7xx: clk: npcm7xx: fix return value check in npcm7xx_clk_init() clk: npcm7xx: add clock controller dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock * clk-of-parent-count: pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding clk: Extract OF clock helpers in <linux/of_clk.h> * clk-qcom-rcg-fix: clk: qcom: Base rcg parent rate off plan frequency
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Stephen Boyd authored
* clk-actions: clk: actions: Add S900 SoC clock support clk: actions: Add pll clock support clk: actions: Add composite clock support clk: actions: Add fixed factor clock support clk: actions: Add factor clock support clk: actions: Add divider clock support clk: actions: Add mux clock support clk: actions: Add gate clock support clk: actions: Add common clock driver support dt-bindings: clock: Add Actions S900 clock bindings
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Stephen Boyd authored
* clk-warn: clk: Print the clock name and warning cause * clk-core: clk: Remove clk_init_cb typedef * clk-spear: clk: spear: fix WDT clock definition on SPEAr600 * clk-qcom-msm8998: clk: qcom: Add MSM8998 Global Clock Control (GCC) driver
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- 02 Jun, 2018 7 commits
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Stephen Boyd authored
We only have two users of the debug_init hook, and we recently stopped caring about the return value from that op. Finish that off by changing the clk_op to return void instead of int because it doesn't matter if debugfs fails or not. Cc: Eric Anholt <eric@anholt.net> Cc: David Lechner <david@lechnology.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:Stephen Boyd <sboyd@kernel.org>
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Greg Kroah-Hartman authored
No one was using this api call, so remove it. If it is ever needed in the future, a "raw" debugfs call can be used. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. The return value of these functions were never checked in the end anyway, so it is obvious this does not change any functionality :) Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Acked-by:
David Lechner <david@lechnology.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Phil Elwell <phil@raspberrypi.org> Cc: Boris Brezillon <boris.brezillon@bootlin.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Danilo Krummrich <danilokrummrich@dk-develop.de> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. This cleans up the init code a lot, and there's no need to return an error value based on the debugfs calls, especially as it turns out no one was even looking at that return value. So it obviously wasn't that important :) Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by:
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Colin Didier authored
Add EPIT clock support to the i.MX6Q clocking infrastructure. Signed-off-by:
Colin Didier <colin.didier@devialet.com> Signed-off-by:
Clément Peron <clement.peron@devialet.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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- 01 Jun, 2018 17 commits
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Chris Packham authored
The correct fieldbit value for the NAND PLL reload trigger is 27. Fixes: commit e120c17a ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
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Daniel Lezcano authored
The current defconfig is inconsistent as it selects the mailbox and the clock for the hi6220 and the hi3660 without having their Kconfigs making sure the dependencies are correct. It ends up when selecting different versions for the kernel (for example when git bisecting) those options disappear and they don't get back, leading to unexpected behaviors. In our case, the cpufreq driver does no longer work because the clock fails to initialize due to the clock stub and the mailbox missing. In order to have the dependencies correctly set when defaulting, let's do the same as commit 3a49afb8 ("clk: enable hi655x common clk automatically") where we select automatically the driver when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Rui Miguel Silva authored
To guarantee that we do not get Overflow in image FIFO the outer bandwidth has to be faster than inputer bandwidth. For that it must be possible to set a faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi block. Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by:
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Rui Miguel Silva authored
Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan clock and set the correct parent. before: cat clk_orphan_summary enable prepare protect clock count count count rate accuracy phase ---------------------------------------------------------------------------------------- mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 cat clk_dump | grep mipi_dphy mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 after: cat clk_dump | grep mipi_dphy mipi_dphy_src 1 1 0 24000000 0 0 mipi_dphy_cg 1 1 0 24000000 0 0 mipi_dphy_pre_div 1 1 0 24000000 0 0 mipi_dphy_post_div 1 1 0 24000000 0 0 mipi_dphy_root_clk 1 1 0 24000000 0 0 Fixes: 8f6d8094 ("ARM: imx: add imx7d clk tree support") Acked-by:Dong Aisheng <Aisheng.dong@nxp.com> Signed-off-by:
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Lei YU authored
Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by:
Lei YU <mine260309@gmail.com> Reviewed-by:
Joel Stanley <joel@jms.id.au> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Anson Huang authored
ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus clock. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Anson Huang authored
Correct enet clock gates as below: CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK Just rename unused IMX7D_ENETx_REF_ROOT_CLK for IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by:
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Anson Huang authored
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly, there is no clock gate after it, rename it to IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change. Signed-off-by:
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Anson Huang authored
IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in CCM_CDHIPR register of Reference Manual CCM chapter is axi_podf_busy, correct its clock type. Signed-off-by:
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Anson Huang authored
Disable those unnecessary clocks during kernel boot up to save power, those modules clock should be managed by modules driver in runtime. Signed-off-by:
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Rajendra Nayak authored
There's no bus infrastructure today to handle all the mmagic bus clocks and GDSCs needed by all the multimedia blocks in msm8996, like mdss, video, camera and gpu. Mark all these clocks with a CLK_IS_CRITICAL and GDSCs with a ALWAYS_ON flag for now so they are left always enabled. This patch should be reverted at some point when we do have a bus driver to manage these clocks and GDSCs. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Rajendra Nayak authored
We have atleast some instances of ALWAYS_ON gdscs, which need to be turned ON *before* some clocks within the gdsc domain marked with a CLK_IS_CRITICAL can be turned ON. To facilitate this sequence, register the GDCSs (and hence handle the ALWAYS_ON gdscs) before we register clocks (and handle the clocks marked as CLK_IS_CRITICAL) Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Rajendra Nayak authored
Some GDSCs might have software control to turn them off, but we might want to keep them enabled always, in some cases because of lack of support in kernel to handle a graceful turning off/on of such GDSCs. Most common instances would be the GDCSs which power up the noc/bus fabrics, which need bus drivers to handle them and atleast support for which is missing on all qcom SoCs. Signed-off-by:
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Jisheng Zhang authored
Use the appropriate SPDX license identifier and drop the previous license text. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'tegra-for-4.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra Pull Tegra clk driver updates from Thierry Reding: - proper implementation of the CDEV1/2 clocks on Tegra20 * tag 'tegra-for-4.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers
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Stephen Boyd authored
Merge tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull rockchip clk driver updates from Heiko Stuebner: Conversion to match_string helper of open-coded string comparison and removal of the initial devicetree-based gate-clocks, which were deprecated since 2014. * tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Maxime Ripard: Not a lot of changes for this release, but two quite important features were added: the H6 PRCM clock support, and the needed changes to the R40 clock driver to allow for the EMAC to operate. * tag 'sunxi-clk-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU
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- 23 May, 2018 1 commit
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Heiko Stuebner authored
Initially we tried modeling clocks via the devicetree before switching to clocks declared in the clock drivers and only exporting specific ids to the devicetree. As the old code was in the kernel for 1-2 releases when the new mode of operation was added we kept it for backwards compatibility. That deprecation notice is in the binding since july 2014, so nearly 4 years now and I think it's time to drop the old cruft. Especially as at the time using the mainline kernel on Rockchip devices was not really possible, except for experiments on the really old socs of the rk3066 + rk3188 line, so there shouldn't be any devicetrees still around that rely on that code. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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- 22 May, 2018 1 commit
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Yisheng Xie authored
match_string() returns the index of an array for a matching string, which can be used intead of open coded variant. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by:
Yisheng Xie <xieyisheng1@huawei.com> Signed-off-by:
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- 18 May, 2018 3 commits
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Dmitry Osipenko authored
CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Dmitry Osipenko authored
Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by:
Marcel Ziswiler <marcel@ziswiler.com> Tested-by:
Marc Dietrich <marvin24@gmx.de> Acked-by:
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Dmitry Osipenko authored
CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by:
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- 17 May, 2018 2 commits
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Icenowy Zheng authored
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
Chen-Yu Tsai <wens@csie.org>
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Icenowy Zheng authored
As we need to register a regmap on the R40 CCU, there needs to be a device structure bound to the CCU device node. Rewrite the R40 CCU driver initial code to make it a proper platform driver, thus we will have a platform device bound to it. Signed-off-by:
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- 15 May, 2018 1 commit
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Michael Trimarchi authored
osc->cko2_sel->cko2_podf->clk_cko2->clk_cko Example of usage to provide clock to the sgtl5000 codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6UL_CLK_OSC>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_CKO>; assigned-clocks = <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>, <&clks IMX6UL_CLK_CKO>; assigned-clock-parents = <&clks IMX6UL_CLK_OSC>, <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>; clock-names = "mclk"; wlf,shared-lrclk; Signed-off-by:Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by:
Michael Trimarchi <michael@amarulasolutions.com> Tested-by:
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