- 18 Aug, 2013 14 commits
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David Herrmann authored
These two helpers are unused. Remove them. They rely on gem_obj->driver_private, which is set to NULL during setup. As this field isn't used by the driver, anymore, we can remove this assignment as well. Signed-off-by:
David Herrmann <dh.herrmann@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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David Herrmann authored
gem_bo->driver_private is never read by cirrus nor DRM core. No need to set it. Besides, drm core clears it during setup, anyway. Signed-off-by:
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David Herrmann authored
gem_bo->driver_private is never read by mgag200 nor DRM core. No need to set it. Besides, drm core clears it during setup, anyway. Signed-off-by:
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David Herrmann authored
gem_bo->driver_private is never read by ast nor DRM core. No need to set it. Besides, drm core clears it during setup, anyway. Signed-off-by:
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Dave Airlie authored
Merge the rcar stable branch that is being shared with the arm-soc tree. Signed-off-by: -
Darren Etheridge authored
Add a fixup function that will flip the hsync priority and add a hskew value that is used to shift the tda998x to the right by a variable number of pixels depending on the mode. This works around an issue with the sync timings that tilcdc is outputing. Signed-off-by:
Darren Etheridge <detheridge@ti.com> Tested-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by:
Russell King <rmk_kernel@arm.linux.org.uk> Signed-off-by:
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Sebastian Hesselbarth authored
Some LCD controller cannot provide valid VESA style sync, i.e. coincident HS/VS edges. First, this patch adds hskew passed from the adjusted_mode to reference pixel calculation to allow those controllers to add an offset relative to the expected reference pixel. Signed-off-by:
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Sebastian Hesselbarth authored
This fixes the wrong sync generation and sync calculation of TDA998x for HS/VS-based sync detection. Signed-off-by:
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Russell King authored
This patch adds tda998x specific parameters to allow it to be configured for different boards using it. Also, this implements rudimentary audio support for S/PDIF attached controllers. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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Russell King authored
The video-input-port (VIP) is highly configurable. This prepares current driver to allow to configure VIP configuration, as some boards connect lcd controller and TDA998x "pin-swapped" and depend on VIP to swap the pins by register configuration. Signed-off-by:
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Russell King authored
The npix/nline registers are supposed to be programmed with the total number of pixels/lines, not the displayed pixels/lines, and not minus one either. Signed-off-by:
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Russell King authored
When switching between various drivers for this device, it's possible that some critical registers are left containing values which affect the device operation. One such case encountered is the VIP output mux register. This defaults to 0x24 on powerup, but other drivers may set this to 0x12. This results in incorrect colours. Fix this by ensuring that the register is always set to the power on default setting. Signed-off-by:
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Russell King authored
TDA19988 devices need their RAM enabled in order to read EDID information. Add support for this. Signed-off-by:
Rob Clark <robdclark@gmail.com> Tested-by:
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Geert Uytterhoeven authored
If NO_DMA=y: drivers/built-in.o: In function `__drm_pci_free': drivers/gpu/drm/drm_pci.c:112: undefined reference to `dma_free_coherent' drivers/built-in.o: In function `drm_pci_alloc': drivers/gpu/drm/drm_pci.c:72: undefined reference to `dma_alloc_coherent' drivers/built-in.o: In function `drm_gem_unmap_dma_buf': drivers/gpu/drm/drm_prime.c:87: undefined reference to `dma_unmap_sg' drivers/built-in.o: In function `drm_gem_map_dma_buf': drivers/gpu/drm/drm_prime.c:78: undefined reference to `dma_map_sg' Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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- 09 Aug, 2013 24 commits
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git://linuxtv.org/pinchartl/fbdevDave Airlie authored
Create topic branch for rcar for shmobile tree to pull as well, arm-soc should probably merge after drm merges if possible. Signed-off-by:
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Laurent Pinchart authored
Use the FB CMA helpers to implement FBDEV emulation support. The VGA connector status must be reported as connector_status_connected instead of connector_status_unknown to be usable by the emulation layer. Signed-off-by:Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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Laurent Pinchart authored
The R8A7790 includes two internal LVDS encoders. Support them in the DU driver. Signed-off-by: -
Laurent Pinchart authored
The R8A7790 DU variant has a single RGB output called DPAD0 that can be fed with the output of DU0, DU1 or DU2. Making the routing configurable. Signed-off-by: -
Laurent Pinchart authored
Split the output routing specification between SoC-internal data, specified in the rcar_du_device_info structure, and board data, passed through platform data. The DU has 5 possible outputs (DPAD0/1, LVDS0/1, TCON). SoC-internal output routing data specify which output are valid, which CRTCs can be connected to the valid outputs, and the type of in-SoC encoder for the output. Platform data then specifies external encoders and the output they are connected to. Signed-off-by: -
Laurent Pinchart authored
The R8A7790 DU has a new extended function control register. Support it. Signed-off-by: -
Laurent Pinchart authored
The R8A7790 DU has 3 CRTCs, split in two groups. Support them. Signed-off-by: -
Laurent Pinchart authored
The R8A7790 DU seems to require a 128 bytes pitch alignment, even though the documentation only mentions a 16 pixels alignement as for the R8A7779 DU. Make this configurable through a device flag. Signed-off-by: -
Laurent Pinchart authored
The DU revision in the R8A7790 SoC uses one IRQ and clock per CRTC. Add a corresponding entry in the module platform ID table. Signed-off-by: -
Laurent Pinchart authored
Output routing is configured in group registers, move the corresponding code from rcar_du_crtc.c to rcar_du_group.c. Signed-off-by: -
Laurent Pinchart authored
Channels are accessed through a global channel memory offset, there's no need to define register addresses for the second channel. Signed-off-by: -
Laurent Pinchart authored
The rcar_du_device structure contains a field that stores the number of CRTCs, use it instead of the CRTCs array size. This prepares the driver to support a variable number of CRTCs. Signed-off-by: -
Laurent Pinchart authored
The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending unit, timings generator, ...) and device-global resources (start/stop control, planes, ...) shared between the two CRTCs. The R8A7790 introduced a third CRTC with its own set of global resources This would be modeled as two separate DU device instances if it wasn't for a handful or resources that are shared between the three CRTCs (mostly related to input and output routing). For this reason the R8A7790 DU must be modeled as a single device with three CRTCs, two sets of "semi-global" resources, and a few device-global resources. Introduce a new rcar_du_group driver-specific object, without any real counterpart in the DU documentation, that models those semi-global resources. Signed-off-by: -
Laurent Pinchart authored
The functions initialize or register all planes, rename them accordingly. Signed-off-by: -
Laurent Pinchart authored
Move the plane-related fields of struct rcar_du_device to their own structure. Signed-off-by: -
Laurent Pinchart authored
The struct rcar_du_encoder_data encoder::field describes the encoder type, and the rcar_du_encoder_lvds_data and rcar_du_encoder_vga_data structures describe connector properties. Rename them accordingly. Signed-off-by: -
Laurent Pinchart authored
Create a single rcar_du_encoder structure that implements a KMS encoder. The current implementation is straightforward and only configures CRTC output routing. Signed-off-by: -
Laurent Pinchart authored
This prepares for the encoders rework. Signed-off-by: -
Laurent Pinchart authored
This prepares for the encoders rework. Signed-off-by: -
Laurent Pinchart authored
The R8A7790 DU documentation contains further information regarding the plane Y source coordinate. Update the comment accordingly. Signed-off-by: -
Laurent Pinchart authored
Some of the DU revisions use one clock and IRQ per CRTC instead of one clock and IRQ per device. Retrieve the correct clock and register the correct IRQ for each CRTC. Signed-off-by: -
Laurent Pinchart authored
The platform device id driver data field points to a device information structure that only contains a (currently empty) features field for now. Support for additional model-dependent features will be added later. Only the R8A7779 variant is currently supported. Signed-off-by: -
Laurent Pinchart authored
Replace the devm_request_mem_region() and devm_ioremap_nocache() calls with devm_ioremap_resource(). Signed-off-by: -
Laurent Pinchart authored
Several alpha plane register definitions are missing, add them. Signed-off-by:
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- 08 Aug, 2013 1 commit
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David Herrmann authored
We currently rely on gcc dead-code elimination so the drm_agp_* helpers are not called if drm_core_has_AGP() is false. That's ugly as hell so provide "static inline" dummies for the case that AGP is disabled. Fixes a build-regression introduced by: commit 28ec711c Author: David Herrmann <dh.herrmann@gmail.com> Date: Sat Jul 27 16:37:00 2013 +0200 drm/agp: move AGP cleanup paths to drm_agpsupport.c v2: switch #ifdef -> #if (spotted by Stephen) Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Daniel Vetter <daniel@ffwll.ch> Tested-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Dave Airlie <airlied@gmail.com>
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- 07 Aug, 2013 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-2013-07-26-fixed' of git://people.freedesktop.org/~danvet/drm-intel into drm-next Neat that QA (and Ben) keeps on humming along while I'm on vacation, so you already get the next feature pull request: - proper eLLC support for HSW from Ben - more interrupt refactoring - add w/a tags where we implement them already (Damien) - hangcheck fixes (Chris) + hangcheck stats (Mika) - flesh out the new vm structs for ppgtt and ggtt (Ben) - PSR for Haswell, still disabled by default (Rodrigo et al.) - pc8+ refclock sequence code from Paulo - more interrupt refactoring from Paulo, unifying ilk/snb with the ivb/hsw interrupt code - full solution for the Haswell concurrent reg access issues (Chris) - fix racy object accounting, used by some new leak tests - fix sync polarity settings on ch7xxx dvo encoder - random bits&pieces, little fixes and better debug output all over [airlied: fix conflict with drm_mm cleanups] * tag 'drm-intel-next-2013-07-26-fixed' of git://people.freedesktop.org/~danvet/drm-intel: (289 commits) drm/i915: Do not dereference NULL crtc or fb until after checking drm/i915: fix pnv display core clock readout out drm/i915: Replace open-coded offset_in_page() drm/i915: Retry DP aux_ch communications with a different clock after failure drm/i915: Add messages useful for HPD storm detection debugging (v2) drm/i915: dvo_ch7xxx: fix vsync polarity setting drm/i915: fix the racy object accounting drm/i915: Convert the register access tracepoint to be conditional drm/i915: Squash gen lookup through multiple indirections inside GT access drm/i915: Use the common register access functions for NOTRACE variants drm/i915: Use a private interface for register access within GT drm/i915: Colocate all GT access routines in the same file drm/i915: fix reference counting in i915_gem_create drm/i915: Use Graphics Base of Stolen Memory on all gen3+ drm/i915: disable stolen mem for OVERLAY_NEEDS_PHYSICAL drm/i915: add functions to disable and restore LCPLL drm/i915: disable CLKOUT_DP when it's not needed drm/i915: extend lpt_enable_clkout_dp drm/i915: fix up error cleanup in i915_gem_object_bind_to_gtt drm/i915: Add some debug breadcrumbs to connector detection ...
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