- 29 May, 2020 11 commits
-
-
Vladimir Kondratiev authored
Accordingly to Cadence documentation, PHY write procedure is: 1. Software sets the PHY Register Address (HRS04[5:0]) and the PHY Write Data (HRS04[15:8]) fields. 2. Software sets the PHY Write Transaction Request (HRS04[24]) field to 1. 3. Software waits as the PHY Write Transaction Acknowledge (HRS04[26]) field is equal to 0. 4. Hardware performs the write transaction to PHY register where HRS04[15:8] is a data written to register under HRS04[5:0] address. 5. Hardware sets the PHY Transaction Acknowledge (HRS04[26]) to 1 when transaction is completed. 6. Software clears the PHY Write Transaction Request (HRS04[24]) to 1 after noticing that the PHY Write Transaction Acknowledge (HRS04[26]) field is equal to 1. 7. Software waits for the PHY Acknowledge Register (HRS04[26]) field is equal to 0. Add missing steps 3 and 7. Lack of these steps causes integrity errors detested by hardware. Signed-off-by:
Vladimir Kondratiev <vladimir.kondratiev@intel.com> Link: https://lore.kernel.org/r/20200525074053.7309-1-vladimir.kondratiev@intel.comSigned-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
-
Pali Rohár authored
Fix ordering of SDIO IDs to conform to the comment above, which says vendor first, device next. Signed-off-by:
Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20200522144412.19712-12-pali@kernel.orgSigned-off-by:
-
Pali Rohár authored
All macro names for SDIO device IDs are prefixed by vendor name to which device ID belongs. So for consistency add Broadcom string vendor prefix to all Cypress macro names as they belong to SDIO Broadcom vendor ID. Change also Cypress 43012 value from decimal do hexadecimal notation to be consistent with all other values. Signed-off-by:
-
Pali Rohár authored
Define appropriate macro names for consistency with other macros. Signed-off-by:
-
Pali Rohár authored
Also replace generic MANUFACTURER macros by proper SDIO IDs macros. Checks for device IDs are slightly modified to use SDIO device IDs. This allows removal of all custom MANUFACTURER macros from ath10k. Signed-off-by:
-
Pali Rohár authored
Also replace generic MANUFACTURER macros by proper SDIO IDs macros. Check for "AR6003 or later" is slightly modified to use SDIO device IDs. This allows removal of all custom MANUFACTURER macros from ath6kl. Signed-off-by:
Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200522144412.19712-8-pali@kernel.orgSigned-off-by:
-
Pali Rohár authored
Define appropriate macro names for consistency with other Siano macros. Signed-off-by:
-
Pali Rohár authored
Define appropriate macro names for consistency with other macros. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20200522144412.19712-6-pali@kernel.orgSigned-off-by:
Ganapathi Bhat <ganapathi.bhat@nxp.com>
-
Pali Rohár authored
Define appropriate macro names for consistency with other Marvell macros. Signed-off-by:
-
Pali Rohár authored
Add _WLAN suffix to macro names for consistency with other Marvell macros. These IDs represents wlan function of combo bt/wlan cards. Other functions of these cards have different IDs. Signed-off-by:
-
Pali Rohár authored
Add underscore as separator in Marvell 8688 macro names for better readability and consistency. Signed-off-by:
-
- 28 May, 2020 29 commits
-
-
Pali Rohár authored
Marvell SDIO device ID 0x9134 is used in SDIO Common CIS (Card Information Structure) and not in SDIO wlan function (with ID 1). SDIO Common CIS is accessed by function ID 0. So change this misleading macro name to SDIO_DEVICE_ID_MARVELL_8887_F0 as it does not refer to wlan function. It refers to function 0. Wlan module on this SDIO card is available at function ID 1 and is identified by different SDIO device ID 0x9135. Kernel quirks for SDIO devices are matched against device ID from SDIO Common CIS. Therefore device ID used in quirk is correct, just has misleading name. Signed-off-by:
-
Ulf Hansson authored
-
Angelo Dureghello authored
Moving specific m5441x clk-related code in more appropriate location, since breaking compilation for other targets. Signed-off-by:
Angelo Dureghello <angelo.dureghello@timesys.com> Link: https://lore.kernel.org/r/20200525102324.2723438-1-angelo.dureghello@timesys.comSigned-off-by:
-
Yangbo Lu authored
The eSDHC HS400 timing requires many specific registers setting, unlike other speed modes which need to set only host controller 2 register. When driver needs to downgrade HS400 mode to other speed mode, the controller have to exit HS400 timing properly first. This patch is to support the procedure of HS400 exiting at the beginning of esdhc_set_uhs_signaling. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200522031256.856-1-yangbo.lu@nxp.comSigned-off-by:
-
Sarthak Garg authored
Implement dump_vendor_registers host operation to print the vendor specific registers in addition to standard SDHC register during error conditions. Signed-off-by:
Sahitya Tummala <stummala@codeaurora.org> Signed-off-by:
Sarthak Garg <sartgarg@codeaurora.org> Acked-by:
-
Sarthak Garg authored
Introduce new sdhci ops to dump vendor specific registers in the sdhci_dumpregs during error. Signed-off-by:
-
Sarthak Garg authored
Certain platforms require different settings in the SDCC_HC_REG_DLL_CONFIG register. This setting can change from platform to platform. So the driver should check whether a particular platform require a different setting by reading the DT file and use it. Also use msm_cm_dll_set_freq only when DLL not supplied. Signed-off-by:
Bao D. Nguyen <nguyenb@codeaurora.org> Signed-off-by:
-
Sarthak Garg authored
Certain platforms require different settings in the SDCC_HC_REG_DDR_CONFIG register. This setting can change from platform to platform. So the driver should check whether a particular platform require a different setting by reading the device tree file and use it. Signed-off-by:
-
Sarthak Garg authored
Update dll_config_3 as per the host clock frequency as specified in the DLL Hardware Reference Guide. Signed-off-by:
-
Veerabhadrarao Badiganti authored
With SDCC v5.1.0, additional setting needed for enabling DLL output. The dll-user-control register need to be configured during dll initialization for getting proper dll output. Without this configuration, we don't get the DLL lock status properly. Also update the DLL register settings according to the SDCC Hardware Programming Guide. Signed-off-by:
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by:
-
Sarthak Garg authored
Add information regarding DLL register properties for getting board specific configurations. These DLL register settings may vary from board to board. Signed-off-by:
-
Sarthak Garg authored
Add new compatible string for sm8250 target. Signed-off-by:
-
Sowjanya Komatineni authored
When auto calibration timeouts, calibration is disabled and fail-safe drive strength values are programmed based on the signal voltage. Different fail-safe drive strength values based on voltage are applicable only for SoCs supporting 3V3 and 1V8 pad controls. So, this patch avoids reading these properties from the device tree for SoCs not using pad controls and the warning of missing properties will not show up on these SoC platforms. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Tested-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Thierry Reding <treding@nvidia.com> Acked-by:
-
Wolfram Sang authored
The SDHI driver en-/disabled its main clock on its own, e.g. during probe() and remove(). Now, we leave all handling to RPM. clk_summary before: sd0 1 1 0 12480000 0 0 50000 sdif0 2 2 0 12480000 0 0 50000 clk_summary after: sd0 1 1 0 12480000 0 0 50000 sdif0 1 1 0 12480000 0 0 50000 Reported-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20200519164251.5430-1-wsa+renesas@sang-engineering.comSigned-off-by:
-
Ulf Hansson authored
If the tmio device is attached to a genpd (PM domain), that genpd may have ->start|stop() callback assigned to it. To make sure the device is accessible during ->probe(), genpd's ->start() callback must be invoked, which is currently managed by tmio_mmc_host_probe(). However, it's likely that may be too late for some cases, as registers may be read and written way before that point. To fix the behaviour, let's move the call to dev_pm_domain_start() from tmio_mmc_host_probe() into those clients that needs it. From discussions at linux-mmc mailing list, it turned out that it should be sufficient to do this for the SDHI renesas variants, hence the call is move to renesas_sdhi_probe(). Signed-off-by:
-
Ulf Hansson authored
Before calling tmio_mmc_host_probe(), the caller is required to enable clocks for its device, as to make it accessible when reading/writing registers during probe. Therefore, the responsibility to disable these clocks, in the error path of ->probe() and during ->remove(), is better managed outside tmio_mmc_host_remove(). As a matter of fact, callers of tmio_mmc_host_remove() already expects this to be the behaviour. However, there's a problem with tmio_mmc_host_remove() when the Kconfig option, CONFIG_PM, is set. More precisely, tmio_mmc_host_remove() may then disable the clock via runtime PM, which leads to clock enable/disable imbalance problems, when the caller of tmio_mmc_host_remove() also tries to disable the same clocks. To solve the problem, let's make sure tmio_mmc_host_remove() leaves the device with clocks enabled, but also make sure to disable the IRQs, as we normally do at ->runtime_suspend(). Reported-by:
-
Angelo Dureghello authored
Since actively working on Freescale ColdFire M5441X, adding myself as a maintainer of this driver. Signed-off-by:
-
Angelo Dureghello authored
This driver has been developed as a separate module starting from the similar sdhci-esdhc-imx.c. Reasons for a separate sdchi-esdhc-mcf driver: - m68K architecture does not support devicetrees, so modifying sdhci-of-esdhc.c that is devicetree-related adding platform data seems not appropriate, - clock-related part, has to be implemented specifically for mcf5441x family (see esdhc_mcf_pltfm_set_clock()), - this is a big endian cpu accessing a big endian controller, but about sdma, this controller does not support hw swap, which needs to be handled with specific code, - some other minor differences but mainly to avoid risks on tweaking inside largely used imx driver. Adding just a small size ColdFire-specific driver, with benefits in a further less risky maintenance. Signed-off-by:
-
Angelo Dureghello authored
Some controller as the ColdFire eshdc may require an endianness byte swap, because DMA read endianness is not configurable. Facilitate using the bounce buffer for this by adding ->copy_to_bounce_buffer(). Signed-off-by:
-
Angelo Dureghello authored
Add support for sdhci-edshc mmc controller. Signed-off-by:
Greg Ungerer <gerg@linux-m68k.org> Link: https://lore.kernel.org/r/20200518191742.1251440-1-angelo.dureghello@timesys.comSigned-off-by:
-
Lad Prabhakar authored
Document SDHI controller for RZ/G1H (R8A7742) SoC, which is compatible with R-Car Gen2 SoC family. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by:
-
Martin Blumenstingl authored
Kbuild test robot reports the following warning in lines 56 and 87 of drivers/mmc/host/meson-mx-sdhc-clkc.c: Using plain integer as NULL pointer Drop the integer value from the struct initialization to fix that warning. This will still ensure that the compiler will zero out the struct so it's in a well-defined state. Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200517222907.1277787-2-martin.blumenstingl@googlemail.comSigned-off-by:
-
Martin Blumenstingl authored
For Meson8 and Meson8b SoCs the vendor driver follows the following pattern: - for eMMC and SD cards in .set_pdma it sets: pdma->rxfifo_manual_flush = 1; - for SDIO cards in .set_pdma it sets: pdma->rxfifo_manual_flush = 0; - before syncing the DMA read buffer is sets: pdma->rxfifo_manual_flush |= 0x02; Set the second bit of MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH without clearing the first bit before syncing the DMA read buffer. This fixes a problem where Meson8 and Meson8b SoCs would read random garbage from SD cards. It is not clear why it worked for eMMC cards. This manifested in the following errors when plugging in an SD card: unrecognised SCR structure version <random number> Cc: Thomas Graichen <thomas.graichen@gmail.com> Signed-off-by:
-
Haibo Chen authored
i.MX6SLL support MMC up to V5.0, which means support HS400 mode. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
-
Martin Blumenstingl authored
For an x86_64 allmodconfig build Stephen reports that building meson-mx-sdhc-clkc.o warns that MODULE_LICENSE is missing and when linking meson_mx_sdhc_register_clkc cannot be found. Compile the MMC controller driver together with the build-in clock controller driver into one module rather than using two separate modules to fix these issues. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
-
Jisheng Zhang authored
Add dwcmshc specific system-level suspend and resume support. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200515141926.52e088fe@xhacker.debianSigned-off-by:
-
Jisheng Zhang authored
We need a different set_uhs_signaling implementation for MMC_TIMING_MMC_HS and MMC_TIMING_MMC_HS400. Signed-off-by:
-
Martin Blumenstingl authored
The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC card interface with 1/4/8-bit bus width. It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock). The public S805 datasheet [0] contains a short documentation about the registers. Unfortunately it does not describe how to use the registers to make the hardware work. Thus this driver is based on reading (and understanding) the Amlogic 3.10 GPL kernel code. Some hardware details are not easy to see. Jianxin Pan was kind enough to answer my questions: The hardware has built-in busy timeout support. The maximum timeout is 30 seconds. This is only documented in Amlogic's internal documentation. The controller only works with very specific clock configurations. The details are not part of the public datasheet. In my own words the supported configurations are: - 399.812kHz: clkin = 850MHz div = 2126 sd_rx_phase = 63 - 1MHz: clkin = 850MHz div = 850 sd_rx_phase = 55 - 5.986MHz: clkin = 850MHz div = 142 sd_rx_phase = 24 - 25MHz: clkin = 850MHz div = 34 sd_rx_phase = 15 - 47.222MHz: clkin = 850MHz div = 18 sd_rx_phase = 11/15 (SDR50/HS) - 53.125MHz: clkin = 850MHz div = 16 sd_rx_phase = (tuning) - 70.833MHz: clkin = 850MHz div = 12 sd_rx_phase = (tuning) - 85MHz: clkin = 850MHz div = 10 sd_rx_phase = (tuning) - 94.44MHz: clkin = 850MHz div = 9 sd_rx_phase = (tuning) - 106.25MHz: clkin = 850MHz div = 8 sd_rx_phase = (tuning) - 127.5MHz: clkin = 1275MHz div = 10 sd_rx_phase = (tuning) - 141.667MHz: clkin = 850MHz div = 6 sd_rx_phase = (tuning) - 159.375MHz: clkin = 1275MHz div = 8 sd_rx_phase = (tuning) - 212.5MHz: clkin = 1275MHz div = 6 sd_rx_phase = (tuning) - (sd_tx_phase is always 1, 94.44MHz is not listed in the datasheet but this is what the 3.10 BSP kernel on Odroid-C1 actually uses) NOTE: CMD23 support is disabled for now because it results in command timeouts and thus decreases read performance. Tested-by:
Wei Wang <lnykww@gmail.com> Tested-by:
Xin Yin <yinxin_1989@aliyun.com> Reviewed-by:
Anand Moon <linux.amoon@gmail.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200512204147.504087-3-martin.blumenstingl@googlemail.comSigned-off-by:
-
Martin Blumenstingl authored
This documents the devicetree bindings for the SDHC MMC host controller found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including HS200 mode (up to 100MHz clock). It embeds an internal clock controller which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is fed by four external input clocks (clkin[0-3]). "pclk" is the module register clock, it has to be enabled to access the registers. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200512204147.504087-2-martin.blumenstingl@googlemail.comSigned-off-by:
-
