- 22 Nov, 2019 7 commits
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Dennis Li authored
Get mmhub error counter by accessing EDC_CNT registers. v2: Add mmhub_v9_4_ prefix for local static variable and function Signed-off-by:
Dennis Li <dennis.li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dennis Li authored
Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by:
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Dennis Li authored
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table. Signed-off-by:
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Xiaojie Yuan authored
Fixes: 0bb419c7 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings (v2)") Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
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Xiaojie Yuan authored
50us is not enough to wait for cp ready after gpu reset on some navi asics. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Alex Sierra authored
Only for the debugger use case. [why] Avoid endless translation retries, after an invalid address access has been issued to the GPU. Instead, the trap handler is forced to enter by generating a no-retry-fault. A s_trap instruction is inserted in the debugger case to let the wave to enter trap handler to save context. [how] Intentionally using an invalid flag combination (F and P set at the same time) to trigger a no-retry-fault, after a retry-fault happens. This is only valid under compute context. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Sierra authored
Flag added to indicate if the amdgpu vm context is used for compute or graphics. Signed-off-by:
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- 19 Nov, 2019 33 commits
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Alex Deucher authored
BACO - Bus Active, Chip Off Everything is in place now. Not enabled by default yet. You still have to specify runpm=1. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Originally we only supported runtime pm on PX/HG laptops so vga_switcheroo and runtime pm are sort of entangled. Attempt to logically separate them. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We originally only supported runtime pm on PX/HG laptops so most of the runtime pm code looks for this. Add a new flag to check for runtime pm enablement and use this rather than checking for PX/HG. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off This adds the necessary support to the runtime suspend and resume functions to handle boards that support baco. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Will be used for runtime pm. Entry will enter the BACO state (chip off). Exit will exit the BACO state (chip on). Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We will take slightly different paths for boco and baco. v2: fold together two consecutive if clauses Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off To better match what we are checking for and to align with amdgpu_device_supports_baco. BOCO is used on PowerXpress/Hybrid Graphics systems and BACO is used on desktop dGPU boards. v2: fix typo in documentation Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off To check if a device supports BACO or not. This will be used in determining when to enable runtime pm. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Not supported. Reviewed-by:
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Alex Deucher authored
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. v2: drop unrelated struct cleanup Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
BACO - Bus Active, Chip Off Used to check whether the device supports BACO. This will be used to enable runtime pm on devices which support BACO. Reviewed-by:
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changzhu authored
To get the value of gpu_busy_percent, it needs to realize get_current_activity_percent and get_metrics_table. The framework of renoir smu is different from old ones like raven. It needs to realize get_current_activity_percent and get_metrics_table in renoir_ppt.c like navi10. v2: remove unused variable (Alex) Signed-off-by:
changzhu <Changfeng.Zhu@amd.com> Reviewed-by:
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Hawking Zhang authored
ras_controller_irq and athub_err_event_irq are only registered when PCIE_BIF ras is marked as supported. as the result, the driver also just need pull the int status in such case. Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Hawking Zhang authored
Drop all the IP specific cmd_submit callback function and use the common helper instead Signed-off-by:
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Hawking Zhang authored
Except for ring wptr update, the psp ring cmd submission function shouldn't be IP specific one. Create a common helper function to be shared for all the ASICs. Signed-off-by:
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Hawking Zhang authored
The ring write pointer regsiter update is the only part that is IP specific ones in psp_cmd_submit function. Add two callbacks for wptr read/write so that we unify the psp_cmd_submit function for all the ASICs. Signed-off-by:
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Evan Quan authored
This can fix the compile errors below: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration] struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion] drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’ if (!ras || !ras->supported) { Signed-off-by: -
Evan Quan authored
Enable baco reset support on Arcturus. Signed-off-by:
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Evan Quan authored
Added bif doorbell interrupt setting and applied different settings for BACO reset for RAS recovery. Signed-off-by:
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Alex Deucher authored
This reverts commit 1c425915. S/G display is not stable with the IOMMU enabled on some platforms. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523Acked-by:
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Alex Deucher authored
There are still combinations of sbios and firmware that are not stable. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204689Acked-by:
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Alex Deucher authored
5.4 and newer works fine with navi14. Reviewed-by:
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Alex Deucher authored
When gfxoff is enabled, accessing gfx registers via MMIO can lead to a hang. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497Acked-by:
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Alex Deucher authored
So that the setting reflects what the hw supports. This will be used in a subsequent patch so needs to be correct. v2: squash in fix from Colin Ian King Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497Reviewed-by:
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Chen Wandun authored
return errno code to caller when error occur, and meanwhile remove gcc '-Wunused-but-set-variable' warning. drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c: In function vegam_populate_smc_boot_level: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1364:6: warning: variable result set but not used [-Wunused-but-set-variable] Reviewed-by:
Chen Wandun <chenwandun@huawei.com> Signed-off-by:
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zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:64:13-31: WARNING: dma_alloc_coherent use in ih -> ring already zeroes out memory, so memset is not needed Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
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Sam Bobroff authored
The INTERRUPT_CNTL2 register expects a valid DMA address, but is currently set with a GPU MC address. This can cause problems on systems that detect the resulting DMA read from an invalid address (found on a Power8 guest). Instead, use the DMA address of the dummy page because it will always be safe. Fixes: 27ae1064 ("drm/amdgpu: add interupt handler implementation for si v3") Signed-off-by:
Sam Bobroff <sbobroff@linux.ibm.com> Signed-off-by:
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Sam Bobroff authored
The INTERRUPT_CNTL2 register expects a valid DMA address, but is currently set with a GPU MC address. This can cause problems on systems that detect the resulting DMA read from an invalid address (found on a Power8 guest). Instead, use the DMA address of the dummy page because it will always be safe. Fixes: d8f60cfc ("drm/radeon/kms: Add support for interrupts on r6xx/r7xx chips (v3)") Fixes: 25a857fb ("drm/radeon/kms: add support for interrupts on SI") Fixes: a59781bb ("drm/radeon: add support for interrupts on CIK (v5)") Signed-off-by:
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zhengbin authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/radeon/radeon_legacy_tv.c: In function radeon_legacy_tv_mode_set: drivers/gpu/drm/radeon/radeon_legacy_tv.c:538:24: warning: variable tv_pll_cntl1 set but not used [-Wunused-but-set-variable] It is introduced by commit 4ce001ab ("drm/radeon/kms: add initial radeon tv-out support."), but never used, so remove it. Reported-by:
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