- 17 Aug, 2017 4 commits
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Simon Horman authored
Use newly added R-Car SATA Gen2 fallback compat string in the DT of the r8a7790 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before the fallback compat string is considered. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - clock-latency = 300 us Approximate worst-case latency to do clock transition for every OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in RZ/G1 Soc. Note:This also fixes the below errors seen on kernel logs [ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19) [ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2 Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Signed-off-by:
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Biju Das authored
Add DT nodes for the Advanced Power Management Unit (APMU) and the second CPU core. Use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by:
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Hans Verkuil authored
The adv7511 on the Koelsch board has a 12 MHz fixed clock for the CEC block. Specify this in the dts to enable CEC support. Signed-off-by:
Hans Verkuil <hans.verkuil@cisco.com> Reviewed-by:
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- 15 Aug, 2017 3 commits
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Sergei Shtylyov authored
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's device tree. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add the (previously omitted) SCIF2 pin data to the SK-RZG1E board's device tree. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A7745 part of the PFC device node. Signed-off-by:
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- 14 Aug, 2017 1 commit
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Biju Das authored
Add the I2C[0-5] devices to the r8a7743 device tree. Signed-off-by:
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- 31 Jul, 2017 10 commits
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Geert Uytterhoeven authored
Fixes: 4658c4b789d8e2ae ("ARM: dts: iwg20m: Add MMCIF0 support") Signed-off-by:Chris Paterson <chris.paterson2@renesas.com> Signed-off-by:
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Chris Brandt authored
Add pin configuration for LED0 which is connected to a GPIO. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Signed-off-by:
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Chris Brandt authored
Add pin configuration for SDHI ch1. Signed-off-by:
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Chris Brandt authored
Add pin configuration for Ethernet. Signed-off-by:
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Chris Brandt authored
Add pin configuration for SCIF2 serial console interface. Signed-off-by:
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Jacopo Mondi authored
Add pin configuration subnode for ETHER ethernet controller. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
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Jacopo Mondi authored
Add device nodes for user leds on Genmai board. Signed-off-by:
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Jacopo Mondi authored
Add pin configuration subnode for RIIC2 interface. Signed-off-by:
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Jacopo Mondi authored
Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by:
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Jacopo Mondi authored
Add pin controller node with 12 gpio controller sub-nodes to r7s72100 dtsi. Signed-off-by:
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- 27 Jul, 2017 22 commits
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Chris Paterson authored
Define the iwg20m board dependent part of the MMCIF0 device node. Signed-off-by:
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Simon Horman authored
Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7794 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7794 and the fallback binding for R-Car Gen 2 Signed-off-by:
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Simon Horman authored
Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7791 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7791 and the fallback binding for R-Car Gen 2 Signed-off-by:
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Simon Horman authored
Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7790 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7790 and the fallback binding for R-Car Gen 2 Signed-off-by:
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Chris Paterson authored
Add the MMCIF0 device to the r8a7743 device tree. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by:
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Geert Uytterhoeven authored
R-Car E2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by:
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Geert Uytterhoeven authored
R-Car M2-N has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by:
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Geert Uytterhoeven authored
R-Car V2H has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by:
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Geert Uytterhoeven authored
R-Car M2-W has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by:
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Geert Uytterhoeven authored
R-Car H2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by:
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Geert Uytterhoeven authored
RZ/G1E has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by:
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Geert Uytterhoeven authored
RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by:
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Biju Das authored
Define the iWave RainboW-G20D-Qseven board dependent part of the Ethernet AVB device node. Signed-off-by:
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Biju Das authored
Add Ethernet AVB support for r8a7743 SoC. Signed-off-by:
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Biju Das authored
Adding pinctrl support for scif0 interface. Signed-off-by:
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