1. 08 Mar, 2018 34 commits
  2. 07 Mar, 2018 6 commits
    • Leon Romanovsky's avatar
      net/mlx5: Fix wrongly assigned CQ reference counter · 31135eb3
      Leon Romanovsky authored
      The kernel compiled with CONFIG_REFCOUNT_FULL produces the following
      error. The reason to it that initial value of refcount_t is supposed
      to be more than 0, change it.
      
      [    3.106634] ------------[ cut here ]------------
      [    3.107756] refcount_t: increment on 0; use-after-free.
      [    3.109130] WARNING: CPU: 0 PID: 1 at lib/refcount.c:153 refcount_inc+0x27/0x30
      [    3.110085] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.16.0-rc1-00028-gf683e04bdccc #137
      [    3.110085] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.7.5-0-ge51488c-20140602_164612-nilsson.home.kraxel.org 04/01/2014
      [    3.110085] RIP: 0010:refcount_inc+0x27/0x30
      [    3.110085] RSP: 0000:ffffaa620000fba0 EFLAGS: 00010286
      [    3.110085] RAX: 0000000000000000 RBX: ffff9a6d1a1821c8 RCX: ffffffff98a50f48
      [    3.110085] RDX: 0000000000000001 RSI: 0000000000000086 RDI: 0000000000000246
      [    3.110085] RBP: ffff9a6d1ac800a0 R08: 0000000000000289 R09: 000000000000000a
      [    3.110085] R10: fffff03bc0682840 R11: ffffffff9949856d R12: ffff9a6d1b4a4000
      [    3.110085] R13: 0000000000000000 R14: ffff9a6d1a0a6c00 R15: ffffaa620000fc5c
      [    3.110085] FS:  0000000000000000(0000) GS:ffff9a6d1fc00000(0000) knlGS:0000000000000000
      [    3.110085] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      [    3.110085] CR2: 0000000000000000 CR3: 000000000ba0a000 CR4: 00000000000006b0
      [    3.110085] Call Trace:
      [    3.110085]  mlx5_core_create_cq+0xde/0x250
      [    3.110085]  ? __kmalloc+0x1ce/0x1e0
      [    3.110085]  mlx5e_create_cq+0x15c/0x1e0
      [    3.110085]  mlx5e_open_drop_rq+0xea/0x190
      [    3.110085]  mlx5e_attach_netdev+0x53/0x140
      [    3.110085]  mlx5e_attach+0x3d/0x60
      [    3.110085]  mlx5e_add+0x11d/0x2f0
      [    3.110085]  mlx5_add_device+0x77/0x170
      [    3.110085]  mlx5_register_interface+0x74/0xc0
      [    3.110085]  ? set_debug_rodata+0x11/0x11
      [    3.110085]  init+0x67/0x72
      [    3.110085]  ? mlx4_en_init_ptys2ethtool_map+0x346/0x346
      [    3.110085]  do_one_initcall+0x98/0x147
      [    3.110085]  ? set_debug_rodata+0x11/0x11
      [    3.110085]  kernel_init_freeable+0x164/0x1e0
      [    3.110085]  ? rest_init+0xb0/0xb0
      [    3.110085]  kernel_init+0xa/0x100
      [    3.110085]  ret_from_fork+0x35/0x40
      [    3.110085] Code: 00 00 00 00 e8 ab ff ff ff 84 c0 74 02 f3 c3 80 3d 3b c3 64 01 00 75 f5 48 c7 c7 68 0b 81 98 c6 05 2b c3 64 01 01 e8 79 d7 a3 ff <0f> ff c3 66 0f 1f 44 00 00 8b 06 83 f8 ff 74 39 31 c9 39 f8 89
      [    3.110085] ---[ end trace a0068e1c68438a74 ]---
      
      Fixes: f105b45b ("net/mlx5: CQ hold/put API")
      Signed-off-by: default avatarLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      31135eb3
    • Aviad Yehezkel's avatar
      net/mlx5: IPSec, Add support for ESN · cb010083
      Aviad Yehezkel authored
      Currently ESN is not supported with IPSec device offload.
      
      This patch adds ESN support to IPsec device offload.
      Implementing new xfrm device operation to synchronize offloading device
      ESN with xfrm received SN. New QP command to update SA state at the
      following:
      
                 ESN 1                    ESN 2                  ESN 3
      |-----------*-----------|-----------*-----------|-----------*
      ^           ^           ^           ^           ^           ^
      
      ^ - marks where QP command invoked to update the SA ESN state
          machine.
      | - marks the start of the ESN scope (0-2^32-1). At this point move SA
          ESN overlap bit to zero and increment ESN.
      * - marks the middle of the ESN scope (2^31). At this point move SA
          ESN overlap bit to one.
      Signed-off-by: default avatarAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: default avatarYossef Efraim <yossefe@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      cb010083
    • Aviad Yehezkel's avatar
      net/mlx5e: Added common function for to_ipsec_sa_entry · 75ef3f55
      Aviad Yehezkel authored
      New function for getting driver internal sa entry from xfrm state.
      All checks are done in one function.
      Signed-off-by: default avatarAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      75ef3f55
    • Aviad Yehezkel's avatar
      net/mlx5: Add flow-steering commands for FPGA IPSec implementation · 05564d0a
      Aviad Yehezkel authored
      In order to add a context to the FPGA, we need to get both the software
      transform context (which includes the keys, etc) and the
      source/destination IPs (which are included in the steering
      rule). Therefore, we register new set of firmware like commands for
      the FPGA. Each time a rule is added, the steering core infrastructure
      calls the FPGA command layer. If the rule is intended for the FPGA,
      it combines the IPs information with the software transformation
      context and creates the respective hardware transform.
      Afterwards, it calls the standard steering command layer.
      Signed-off-by: default avatarAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      05564d0a
    • Aviad Yehezkel's avatar
      net/mlx5: Refactor accel IPSec code · d6c4f029
      Aviad Yehezkel authored
      The current code has one layer that executed FPGA commands and
      the Ethernet part directly used this code. Since downstream patches
      introduces support for IPSec in mlx5_ib, we need to provide some
      abstractions. This patch refactors the accel code into one layer
      that creates a software IPSec transformation and another one which
      creates the actual hardware context.
      The internal command implementation is now hidden in the FPGA
      core layer. The code also adds the ability to share FPGA hardware
      contexts. If two contexts are the same, only a reference count
      is taken.
      Signed-off-by: default avatarAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      d6c4f029
    • Aviad Yehezkel's avatar
      net/mlx5: Added required metadata capability for ipsec · af9fe19d
      Aviad Yehezkel authored
      Currently our device requires additional metadata in packet
      to perform ipsec crypto offload.
      Signed-off-by: default avatarAviad Yehezkel <aviadye@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      af9fe19d