- 14 Sep, 2009 4 commits
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Bjorn Helgaas authored
Convert quirk printks to dev_printk(). Signed-off-by:
Bjorn Helgaas <bjorn.helgaas@hp.com> CC: Olaf Dabrunz <od@suse.de> Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Rafael J. Wysocki authored
After commit c82f63e4 (PCI: check saved state before restore) pcie_portdrv_slot_reset() may not work correctly if dev->error_state is equal to pci_channel_io_frozen, because dev->state_saved need not be set at that time. Fix this issue by setting dev->state_saved before pci_restore_state() is called in pcie_portdrv_slot_reset(). Signed-off-by:
Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by:
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Alex Chiang authored
acpi_pci_detect_ejectable() goes through effort to convert its struct pci_bus arg to an acpi_handle, but every time we use this interface, we already have the handle available. So let's just use the handle instead of converting back and forth. Reviewed-by:
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Tested-by:
Alex Chiang <achiang@hp.com> Signed-off-by:
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Alex Chiang authored
Instead of constantly evaluating _ADR and _SEG over and over again, let's simplify our lives by using: acpi_pci_find_root() for root bridges acpi_get_pci_dev() for p2p bridges This change eliminates some copy 'n paste code and also allows us to simplify some internal interfaces. Reviewed-by:
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- 11 Sep, 2009 1 commit
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Jesse Barnes authored
Remove unused port_data variable left over from the MCH hotplug quirk cleanup. Signed-off-by:
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- 09 Sep, 2009 35 commits
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Rafael J. Wysocki authored
Some PCI devices (not PCI Express), like PCI add-on cards, can generate PME#, but they don't have any special platform wake-up support. For this reason, even if they generate PME# to wake up the system from a sleep state, wake-up events are not generated by the platform. It turns out that, at least on some systems, PCI bridges and the PCI host bridge have ACPI GPEs associated with them that, if enabled to generate wake-up events, allow the system to wake up if one of the add-on devices asserts PME# while the system is in a sleep state. Following this observation, if a PCI device without direct ACPI wake-up support is prepared to wake up the system during a transition into a sleep state (eg. suspend to RAM), try to configure the bridges on the path from the device to the root bridge to wake-up the system. Reviewed-by:
Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by:
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Rafael J. Wysocki authored
The wakeup.prepared flag is used for marking devices that have the wake-up power already enabled, so that the wake-up power is not enabled twice in a row for the same device. This assumes, however, that device wake-up power will only be enabled once, while the device is being prepared for a system-wide sleep transition, and the second attempt is made by acpi_enable_wakeup_device_prep(). With the upcoming PCI wake-up rework this assumption will not hold any more for PCI bridges and the root bridge whose wake-up power may be enabled as a result of wake-up enable propagation from other devices (eg. add-on devices that are not associated with any GPEs). Thus, there may be many attempts to enable wake-up power on a PCI bridge or the root bridge during a system power state transition and it's better to replace wakeup.prepared with a reference counter. Reviewed-by:
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Rafael J. Wysocki authored
Introduce a new PCI device flag, wakeup_prepared, to prevent PCI wake-up preparation code from being executed twice in a row for the same device and for the same purpose. Reviewed-by:
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Rafael J. Wysocki authored
Move a debug message from acpi_pci_sleep_wake() to acpi_pm_device_sleep_wake() and use the standard dev_*() macros in there. Reviewed-by:
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Rafael J. Wysocki authored
Rework the PCI wake-up code so that it's easier to read without changing the functionality. Reviewed-by:
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Jiri Slaby authored
Stanse found a pci reference leak in quirk_amd_nb_node. Instead of putting nb_ht, there is a put of dev passed as an argument. http://stanse.fi.muni.cz/Signed-off-by:
Jiri Slaby <jirislaby@gmail.com> Signed-off-by:
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Eric W. Biederman authored
In general a BIOS may goof or we may hotplug in a hotplug controller. In either case the kernel needs to reserve resources for plugging in more devices in the future instead of creating a minimal resource assignment. We already do this for cardbus bridges I am just adding a variant for pcie bridges. v2: Make testing for pcie hotplug bridges based on a flag. So far we only set the flag for pcie but a header_quirk could easily be added for the non-standard pci hotplug bridges. Signed-off-by:Eric W. Biederman <ebiederm@aristanetworks.com> Signed-off-by:
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Eric W. Biederman authored
There is a very old quirk for the intel E7502 E7320 and E7525 memory controller hubs that disables usage of msi interrupts on pcie hotplug bridges of those devices, and disables changing the affinity of irqs. Today all we have to do to disable msi on a specific device is to set dev->no_msi, which is much more straightforward than the previous logic. The re-running of this fixup after pci hotplug happens below these devices is totally bogus. All of the state we change is pure software state and we don't change the hardware at all. Which means hotplug on the lower devices doesn't have a chance to change this state. So we can safely remove the special case from the pciehp driver and the pcie portdriver. I suspect the special case was someone's expermental debug code that slipped in. Certainly it isn't mentioned in commit 6fb8880a61510295aece04a542767161f624dffe aka BKrev: 41966101LJ_ogfOU0m2aE6teZfQnuQ where the code first appears. Reviewed-by:
"Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by:
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Hidetoshi Seto authored
This patch is required not to lost error records by action invoked on error recovery, such as slot reset etc. Following sample (real machine + dummy record injected by aer-inject) shows that record of 28:00.1 could not be retrieved by recovery of 28:00.0: - Before: pcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id=2801 e1000e 0000:28:00.0: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2800(Receiver ID) e1000e 0000:28:00.0: device [8086:1096] error status/mask=00001000/00100000 e1000e 0000:28:00.0: [12] Poisoned TLP (First) e1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003 e1000e 0000:28:00.0: broadcast error_detected message e1000e 0000:28:00.0: broadcast slot_reset message e1000e 0000:28:00.0: setting latency timer to 64 e1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147) e1000e 0000:28:00.0: PME# disabled e1000e 0000:28:00.0: PME# disabled e1000e 0000:28:00.1: setting latency timer to 64 e1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147) e1000e 0000:28:00.1: PME# disabled e1000e 0000:28:00.1: PME# disabled e1000e 0000:28:00.0: broadcast resume message e1000e 0000:28:00.0: AER driver successfully recovered e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX - After: pcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id=2801 e1000e 0000:28:00.0: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2800(Receiver ID) e1000e 0000:28:00.0: device [8086:1096] error status/mask=00001000/00100000 e1000e 0000:28:00.0: [12] Poisoned TLP (First) e1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003 e1000e 0000:28:00.1: PCIE Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=2801(Receiver ID) e1000e 0000:28:00.1: device [8086:1096] error status/mask=00081000/00100000 e1000e 0000:28:00.1: [12] Poisoned TLP (First) e1000e 0000:28:00.1: [19] ECRC e1000e 0000:28:00.1: TLP Header: 00000000 00000001 00000002 00000003 e1000e 0000:28:00.1: Error of this Agent(2801) is reported first e1000e 0000:28:00.0: broadcast error_detected message e1000e 0000:28:00.0: broadcast slot_reset message e1000e 0000:28:00.0: setting latency timer to 64 e1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147) e1000e 0000:28:00.0: PME# disabled e1000e 0000:28:00.0: PME# disabled e1000e 0000:28:00.1: setting latency timer to 64 e1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147) e1000e 0000:28:00.1: PME# disabled e1000e 0000:28:00.1: PME# disabled e1000e 0000:28:00.0: broadcast resume message e1000e 0000:28:00.0: AER driver successfully recovered e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX Signed-off-by:
Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by:
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Hidetoshi Seto authored
Use dev_printk like format. Sample (real machine + dummy error injected by aer-inject): - Before: +------ PCI-Express Device Error ------+ Error Severity : Corrected PCIE Bus Error type : Data Link Layer Bad TLP : Receiver ID : 2800 VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=00h +------ PCI-Express Device Error ------+ Error Severity : Corrected PCIE Bus Error type : Data Link Layer Bad TLP : Bad DLLP : Receiver ID : 2801 VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=01h Error of this Agent(2801) is reported first - After: pcieport-driver 0000:00:02.0: AER: Multiple Corrected error received: id=2801 e1000e 0000:28:00.0: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2800(Receiver ID) e1000e 0000:28:00.0: device [8086:1096] error status/mask=00000040/00000000 e1000e 0000:28:00.0: [ 6] Bad TLP e1000e 0000:28:00.1: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2801(Receiver ID) e1000e 0000:28:00.1: device [8086:1096] error status/mask=000000c0/00000000 e1000e 0000:28:00.1: [ 6] Bad TLP e1000e 0000:28:00.1: [ 7] Bad DLLP e1000e 0000:28:00.1: Error of this Agent(2801) is reported first Signed-off-by:
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Hidetoshi Seto authored
Compact struct and codes. Signed-off-by:
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Hidetoshi Seto authored
Cleanup. Signed-off-by:
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Hidetoshi Seto authored
Multiple bits might be set in the Uncorrectable Error Status register. But aer_print_error_source() only report a error of the lowest bit set in the error status register. So print strings for all bits unmasked and set. And check First Error Pointer to mark the error occured first. This FEP is not valid when the corresponing bit of the Uncorrectable Error Status register is not set, or unimplemented or undefined. Signed-off-by:
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Hidetoshi Seto authored
ERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know, set of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h. This masks make aerdrv not to report errors of unknown bit, while aerdrv have ability to report such undefined errors as "Unknown Error Bit %2d". OTOH aerdrv_errprint does not have any check of setting in mask register. So it could report masked wrong error by finding bit in status without knowing that the bit is masked in the mask register. This patch changes aerdrv to use mask state in mask register propely instead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK. This change prevents aerdrv from reporting masked error, and also enable reporting unknown errors. Signed-off-by:Andrew Patterson <andrew.patterson@hp.com> Signed-off-by:
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Hidetoshi Seto authored
The static buffer errmsg_buff[] is used only for building error message in fixed format, and is protected by a spinlock. This patch removes this buffer and the spinlock. Signed-off-by:
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Hidetoshi Seto authored
The flag AER_MULTI_ERROR_VALID_FLAG in info->flag does mean that the root port receives multiple error messages. Error messages can be posted from different devices, so it does not mean that each reported device has multiple errors. If there are multiple error devices and the root port has valid error source ID, it would be nice to report which device is the error source reported first. Signed-off-by:
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Hidetoshi Seto authored
In case of multiple errors, struct aer_err_info would be reused among all reported devices. So the info->status should be initialized before recycled. Otherwise error of one device might be reported as the error of another device. Also info->flags has similar problem on reporting TLP header. Signed-off-by:
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Hidetoshi Seto authored
Definitions of MASK macros in aerdrv_errprint.c are tricky and unsafe. For example, AER_AGENT_TRANSMITTER_MASK(_sev, _stat) does work like: static inline func(int _sev, int _stat) { if (_sev == AER_CORRECTABLE) return (_stat & (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER)); else return (_stat & PCI_ERR_COR_REP_ROLL); } In case of else path here, for uncorrectable errors, testing bits in _stat by PCI_ERR_COR_* does not make sense because _stat should have only PCI_ERR_UNC_* bits originated in uncorrectable error status register. But at this time this is safe because uncorrectable error using bit position same to PCI_ERR_COR_REP_ROLL(= bit position 8) is not defined. Likewise, AER_AGENT_COMPLETER_MASK is always PCI_ERR_UNC_COMP_ABORT but it works because bit 15 of correctable error status is not defined. It means that these MASK macros will turn to be wrong once if new error is defined. (In fact, bit 15 of correctable is now defined in PCIe 2.1) This patch changes these MASK macros to be more strict, not to return PCI_ERR_COR_* bits for uncorrectable error status and vise versa. Signed-off-by: -
Hidetoshi Seto authored
Add workaround macro to reduce the number of checkpatch warning: WARNING: printk() should include KERN_ facility level Before: total: 0 errors, 10 warnings, 247 lines checked After: total: 0 errors, 1 warnings, 243 lines checked Signed-off-by:
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Hidetoshi Seto authored
Before: drivers/pci/pcie/aer/aer_inject.c total: 4 errors, 4 warnings, 473 lines checked drivers/pci/pcie/aer/aerdrv.c total: 5 errors, 2 warnings, 333 lines checked drivers/pci/pcie/aer/aerdrv.h total: 1 errors, 0 warnings, 139 lines checked drivers/pci/pcie/aer/aerdrv_core.c total: 4 errors, 3 warnings, 872 lines checked drivers/pci/pcie/aer/aerdrv_errprint.c total: 12 errors, 11 warnings, 248 lines checked After: drivers/pci/pcie/aer/aer_inject.c total: 0 errors, 0 warnings, 466 lines checked drivers/pci/pcie/aer/aerdrv.c total: 0 errors, 0 warnings, 335 lines checked drivers/pci/pcie/aer/aerdrv.h total: 0 errors, 0 warnings, 139 lines checked drivers/pci/pcie/aer/aerdrv_core.c total: 0 errors, 0 warnings, 869 lines checked drivers/pci/pcie/aer/aerdrv_errprint.c total: 0 errors, 10 warnings, 247 lines checked Signed-off-by:
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Tejun Heo authored
Add ids module parameter which allows specifying initial IDs for the pci-stub driver. When built into the kernel, pci-stub is linked before any real pci drivers and by setting up IDs from initialization it can prevent built-in drivers from attaching to specific devices. While at it, make pci_stub_probe() print out about devices it grabbed to weed out "but my controller isn't being probed" bug reports. Signed-off-by:
Tejun Heo <tj@kernel.org> Signed-off-by:
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Tejun Heo authored
Separate out pci_add_dynid() from store_new_id() and export it so that in-kernel code can add PCI IDs dynamically. As the function will be available regardless of HOTPLUG, put it and pull pci_free_dynids() outside of CONFIG_HOTPLUG. This will be used by pci-stub to initialize initial IDs via module param. While at it, remove bogus get_driver() failure check. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Reviewed-by:
Grant Grundler <grundler@parisc-linux.org> Signed-off-by:
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Kenji Kaneshige authored
Add support for PCI-E 5.0 GT/s in max_bus_speed and cur_bus_speed. Reviewed-by:
Matthew Wilcox <matthew@wil.cx> Signed-off-by:
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Kenji Kaneshige authored
Fix typo in PCI-E link speed. Reviewed-by:
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Kenji Kaneshige authored
The L0s state can be managed separately for each direction (upstream direction and downstream direction) of the link. But in the current implementation, those are mixed up. With this patch, L0s for each direction are managed separately. To maintain three states (upstream direction L0s, downstream L0s and L1), 'aspm_support', 'aspm_enabled', 'aspm_capable', 'aspm_disable' and 'aspm_default' fields in struct pcie_link_state are changed to 3-bit from 2-bit. The 'latency' field is separated to two 'latency_up' and 'latency_dw' fields to maintain exit latencies for each direction of the link. For L0, 'latency_up.l0' and 'latency_dw.l0' are used to configure upstream direction L0s and downstream direction L0s respectively. For L1, larger value of 'latency_up.l1' and 'latency_dw.l1' is considered as L1 exit latency. Acked-by:
Shaohua Li <shaohua.li@intel.com> Signed-off-by:
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Kenji Kaneshige authored
In the current implementation, ASPM L0s/L1 is disabled for all links in the hierarchy if one of the link doesn't meet latency requirement. But we can partially enable ASPM L0s/L1 on sub-tree in the hierarchy. This patch allows partial L0s/L1 enablement in the hierarchy. And it also reduce the calculation cost of ASPM configuration very much. In the previous implementation, all links were enabled with the same state. With this patch, enabled state for each link is determined simply as follows (the 'requested' is from policy_to_aspm_state()). enabled = requested & (link->aspm_capable & link->aspm_disable) Acked-by: -
Kenji Kaneshige authored
Introduce 'aspm_capable' field to maintain the capable ASPM setting of the link. By the 'aspm_capable', we don't need to recheck latency every time ASPM policy is changed. Each bit in 'aspm_capable' is associated to ASPM state (L0S/L1). The bit is set if the associated ASPM state is supported by the link and it satisfies the latency requirement (i.e. exit latency < endpoint acceptable latency). The 'aspm_capable' is updated when - an endpoint device is added (boot time or hot-plug time) - an endpoint device is removed (hot-unplug time) - PCI power state is changed. Acked-by:
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Kenji Kaneshige authored
Introduce 'aspm_disable' flag to manage disabled ASPM state more robust way. Acked-by:
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Kenji Kaneshige authored
Fix possible NULL dereference in pcie_aspm_exit_link_state(). This patch also cleanup some code. Acked-by:
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Kenji Kaneshige authored
Remove the following check in __pcie_aspm_config_link() because it nerver be true. Acked-by:
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Kenji Kaneshige authored
We must not clear bits in 'aspm_enabled' using 'aspm_support', or 'aspm_enabled' and 'aspm_default' might be different from the actual state. In addtion, 'aspm_default' should be intialized even if 'aspm_support' is 0. Acked-by:
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Alexander Duyck authored
This patch adds the most recent additions to the list of 82576 device IDs to the list of devices needing the SR-IOV quirk. Signed-off-by:
Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by:
Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by:
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Tiago Vignatti authored
Document the new VGA arbiter. Signed-off-by:
Tiago Vignatti <tiago.vignatti@nokia.com> Signed-off-by:
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Dave Airlie authored
Fix some warnings reported in linux-next + also cleanup some comment errors noticed by Pekka Paalanen. Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Mike Mason authored
By default, the EEH framework on powerpc does what's known as a "hot reset" during recovery of a PCI Express device. We've found a case where the device needs a "fundamental reset" to recover properly. The current PCI error recovery and EEH frameworks do not support this distinction. The attached patch makes changes to EEH to utilize the new bit field. Signed-off-by:
Mike Mason <mmlnx@us.ibm.com> Signed-off-by:
Richard Lary <rlary@us.ibm.com> Signed-off-by:
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