Commit faadc6df authored by Thomas Gambier's avatar Thomas Gambier 🚴🏼

Update README

parent 5ec75ea3
# M2 to ethernet board design on kicad 8 # M2 to ethernet board design on kicad 8
This repository holds the hardware for M2 to ethernet board which has a intel I225 . This repository holds the hardware for M2 to ethernet board with a intel I225 controler with TSN feature.
This board contains : This board contains :
* a I225 : KTI225IT S LNNL from intel * a I225 : KTI225IT S LNNL from intel
-advance feature : Time Sensitive Networking (TSN) – – advance feature : Time Sensitive Networking (TSN) –
* an 8-pin connector to manage an Ethernet network (need specific cable adapter * a 8-pin connector (not RJ45 !) to connect an Ethernet cable
to connect Ethernet network)
* a PPS output on UFL connector * a PPS output on UFL connector
Release 1 : not working
Release 1 : fixed bugs
* fix signal inversion: PCIE_TX_N with PCIE_TX_P Release 1 (July 2024) : first version (not working)
* fix Intel reference I225 with advance feature to to handle TSN
* remove from design solder paste from connectors Release 2 (Nov 2024) :
* add solder paste on ethernet transformer pads * fixed bugs
* remove gnd plane under ethernet transformer + fix signal inversion: PCIE_TX_N with PCIE_TX_P
+ fix Intel reference I225 with advance feature to to handle TSN
Release 2 : add ons + remove from design solder paste from connectors
* PCIE SM bus is now connected I225 (normally not necessary) + add solder paste on ethernet transformer pads
* The flash can be programmed via an external SPI programmer. + remove gnd plane under ethernet transformer
* addons
+ PCIE SM bus is now connected I225 (normally not necessary)
+ The flash can be programmed via an external SPI programmer:
- 4 resistors need to be removed to operate this programming - 4 resistors need to be removed to operate this programming
- SPI bus connection and supply are on 1mm test point - SPI bus connection and supply are on 1mm test point
* what remains to be done :
Release 2 published on 28.11.2024 * complete fonctionnel schematic rewiew
what remains to be done : * check bom (possibly reduce bom by grouping components)
* complete fonctionnel schematic rewiew * generate fab files
* check bom (possibly reduce bom by grouping components)
* generate fab files
......
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