Merge branch 'grooverdan-10.2-MDEV-9872-crc32-generic-message' into 10.2

storage/innobase/include/ut0crc32.h

 /*****************************************************************************
 
 Copyright (c) 2011, 2015, Oracle and/or its affiliates. All Rights Reserved.
+Copyright (c) 2016, MariaDB Corporation.
 
 This program is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free Software
@@ -54,8 +55,6 @@ extern ut_crc32_func_t	ut_crc32_legacy_big_endian;
 but very slow). */
 extern ut_crc32_func_t	ut_crc32_byte_by_byte;
 
-/** Flag that tells whether the CPU supports CRC32 or not */
-extern bool		ut_crc32_sse2_enabled;
-extern bool		ut_crc32_power8_enabled;
+extern const char*	ut_crc32_implementation;
 
 #endif /* ut0crc32_h */

storage/innobase/srv/srv0start.cc

@@ -1702,13 +1702,8 @@ innobase_start_or_create_for_mysql(void)
 
 	srv_boot();
 
-	if (ut_crc32_sse2_enabled) {
-		ib::info() << "Using SSE crc32 instructions";
-	} else if (ut_crc32_power8_enabled) {
-		ib::info() << "Using POWER8 crc32 instructions";
-	} else {
-		ib::info() << "Using generic crc32 instructions";
-	}
+	ib::info() << ut_crc32_implementation;
+
 
 	if (!srv_read_only_mode) {
 

storage/innobase/ut/ut0crc32.cc

@@ -2,6 +2,7 @@
 
 Copyright (c) 2009, 2010 Facebook, Inc. All Rights Reserved.
 Copyright (c) 2011, 2015, Oracle and/or its affiliates. All Rights Reserved.
+Copyright (c) 2016, MariaDB Corporation.
 
 This program is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free Software
@@ -96,6 +97,9 @@ ut_crc32_func_t	ut_crc32_legacy_big_endian;
 but very slow). */
 ut_crc32_func_t	ut_crc32_byte_by_byte;
 
+/** Text description of CRC32 implementation */
+const char*	ut_crc32_implementation;
+
 /** Swap the byte order of an 8 byte integer.
 @param[in]	i	8-byte integer
 @return 8-byte integer */
@@ -116,10 +120,6 @@ ut_crc32_swap_byteorder(
 
 /* CRC32 hardware implementation. */
 
-/* Flag that tells whether the CPU supports CRC32 or not */
-bool	ut_crc32_sse2_enabled = false;
-UNIV_INTERN bool	ut_crc32_power8_enabled = false;
-
 #ifdef HAVE_CRC32_VPMSUM
 extern "C" {
 unsigned int crc32c_vpmsum(unsigned int crc, const unsigned char *p, unsigned long len);
@@ -284,8 +284,6 @@ ut_crc32_hw(
 {
 	uint32_t	crc = 0xFFFFFFFFU;
 
-	ut_a(ut_crc32_sse2_enabled);
-
 	/* Calculate byte-by-byte up to an 8-byte aligned address. After
 	this consume the input 8-bytes at a time. */
 	while (len > 0 && (reinterpret_cast<uintptr_t>(buf) & 7) != 0) {
@@ -375,8 +373,6 @@ ut_crc32_legacy_big_endian_hw(
 {
 	uint32_t	crc = 0xFFFFFFFFU;
 
-	ut_a(ut_crc32_sse2_enabled);
-
 	/* Calculate byte-by-byte up to an 8-byte aligned address. After
 	this consume the input 8-bytes at a time. */
 	while (len > 0 && (reinterpret_cast<uintptr_t>(buf) & 7) != 0) {
@@ -427,8 +423,6 @@ ut_crc32_byte_by_byte_hw(
 {
 	uint32_t	crc = 0xFFFFFFFFU;
 
-	ut_a(ut_crc32_sse2_enabled);
-
 	while (len > 0) {
 		ut_crc32_8_hw(&crc, &buf, &len);
 	}
@@ -452,7 +446,6 @@ void
 ut_crc32_slice8_table_init()
 /*========================*/
 {
-#ifndef HAVE_CRC32_VPMSUM
 	/* bit-reversed poly 0x1EDC6F41 (from SSE42 crc32 instruction) */
 	static const uint32_t	poly = 0x82f63b78;
 	uint32_t		n;
@@ -476,7 +469,6 @@ ut_crc32_slice8_table_init()
 	}
 
 	ut_crc32_slice8_table_initialized = true;
-#endif
 }
 
 /** Calculate CRC32 over 8-bit data using a software implementation.
@@ -706,6 +698,12 @@ void
 ut_crc32_init()
 /*===========*/
 {
+	ut_crc32_slice8_table_init();
+	ut_crc32 = ut_crc32_sw;
+	ut_crc32_legacy_big_endian = ut_crc32_legacy_big_endian_sw;
+	ut_crc32_byte_by_byte = ut_crc32_byte_by_byte_sw;
+	ut_crc32_implementation = "Using generic crc32 instructions";
+
 #if defined(__GNUC__) && defined(__x86_64__)
 	uint32_t	vend[3];
 	uint32_t	model;
@@ -733,27 +731,17 @@ ut_crc32_init()
 	probably kill your program.
 
 	*/
-#ifndef UNIV_DEBUG_VALGRIND
-	ut_crc32_sse2_enabled = (features_ecx >> 20) & 1;
-#endif /* UNIV_DEBUG_VALGRIND */
 
-	if (ut_crc32_sse2_enabled) {
+	if (features_ecx & 1 << 20) {
 		ut_crc32 = ut_crc32_hw;
 		ut_crc32_legacy_big_endian = ut_crc32_legacy_big_endian_hw;
 		ut_crc32_byte_by_byte = ut_crc32_byte_by_byte_hw;
+		ut_crc32_implementation = "Using SSE2 crc32 instructions";
 	}
 
-#endif /* defined(__GNUC__) && defined(__x86_64__) */
-
-#ifdef HAVE_CRC32_VPMSUM
-	ut_crc32_power8_enabled = true;
+#elif defined(HAVE_CRC32_VPMSUM)
 	ut_crc32 = ut_crc32_power8;
+	ut_crc32_implementation = "Using POWER8 crc32 instructions";
 #endif
 
-	if (!ut_crc32_sse2_enabled && !ut_crc32_power8_enabled) {
-		ut_crc32_slice8_table_init();
-		ut_crc32 = ut_crc32_sw;
-		ut_crc32_legacy_big_endian = ut_crc32_legacy_big_endian_sw;
-		ut_crc32_byte_by_byte = ut_crc32_byte_by_byte_sw;
-	}
 }

storage/xtradb/include/ut0crc32.h

@@ -46,7 +46,6 @@ typedef ib_uint32_t (*ib_ut_crc32_t)(const byte* ptr, ulint len);
 
 extern ib_ut_crc32_t	ut_crc32;
 
-extern bool	ut_crc32_sse2_enabled;
-extern bool     ut_crc32_power8_enabled;
+extern const char *ut_crc32_implementation;
 
 #endif /* ut0crc32_h */

storage/xtradb/srv/srv0start.cc

@@ -1938,13 +1938,7 @@ innobase_start_or_create_for_mysql(void)
 
 	srv_boot();
 
-	if (ut_crc32_sse2_enabled) {
-		ib_logf(IB_LOG_LEVEL_INFO, "Using SSE crc32 instructions");
-	} else if (ut_crc32_power8_enabled) {
-		ib_logf(IB_LOG_LEVEL_INFO, "Using POWER8 crc32 instructions");
-	} else {
-		ib_logf(IB_LOG_LEVEL_INFO, "Using generic crc32 instructions");
-	}
+	ib_logf(IB_LOG_LEVEL_INFO, ut_crc32_implementation);
 
 	if (!srv_read_only_mode) {
 

storage/xtradb/ut/ut0crc32.cc

@@ -97,9 +97,8 @@ have support for it */
 static ib_uint32_t	ut_crc32_slice8_table[8][256];
 static ibool		ut_crc32_slice8_table_initialized = FALSE;
 
-/* Flag that tells whether the CPU supports CRC32 or not */
-UNIV_INTERN bool	ut_crc32_sse2_enabled = false;
-UNIV_INTERN bool	ut_crc32_power8_enabled = false;
+/** Text description of CRC32 implementation */
+const char *ut_crc32_implementation = NULL;
 
 /********************************************************************//**
 Initializes the table that is used to generate the CRC32 if the CPU does
@@ -213,8 +212,6 @@ ut_crc32_sse42(
 #if defined(__GNUC__) && defined(__x86_64__)
 	ib_uint64_t	crc = (ib_uint32_t) (-1);
 
-	ut_a(ut_crc32_sse2_enabled);
-
 	while (len && ((ulint) buf & 7)) {
 		ut_crc32_sse42_byte;
 	}
@@ -302,6 +299,10 @@ void
 ut_crc32_init()
 /*===========*/
 {
+	ut_crc32_slice8_table_init();
+	ut_crc32 = ut_crc32_slice8;
+	ut_crc32_implementation = "Using generic crc32 instructions";
+
 #if defined(__GNUC__) && defined(__x86_64__)
 	ib_uint32_t	vend[3];
 	ib_uint32_t	model;
@@ -329,21 +330,13 @@ ut_crc32_init()
 	probably kill your program.
 
 	*/
-#ifndef UNIV_DEBUG_VALGRIND
-	ut_crc32_sse2_enabled = (features_ecx >> 20) & 1;
-#endif /* UNIV_DEBUG_VALGRIND */
-
-#endif /* defined(__GNUC__) && defined(__x86_64__) */
-
-#ifdef HAVE_CRC32_VPMSUM
-	ut_crc32_power8_enabled = true;
-	ut_crc32 = ut_crc32_power8;
-#else
-	if (ut_crc32_sse2_enabled) {
+	if ((features_ecx >> 20) & 1) {
 		ut_crc32 = ut_crc32_sse42;
-	} else {
-		ut_crc32_slice8_table_init();
-		ut_crc32 = ut_crc32_slice8;
+		ut_crc32_implementation = "Using SSE2 crc32 instructions";
 	}
+
+#elif defined(HAVE_CRC32_VPMSUM)
+	ut_crc32 = ut_crc32_power8;
+	ut_crc32_implementation = "Using POWER8 crc32 instructions";
 #endif
 }