The current global interrupt clear programming register offset
was not correct. Fix the programming with right offset

Fixes: ded1f3db ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")
Cc: stable@vger.kernel.org
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Link: https://lore.kernel.org/r/20230102064844.31306-1-mkumard@nvidia.comSigned-off-by: Vinod Koul <vkoul@kernel.org>