• Albert Lee's avatar
    libata: pata_pdc2027x PLL input clock fix · 8c781bf7
    Albert Lee authored
    Recently the PLL input clock of pata_pdc2027x is sometimes detected
    higer than expected (e.g. 20.027 MHz compared to 16.714 MHz).
    It seems sometimes the mdelay() function is not as precise as it
    used to be. Per Alan's advice, HT or power management might affect
    the precision of mdelay().
    
    This patch calls gettimeofday() to mesure the time elapsed and
    calculate the PLL input clock accordingly.
    Signed-off-by: default avatarAlbert Lee <albertcc@tw.ibm.com>
    Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
    Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
    8c781bf7
pata_pdc2027x.c 23.3 KB