Commit 22bd1f7e authored by Stephen Warren's avatar Stephen Warren

ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent b46b0b54
......@@ -281,7 +281,7 @@ isl29018@44 {
};
i2c@7000c400 {
clock-frequency = <400000>;
clock-frequency = <100000>;
};
i2c@7000c500 {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment