ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.
Signed-off-by: Stephen Warren <swarren@nvidia.com>

arch/arm/boot/dts/tegra-seaboard.dts

@@ -281,7 +281,7 @@ isl29018@44 {
 	};
 
 	i2c@7000c400 {
-		clock-frequency = <400000>;
+		clock-frequency = <100000>;
 	};
 
 	i2c@7000c500 {