Skip to content

L
linux
Commit 276836d4 authored by Ben Skeggs's avatar Ben Skeggs
Browse files
Options

drm/nouveau/gr: switch to device pri macros 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 87744403
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1181 additions and 1089 deletions
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View file @ 276836d4
......@@ -1005,6 +1005,7 @@ void
gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data,
int shift, int buffer)
{
struct nvkm_device *device = info->gr->base.engine.subdev.device;
if (info->data) {
if (shift >= 0) {
info->mmio->addr = addr;
......@@ -1021,7 +1022,7 @@ gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data,
return;
}
nv_wr32(info->gr, addr, data);
nvkm_wr32(device, addr, data);
}
void
......@@ -1085,20 +1086,21 @@ gf100_grctx_generate_unkn(struct gf100_gr *gr)
void
gf100_grctx_generate_tpcid(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
if (tpc < gr->tpc_nr[gpc]) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x4e8), id);
nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), id);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
......@@ -1106,18 +1108,20 @@ gf100_grctx_generate_tpcid(struct gf100_gr *gr)
void
gf100_grctx_generate_r406028(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 tmp[GPC_MAX / 8] = {}, i = 0;
for (i = 0; i < gr->gpc_nr; i++)
tmp[i / 8] |= gr->tpc_nr[i] << ((i % 8) * 4);
for (i = 0; i < 4; i++) {
nv_wr32(gr, 0x406028 + (i * 4), tmp[i]);
nv_wr32(gr, 0x405870 + (i * 4), tmp[i]);
nvkm_wr32(device, 0x406028 + (i * 4), tmp[i]);
nvkm_wr32(device, 0x405870 + (i * 4), tmp[i]);
}
}
void
gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
......@@ -1134,12 +1138,13 @@ gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
}
for (i = 0; i < 4; i++)
nv_wr32(gr, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
}
void
gf100_grctx_generate_r418bb8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
u8 shift, ntpcv;
......@@ -1176,28 +1181,29 @@ gf100_grctx_generate_r418bb8(struct gf100_gr *gr)
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
nv_wr32(gr, 0x419bd0, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) |
gr->magic_not_rop_nr | data2[0]);
nv_wr32(gr, 0x419be4, data2[1]);
nvkm_wr32(device, 0x419be4, data2[1]);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x419b00 + (i * 4), data[i]);
nvkm_wr32(device, 0x419b00 + (i * 4), data[i]);
/* UNK78xx */
nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x40780c + (i * 4), data[i]);
nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
}
void
gf100_grctx_generate_r406800(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
int gpc, tpc;
......@@ -1219,11 +1225,11 @@ gf100_grctx_generate_r406800(struct gf100_gr *gr)
tpc_set |= 1ULL << ((gpc * 8) + tpc);
}
nv_wr32(gr, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
nv_wr32(gr, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
nvkm_wr32(device, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
nvkm_wr32(device, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
if (gr->gpc_nr > 4) {
nv_wr32(gr, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
nv_wr32(gr, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
nvkm_wr32(device, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
nvkm_wr32(device, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
}
}
}
......@@ -1231,6 +1237,7 @@ gf100_grctx_generate_r406800(struct gf100_gr *gr)
void
gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
nvkm_mc(gr)->unk260(nvkm_mc(gr), 0);
......@@ -1241,7 +1248,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, oclass->tpc);
gf100_gr_mmio(gr, oclass->ppc);
nv_wr32(gr, 0x404154, 0x00000000);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
......@@ -1255,7 +1262,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_r406800(gr);
gf100_gr_icmd(gr, oclass->icmd);
nv_wr32(gr, 0x404154, 0x00000400);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, oclass->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
......@@ -1264,7 +1271,8 @@ int
gf100_grctx_generate(struct gf100_gr *gr)
{
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
struct nvkm_bar *bar = nvkm_bar(gr);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_bar *bar = device->bar;
struct nvkm_gpuobj *chan;
struct gf100_grctx info;
int ret, i;
......@@ -1302,8 +1310,8 @@ gf100_grctx_generate(struct gf100_gr *gr)
bar->flush(bar);
nv_wr32(gr, 0x100cb8, (chan->addr + 0x1000) >> 8);
nv_wr32(gr, 0x100cbc, 0x80000001);
nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8);
nvkm_wr32(device, 0x100cbc, 0x80000001);
nv_wait(gr, 0x100c80, 0x00008000, 0x00008000);
/* setup default state for mmio list construction */
......@@ -1315,9 +1323,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
/* make channel current */
if (gr->firmware) {
nv_wr32(gr, 0x409840, 0x00000030);
nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
nv_wr32(gr, 0x409504, 0x00000003);
nvkm_wr32(device, 0x409840, 0x00000030);
nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12);
nvkm_wr32(device, 0x409504, 0x00000003);
if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010))
nv_error(gr, "load_ctx timeout\n");
......@@ -1327,9 +1335,9 @@ gf100_grctx_generate(struct gf100_gr *gr)
nv_wo32(chan, 0x8002c, 0);
bar->flush(bar);
} else {
nv_wr32(gr, 0x409840, 0x80000000);
nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12);
nv_wr32(gr, 0x409504, 0x00000001);
nvkm_wr32(device, 0x409840, 0x80000000);
nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12);
nvkm_wr32(device, 0x409504, 0x00000001);
if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000))
nv_error(gr, "HUB_SET_CHAN timeout\n");
}
......@@ -1339,8 +1347,8 @@ gf100_grctx_generate(struct gf100_gr *gr)
/* trigger a context unload by unsetting the "next channel valid" bit
* and faking a context switch interrupt
*/
nv_mask(gr, 0x409b04, 0x80000000, 0x00000000);
nv_wr32(gr, 0x409000, 0x00000100);
nvkm_mask(device, 0x409b04, 0x80000000, 0x00000000);
nvkm_wr32(device, 0x409000, 0x00000100);
if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) {
nv_error(gr, "grctx template channel unload timeout\n");
ret = -EBUSY;
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
View file @ 276836d4
......@@ -767,12 +767,13 @@ gf108_grctx_generate_attrib(struct gf100_grctx *info)
void
gf108_grctx_generate_unkn(struct gf100_gr *gr)
{
nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
nv_mask(gr, 0x419814, 0x00000004, 0x00000004);
nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001);
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x419814, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
struct nvkm_oclass *
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
View file @ 276836d4
......@@ -219,6 +219,7 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info)
void
gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
......@@ -230,7 +231,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, oclass->tpc);
gf100_gr_mmio(gr, oclass->ppc);
nv_wr32(gr, 0x404154, 0x00000000);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
......@@ -244,10 +245,10 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
gf100_gr_icmd(gr, oclass->icmd);
nv_wr32(gr, 0x404154, 0x00000400);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, oclass->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View file @ 276836d4
......@@ -874,17 +874,19 @@ gk104_grctx_generate_pagepool(struct gf100_grctx *info)
void
gk104_grctx_generate_unkn(struct gf100_gr *gr)
{
nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(gr, 0x41980c, 0x00000010, 0x00000010);
nv_mask(gr, 0x41be08, 0x00000004, 0x00000004);
nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000);
nv_mask(gr, 0x405800, 0x08000000, 0x08000000);
nv_mask(gr, 0x419c00, 0x00000008, 0x00000008);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001);
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
void
gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
u8 shift, ntpcv;
......@@ -921,36 +923,38 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr)
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x418b08 + (i * 4), data[i]);
nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
nv_wr32(gr, 0x41bfd0, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
gr->magic_not_rop_nr | data2[0]);
nv_wr32(gr, 0x41bfe4, data2[1]);
nvkm_wr32(device, 0x41bfe4, data2[1]);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x41bf00 + (i * 4), data[i]);
nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]);
/* UNK78xx */
nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) |
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->magic_not_rop_nr);
for (i = 0; i < 6; i++)
nv_wr32(gr, 0x40780c + (i * 4), data[i]);
nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
}
void
gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
const u32 fbp_count = nv_rd32(gr, 0x120074);
nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x120074);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
......@@ -962,7 +966,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, oclass->tpc);
gf100_gr_mmio(gr, oclass->ppc);
nv_wr32(gr, 0x404154, 0x00000000);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
......@@ -975,19 +979,19 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nv_mask(gr, 0x419f78, 0x00000001, 0x00000000);
nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000);
gf100_gr_icmd(gr, oclass->icmd);
nv_wr32(gr, 0x404154, 0x00000400);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, oclass->mthd);
nvkm_mc(gr)->unk260(nvkm_mc(gr), 1);
nv_mask(gr, 0x418800, 0x00200000, 0x00200000);
nv_mask(gr, 0x41be10, 0x00800000, 0x00800000);
nvkm_mask(device, 0x418800, 0x00200000, 0x00200000);
nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000);
}
struct nvkm_oclass *
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
View file @ 276836d4
......@@ -28,6 +28,7 @@
static void
gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i;
......@@ -36,8 +37,8 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_wait_idle(gr);
idle_timeout_save = nv_rd32(gr, 0x404154);
nv_wr32(gr, 0x404154, 0x00000000);
idle_timeout_save = nvkm_rd32(device, 0x404154);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->attrib(info);
......@@ -49,17 +50,17 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_r406800(gr);
for (i = 0; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nv_mask(gr, 0x5044b0, 0x8000000, 0x8000000);
nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000);
gf100_gr_wait_idle(gr);
nv_wr32(gr, 0x404154, idle_timeout_save);
nvkm_wr32(device, 0x404154, idle_timeout_save);
gf100_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->fuc_method);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
View file @ 276836d4
......@@ -934,19 +934,20 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info)
void
gm107_grctx_generate_tpcid(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
if (tpc < gr->tpc_nr[gpc]) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
}
}
......@@ -954,6 +955,7 @@ gm107_grctx_generate_tpcid(struct gf100_gr *gr)
static void
gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int i;
......@@ -963,7 +965,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, oclass->tpc);
gf100_gr_mmio(gr, oclass->ppc);
nv_wr32(gr, 0x404154, 0x00000000);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
......@@ -975,23 +977,23 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gk104_grctx_generate_r418bb8(gr);
gf100_grctx_generate_r406800(gr);
nv_wr32(gr, 0x4064d0, 0x00000001);
nvkm_wr32(device, 0x4064d0, 0x00000001);
for (i = 1; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(gr, 0x406500, 0x00000001);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x406500, 0x00000001);
nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
gf100_gr_icmd(gr, oclass->icmd);
nv_wr32(gr, 0x404154, 0x00000400);
nvkm_wr32(device, 0x404154, 0x00000400);
gf100_gr_mthd(gr, oclass->mthd);
nv_mask(gr, 0x419e00, 0x00808080, 0x00808080);
nv_mask(gr, 0x419ccc, 0x80000000, 0x80000000);
nv_mask(gr, 0x419f80, 0x80000000, 0x80000000);
nv_mask(gr, 0x419f88, 0x80000000, 0x80000000);
nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080);
nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000);
nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000);
nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000);
}
struct nvkm_oclass *
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c
View file @ 276836d4
......@@ -921,14 +921,15 @@ gm204_grctx_pack_ppc[] = {
void
gm204_grctx_generate_tpcid(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc, id;
for (tpc = 0, id = 0; tpc < 4; tpc++) {
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
if (tpc < gr->tpc_nr[gpc]) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id);
nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id);
id++;
}
}
......@@ -938,14 +939,16 @@ gm204_grctx_generate_tpcid(struct gf100_gr *gr)
static void
gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
const u32 fbp_count = nv_rd32(gr, 0x12006c);
nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */
nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x12006c);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
gm204_grctx_generate_405b60(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
u32 dist[TPC_MAX / 4] = {};
u32 gpcs[GPC_MAX] = {};
......@@ -969,14 +972,15 @@ gm204_grctx_generate_405b60(struct gf100_gr *gr)
}
for (i = 0; i < dist_nr; i++)
nv_wr32(gr, 0x405b60 + (i * 4), dist[i]);
nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
for (i = 0; i < gr->gpc_nr; i++)
nv_wr32(gr, 0x405ba0 + (i * 4), gpcs[i]);
nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
}
void
gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
u32 tmp;
int i;
......@@ -987,7 +991,7 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_mmio(gr, oclass->tpc);
gf100_gr_mmio(gr, oclass->ppc);
nv_wr32(gr, 0x404154, 0x00000000);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
......@@ -999,25 +1003,25 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(gr, 0x406500, 0x00000000);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x406500, 0x00000000);
nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gm204_grctx_generate_rop_active_fbps(gr);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nv_wr32(gr, 0x4041c4, tmp);
nvkm_wr32(device, 0x4041c4, tmp);
gm204_grctx_generate_405b60(gr);
gf100_gr_icmd(gr, oclass->icmd);
nv_wr32(gr, 0x404154, 0x00000800);
nvkm_wr32(device, 0x404154, 0x00000800);
gf100_gr_mthd(gr, oclass->mthd);
nv_mask(gr, 0x418e94, 0xffffffff, 0xc4230000);
nv_mask(gr, 0x418e4c, 0xffffffff, 0x70000000);
nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000);
nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000);
}
struct nvkm_oclass *
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
View file @ 276836d4
......@@ -24,19 +24,21 @@
static void
gm20b_grctx_generate_r406028(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 tpc_per_gpc = 0;
int i;
for (i = 0; i < gr->gpc_nr; i++)
tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
nv_wr32(gr, 0x406028, tpc_per_gpc);
nv_wr32(gr, 0x405870, tpc_per_gpc);
nvkm_wr32(device, 0x406028, tpc_per_gpc);
nvkm_wr32(device, 0x405870, tpc_per_gpc);
}
static void
gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
int idle_timeout_save;
int i, tmp;
......@@ -45,8 +47,8 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_wait_idle(gr);
idle_timeout_save = nv_rd32(gr, 0x404154);
nv_wr32(gr, 0x404154, 0x00000000);
idle_timeout_save = nvkm_rd32(device, 0x404154);
nvkm_wr32(device, 0x404154, 0x00000000);
oclass->attrib(info);
......@@ -57,22 +59,22 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gk104_grctx_generate_r418bb8(gr);
for (i = 0; i < 8; i++)
nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gk104_grctx_generate_rop_active_fbps(gr);
nv_wr32(gr, 0x408908, nv_rd32(gr, 0x410108) | 0x80000000);
nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nv_wr32(gr, 0x4041c4, tmp);
nvkm_wr32(device, 0x4041c4, tmp);
gm204_grctx_generate_405b60(gr);
gf100_gr_wait_idle(gr);
nv_wr32(gr, 0x404154, idle_timeout_save);
nvkm_wr32(device, 0x404154, idle_timeout_save);
gf100_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->fuc_method);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
View file @ 276836d4
......@@ -683,9 +683,9 @@ nv40_grctx_init(struct nvkm_device *device, u32 *size)
nv40_grctx_generate(&ctx);
nv_wr32(device, 0x400324, 0);
nvkm_wr32(device, 0x400324, 0);
for (i = 0; i < ctx.ctxprog_len; i++)
nv_wr32(device, 0x400328, ctxprog[i]);
nvkm_wr32(device, 0x400328, ctxprog[i]);
*size = ctx.ctxvals_pos * 4;
kfree(ctxprog);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
View file @ 276836d4
......@@ -276,9 +276,9 @@ nv50_grctx_init(struct nvkm_device *device, u32 *size)
return -ENOMEM;
nv50_grctx_generate(&ctx);
nv_wr32(device, 0x400324, 0);
nvkm_wr32(device, 0x400324, 0);
for (i = 0; i < ctx.ctxprog_len; i++)
nv_wr32(device, 0x400328, ctxprog[i]);
nvkm_wr32(device, 0x400328, ctxprog[i]);
*size = ctx.ctxvals_pos * 4;
kfree(ctxprog);
return 0;
......@@ -298,7 +298,7 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx)
struct nvkm_device *device = ctx->device;
int i, j;
int offset, base;
u32 units = nv_rd32 (ctx->device, 0x1540);
u32 units = nvkm_rd32(device, 0x1540);
/* 0800: DISPATCH */
cp_ctx(ctx, 0x400808, 7);
......@@ -1189,7 +1189,7 @@ nv50_gr_construct_xfer1(struct nvkm_grctx *ctx)
int i;
int offset;
int size = 0;
u32 units = nv_rd32 (ctx->device, 0x1540);
u32 units = nvkm_rd32(device, 0x1540);
offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
ctx->ctxvals_base = offset;
......@@ -3272,7 +3272,7 @@ nv50_gr_construct_xfer2(struct nvkm_grctx *ctx)
struct nvkm_device *device = ctx->device;
int i;
u32 offset;
u32 units = nv_rd32 (ctx->device, 0x1540);
u32 units = nvkm_rd32(device, 0x1540);
int size = 0;
offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View file @ 276836d4
......@@ -197,7 +197,8 @@ gk104_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
struct gf100_gr *gr = (void *)object;
struct nvkm_pmu *pmu = nvkm_pmu(gr);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_pmu *pmu = device->pmu;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
......@@ -211,18 +212,18 @@ gk104_gr_init(struct nvkm_object *object)
if (ret)
return ret;
nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
gf100_gr_mmio(gr, oclass->mmio);
nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
......@@ -235,75 +236,75 @@ gk104_gr_init(struct nvkm_object *object)
data[i / 8] |= tpc << ((i % 8) * 4);
}
nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
nv_wr32(gr, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400500, 0x00010001);
nv_wr32(gr, 0x400100, 0xffffffff);
nv_wr32(gr, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nv_wr32(gr, 0x409ffc, 0x00000000);
nv_wr32(gr, 0x409c14, 0x00003e3e);
nv_wr32(gr, 0x409c24, 0x000f0001);
nv_wr32(gr, 0x404000, 0xc0000000);
nv_wr32(gr, 0x404600, 0xc0000000);
nv_wr32(gr, 0x408030, 0xc0000000);
nv_wr32(gr, 0x404490, 0xc0000000);
nv_wr32(gr, 0x406018, 0xc0000000);
nv_wr32(gr, 0x407020, 0x40000000);
nv_wr32(gr, 0x405840, 0xc0000000);
nv_wr32(gr, 0x405844, 0x00ffffff);
nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000);
nvkm_wr32(device, 0x409ffc, 0x00000000);
nvkm_wr32(device, 0x409c14, 0x00003e3e);
nvkm_wr32(device, 0x409c24, 0x000f0001);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nv_wr32(gr, GPC_UNIT(gpc, 0x3038), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
for (rop = 0; rop < gr->rop_nr; rop++) {
nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000);
nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000);
nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
}
nv_wr32(gr, 0x400108, 0xffffffff);
nv_wr32(gr, 0x400138, 0xffffffff);
nv_wr32(gr, 0x400118, 0xffffffff);
nv_wr32(gr, 0x400130, 0xffffffff);
nv_wr32(gr, 0x40011c, 0xffffffff);
nv_wr32(gr, 0x400134, 0xffffffff);
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
nv_wr32(gr, 0x400054, 0x34ce3464);
nvkm_wr32(device, 0x400054, 0x34ce3464);
gf100_gr_zbc_init(gr);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View file @ 276836d4
......@@ -236,8 +236,9 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
static void
gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
nv_wr32(gr, 0x419e44, 0x1ffffe);
nv_wr32(gr, 0x419e4c, 0x7f);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x419e44, 0x1ffffe);
nvkm_wr32(device, 0x419e4c, 0x7f);
}
int
......@@ -245,6 +246,7 @@ gk20a_gr_init(struct nvkm_object *object)
{
struct gk20a_gr_oclass *oclass = (void *)object->oclass;
struct gf100_gr *gr = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
......@@ -256,7 +258,7 @@ gk20a_gr_init(struct nvkm_object *object)
return ret;
/* Clear SCC RAM */
nv_wr32(gr, 0x40802c, 0x1);
nvkm_wr32(device, 0x40802c, 0x1);
gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
......@@ -269,14 +271,14 @@ gk20a_gr_init(struct nvkm_object *object)
return ret;
/* MMU debug buffer */
nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8);
nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8);
nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8);
nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8);
if (oclass->init_gpc_mmu)
oclass->init_gpc_mmu(gr);
/* Set the PE as stream master */
nv_mask(gr, 0x503018, 0x1, 0x1);
nvkm_mask(device, 0x503018, 0x1, 0x1);
/* Zcull init */
memset(data, 0x00, sizeof(data));
......@@ -290,49 +292,49 @@ gk20a_gr_init(struct nvkm_object *object)
data[i / 8] |= tpc << ((i % 8) * 4);
}
nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
/* Enable FIFO access */
nv_wr32(gr, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400500, 0x00010001);
/* Enable interrupts */
nv_wr32(gr, 0x400100, 0xffffffff);
nv_wr32(gr, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
/* Enable FECS error interrupts */
nv_wr32(gr, 0x409c24, 0x000f0000);
nvkm_wr32(device, 0x409c24, 0x000f0000);
/* Enable hardware warning exceptions */
nv_wr32(gr, 0x404000, 0xc0000000);
nv_wr32(gr, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
if (oclass->set_hww_esr_report_mask)
oclass->set_hww_esr_report_mask(gr);
/* Enable TPC exceptions per GPC */
nv_wr32(gr, 0x419d0c, 0x2);
nv_wr32(gr, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
nvkm_wr32(device, 0x419d0c, 0x2);
nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
/* Reset and enable all exceptions */
nv_wr32(gr, 0x400108, 0xffffffff);
nv_wr32(gr, 0x400138, 0xffffffff);
nv_wr32(gr, 0x400118, 0xffffffff);
nv_wr32(gr, 0x400130, 0xffffffff);
nv_wr32(gr, 0x40011c, 0xffffffff);
nv_wr32(gr, 0x400134, 0xffffffff);
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
gf100_gr_zbc_init(gr);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View file @ 276836d4
......@@ -304,7 +304,8 @@ gm107_gr_init_bios(struct gf100_gr *gr)
{ 0x419af0, 0x419af4 },
{ 0x419af8, 0x419afc },
};
struct nvkm_bios *bios = nvkm_bios(gr);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_bios *bios = device->bios;
struct nvbios_P0260E infoE;
struct nvbios_P0260X infoX;
int E = -1, X;
......@@ -312,9 +313,9 @@ gm107_gr_init_bios(struct gf100_gr *gr)
while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
if (X = -1, E < ARRAY_SIZE(regs)) {
nv_wr32(gr, regs[E].ctrl, infoE.data);
nvkm_wr32(device, regs[E].ctrl, infoE.data);
while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
nv_wr32(gr, regs[E].data, infoX.data);
nvkm_wr32(device, regs[E].data, infoX.data);
}
}
}
......@@ -324,6 +325,7 @@ gm107_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
struct gf100_gr *gr = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
......@@ -334,17 +336,17 @@ gm107_gr_init(struct nvkm_object *object)
if (ret)
return ret;
nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000);
nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8);
gf100_gr_mmio(gr, oclass->mmio);
gm107_gr_init_bios(gr);
nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
......@@ -357,75 +359,75 @@ gm107_gr_init(struct nvkm_object *object)
data[i / 8] |= tpc << ((i % 8) * 4);
}
nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
nv_wr32(gr, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400500, 0x00010001);
nv_wr32(gr, 0x400100, 0xffffffff);
nv_wr32(gr, 0x40013c, 0xffffffff);
nv_wr32(gr, 0x400124, 0x00000002);
nv_wr32(gr, 0x409c24, 0x000e0000);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000e0000);
nv_wr32(gr, 0x404000, 0xc0000000);
nv_wr32(gr, 0x404600, 0xc0000000);
nv_wr32(gr, 0x408030, 0xc0000000);
nv_wr32(gr, 0x404490, 0xc0000000);
nv_wr32(gr, 0x406018, 0xc0000000);
nv_wr32(gr, 0x407020, 0x40000000);
nv_wr32(gr, 0x405840, 0xc0000000);
nv_wr32(gr, 0x405844, 0x00ffffff);
nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++)
nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
}
nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
for (rop = 0; rop < gr->rop_nr; rop++) {
nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000);
nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000);
nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
}
nv_wr32(gr, 0x400108, 0xffffffff);
nv_wr32(gr, 0x400138, 0xffffffff);
nv_wr32(gr, 0x400118, 0xffffffff);
nv_wr32(gr, 0x400130, 0xffffffff);
nv_wr32(gr, 0x40011c, 0xffffffff);
nv_wr32(gr, 0x400134, 0xffffffff);
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
nv_wr32(gr, 0x400054, 0x2c350f63);
nvkm_wr32(device, 0x400054, 0x2c350f63);
gf100_gr_zbc_init(gr);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c
View file @ 276836d4
......@@ -253,6 +253,7 @@ gm204_gr_init(struct nvkm_object *object)
{
struct gf100_gr_oclass *oclass = (void *)object->oclass;
struct gf100_gr *gr = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
......@@ -264,24 +265,24 @@ gm204_gr_init(struct nvkm_object *object)
if (ret)
return ret;
tmp = nv_rd32(gr, 0x100c80); /*XXX: mask? */
nv_wr32(gr, 0x418880, 0x00001000 | (tmp & 0x00000fff));
nv_wr32(gr, 0x418890, 0x00000000);
nv_wr32(gr, 0x418894, 0x00000000);
nv_wr32(gr, 0x4188b4, gr->unk4188b4->addr >> 8);
nv_wr32(gr, 0x4188b8, gr->unk4188b8->addr >> 8);
nv_mask(gr, 0x4188b0, 0x00040000, 0x00040000);
tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */
nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff));
nvkm_wr32(device, 0x418890, 0x00000000);
nvkm_wr32(device, 0x418894, 0x00000000);
nvkm_wr32(device, 0x4188b4, gr->unk4188b4->addr >> 8);
nvkm_wr32(device, 0x4188b8, gr->unk4188b8->addr >> 8);
nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000);
/*XXX: belongs in fb */
nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8);
nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8);
nv_mask(gr, 0x100cc4, 0x00040000, 0x00040000);
nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8);
nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8);
nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000);
gf100_gr_mmio(gr, oclass->mmio);
gm107_gr_init_bios(gr);
nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001);
nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
memset(data, 0x00, sizeof(data));
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
......@@ -294,76 +295,76 @@ gm204_gr_init(struct nvkm_object *object)
data[i / 8] |= tpc << ((i % 8) * 4);
}
nv_wr32(gr, GPC_BCAST(0x0980), data[0]);
nv_wr32(gr, GPC_BCAST(0x0984), data[1]);
nv_wr32(gr, GPC_BCAST(0x0988), data[2]);
nv_wr32(gr, GPC_BCAST(0x098c), data[3]);
nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nv_wr32(gr, GPC_UNIT(gpc, 0x0914),
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 |
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918);
nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800));
nv_wr32(gr, GPC_BCAST(0x033c), nv_rd32(gr, 0x100804));
nv_wr32(gr, 0x400500, 0x00010001);
nv_wr32(gr, 0x400100, 0xffffffff);
nv_wr32(gr, 0x40013c, 0xffffffff);
nv_wr32(gr, 0x400124, 0x00000002);
nv_wr32(gr, 0x409c24, 0x000e0000);
nv_wr32(gr, 0x405848, 0xc0000000);
nv_wr32(gr, 0x40584c, 0x00000001);
nv_wr32(gr, 0x404000, 0xc0000000);
nv_wr32(gr, 0x404600, 0xc0000000);
nv_wr32(gr, 0x408030, 0xc0000000);
nv_wr32(gr, 0x404490, 0xc0000000);
nv_wr32(gr, 0x406018, 0xc0000000);
nv_wr32(gr, 0x407020, 0x40000000);
nv_wr32(gr, 0x405840, 0xc0000000);
nv_wr32(gr, 0x405844, 0x00ffffff);
nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008);
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000e0000);
nvkm_wr32(device, 0x405848, 0xc0000000);
nvkm_wr32(device, 0x40584c, 0x00000001);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x407020, 0x40000000);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++)
nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000);
nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
}
nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
for (rop = 0; rop < gr->rop_nr; rop++) {
nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000);
nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000);
nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff);
nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
}
nv_wr32(gr, 0x400108, 0xffffffff);
nv_wr32(gr, 0x400138, 0xffffffff);
nv_wr32(gr, 0x400118, 0xffffffff);
nv_wr32(gr, 0x400130, 0xffffffff);
nv_wr32(gr, 0x40011c, 0xffffffff);
nv_wr32(gr, 0x400134, 0xffffffff);
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
nv_wr32(gr, 0x400054, 0x2c350f63);
nvkm_wr32(device, 0x400054, 0x2c350f63);
gf100_gr_zbc_init(gr);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
View file @ 276836d4
......@@ -37,32 +37,34 @@ gm20b_gr_sclass[] = {
static void
gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 val;
/* TODO this needs to be removed once secure boot works */
if (1) {
nv_wr32(gr, 0x100ce4, 0xffffffff);
nvkm_wr32(device, 0x100ce4, 0xffffffff);
}
/* TODO update once secure boot works */
val = nv_rd32(gr, 0x100c80);
val = nvkm_rd32(device, 0x100c80);
val &= 0xf000087f;
nv_wr32(gr, 0x418880, val);
nv_wr32(gr, 0x418890, 0);
nv_wr32(gr, 0x418894, 0);
nvkm_wr32(device, 0x418880, val);
nvkm_wr32(device, 0x418890, 0);
nvkm_wr32(device, 0x418894, 0);
nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4));
nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8));
nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc));
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800));
nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
}
static void
gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
nv_wr32(gr, 0x419e44, 0xdffffe);
nv_wr32(gr, 0x419e4c, 0x5);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x419e44, 0xdffffe);
nvkm_wr32(device, 0x419e4c, 0x5);
}
struct nvkm_oclass *
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View file @ 276836d4
......@@ -446,7 +446,8 @@ static void
nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value)
{
struct nv04_gr *gr = (void *)object->engine;
int subc = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
struct nvkm_device *device = gr->base.engine.subdev.device;
int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
u32 tmp;
tmp = nv_ro32(object, 0x00);
......@@ -454,8 +455,8 @@ nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value)
tmp |= value;
nv_wo32(object, 0x00, tmp);
nv_wr32(gr, NV04_PGRAPH_CTX_SWITCH1, tmp);
nv_wr32(gr, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp);
nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
}
static void
......@@ -528,6 +529,7 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
struct nv04_gr *gr = (void *)object->engine;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
......@@ -539,8 +541,8 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd,
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nv_wr32(gr, 0x40053c, min);
nv_wr32(gr, 0x400544, max);
nvkm_wr32(device, 0x40053c, min);
nvkm_wr32(device, 0x400544, max);
return 0;
}
......@@ -549,6 +551,7 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
struct nv04_gr *gr = (void *)object->engine;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data = *(u32 *)args;
u32 min = data & 0xffff, max;
u32 w = data >> 16;
......@@ -560,8 +563,8 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd,
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nv_wr32(gr, 0x400540, min);
nv_wr32(gr, 0x400548, max);
nvkm_wr32(device, 0x400540, min);
nvkm_wr32(device, 0x400548, max);
return 0;
}
......@@ -1033,9 +1036,10 @@ nv04_gr_sclass[] = {
static struct nv04_gr_chan *
nv04_gr_channel(struct nv04_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv04_gr_chan *chan = NULL;
if (nv_rd32(gr, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
int chid = nv_rd32(gr, NV04_PGRAPH_CTX_USER) >> 24;
if (nvkm_rd32(device, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24;
if (chid < ARRAY_SIZE(gr->chan))
chan = gr->chan[chid];
}
......@@ -1046,14 +1050,15 @@ static int
nv04_gr_load_context(struct nv04_gr_chan *chan, int chid)
{
struct nv04_gr *gr = nv04_gr(chan);
struct nvkm_device *device = gr->base.engine.subdev.device;
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
nv_wr32(gr, nv04_gr_ctx_regs[i], chan->nv04[i]);
nvkm_wr32(device, nv04_gr_ctx_regs[i], chan->nv04[i]);
nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
nv_mask(gr, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
nvkm_mask(device, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
return 0;
}
......@@ -1061,19 +1066,21 @@ static int
nv04_gr_unload_context(struct nv04_gr_chan *chan)
{
struct nv04_gr *gr = nv04_gr(chan);
struct nvkm_device *device = gr->base.engine.subdev.device;
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
chan->nv04[i] = nv_rd32(gr, nv04_gr_ctx_regs[i]);
chan->nv04[i] = nvkm_rd32(device, nv04_gr_ctx_regs[i]);
nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
return 0;
}
static void
nv04_gr_context_switch(struct nv04_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv04_gr_chan *prev = NULL;
struct nv04_gr_chan *next = NULL;
unsigned long flags;
......@@ -1088,7 +1095,7 @@ nv04_gr_context_switch(struct nv04_gr *gr)
nv04_gr_unload_context(prev);
/* load context for next channel */
chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
next = gr->chan[chid];
if (next)
nv04_gr_load_context(next, chid);
......@@ -1161,13 +1168,14 @@ nv04_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_gr *gr = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (nv04_gr_channel(gr) == chan)
nv04_gr_unload_context(chan);
nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&gr->lock, flags);
return nvkm_object_fini(&chan->base, suspend);
......@@ -1192,6 +1200,7 @@ bool
nv04_gr_idle(void *obj)
{
struct nvkm_gr *gr = nvkm_gr(obj);
struct nvkm_device *device = gr->engine.subdev.device;
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
......@@ -1199,7 +1208,7 @@ nv04_gr_idle(void *obj)
if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) {
nv_error(gr, "idle timed out with status 0x%08x\n",
nv_rd32(gr, NV04_PGRAPH_STATUS));
nvkm_rd32(device, NV04_PGRAPH_STATUS));
return false;
}
......@@ -1252,16 +1261,17 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
struct nv04_gr_chan *chan = NULL;
struct nvkm_namedb *namedb = NULL;
struct nvkm_handle *handle = NULL;
u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS);
u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR);
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x0f000000) >> 24;
u32 subc = (addr & 0x0000e000) >> 13;
u32 mthd = (addr & 0x00001ffc);
u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nv_rd32(gr, 0x400180 + subc * 4) & 0xff;
u32 inst = (nv_rd32(gr, 0x40016c) & 0xffff) << 4;
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff;
u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4;
u32 show = stat;
unsigned long flags;
......@@ -1280,14 +1290,14 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
}
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
nv04_gr_context_switch(gr);
}
nv_wr32(gr, NV03_PGRAPH_INTR, stat);
nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001);
nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
......@@ -1332,6 +1342,7 @@ nv04_gr_init(struct nvkm_object *object)
{
struct nvkm_engine *engine = nv_engine(object);
struct nv04_gr *gr = (void *)engine;
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret;
ret = nvkm_gr_init(&gr->base);
......@@ -1339,33 +1350,33 @@ nv04_gr_init(struct nvkm_object *object)
return ret;
/* Enable PGRAPH interrupts */
nv_wr32(gr, NV03_PGRAPH_INTR, 0xFFFFFFFF);
nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nv_wr32(gr, NV04_PGRAPH_VALID1, 0);
nv_wr32(gr, NV04_PGRAPH_VALID2, 0);
/*nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x000001FF);
nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x1231c000);
nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_VALID1, 0);
nvkm_wr32(device, NV04_PGRAPH_VALID2, 0);
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000);
/*1231C000 blob, 001 haiku*/
/*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x72111100);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100);
/*0x72111100 blob , 01 haiku*/
/*nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
/*haiku same*/
/*nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
/*haiku and blob 10d4*/
nv_wr32(gr, NV04_PGRAPH_STATE , 0xFFFFFFFF);
nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
/* These don't belong here, they're part of a per-channel context */
nv_wr32(gr, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
nv_wr32(gr, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
View file @ 276836d4
......@@ -153,67 +153,68 @@ nv30_gr_init(struct nvkm_object *object)
{
struct nvkm_engine *engine = nv_engine(object);
struct nv20_gr *gr = (void *)engine;
struct nvkm_fb *fb = nvkm_fb(object);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
int ret, i;
ret = nvkm_gr_init(&gr->base);
if (ret)
return ret;
nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000);
nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0);
nv_wr32(gr, 0x400890, 0x01b463ff);
nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000);
nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
nv_wr32(gr, 0x400B80, 0x1003d888);
nv_wr32(gr, 0x400B84, 0x0c000000);
nv_wr32(gr, 0x400098, 0x00000000);
nv_wr32(gr, 0x40009C, 0x0005ad00);
nv_wr32(gr, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
nv_wr32(gr, 0x4000a0, 0x00000000);
nv_wr32(gr, 0x4000a4, 0x00000008);
nv_wr32(gr, 0x4008a8, 0xb784a400);
nv_wr32(gr, 0x400ba0, 0x002f8685);
nv_wr32(gr, 0x400ba4, 0x00231f3f);
nv_wr32(gr, 0x4008a4, 0x40000020);
nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4);
nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
nvkm_wr32(device, 0x400890, 0x01b463ff);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
nvkm_wr32(device, 0x400B80, 0x1003d888);
nvkm_wr32(device, 0x400B84, 0x0c000000);
nvkm_wr32(device, 0x400098, 0x00000000);
nvkm_wr32(device, 0x40009C, 0x0005ad00);
nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
nvkm_wr32(device, 0x4000a0, 0x00000000);
nvkm_wr32(device, 0x4000a4, 0x00000008);
nvkm_wr32(device, 0x4008a8, 0xb784a400);
nvkm_wr32(device, 0x400ba0, 0x002f8685);
nvkm_wr32(device, 0x400ba4, 0x00231f3f);
nvkm_wr32(device, 0x4008a4, 0x40000020);
if (nv_device(gr)->chipset == 0x34) {
nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00200201);
nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000008);
nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000032);
nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000002);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002);
}
nv_wr32(gr, 0x4000c0, 0x00000016);
nvkm_wr32(device, 0x4000c0, 0x00000016);
/* Turn all the tiling regions off. */
for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i);
nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF);
nv_wr32(gr, 0x0040075c , 0x00000001);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
nvkm_wr32(device, 0x0040075c , 0x00000001);
/* begin RAM config */
/* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200));
nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204));
nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
if (nv_device(gr)->chipset != 0x34) {
nv_wr32(gr, 0x400750, 0x00EA0000);
nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100200));
nv_wr32(gr, 0x400750, 0x00EA0004);
nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100204));
nvkm_wr32(device, 0x400750, 0x00EA0000);
nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x400750, 0x00EA0004);
nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204));
}
return 0;
}
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7