Commit 401d0069 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'fbdev-for-linus' of git://github.com/schandinat/linux-2.6

* 'fbdev-for-linus' of git://github.com/schandinat/linux-2.6:
  viafb: correct sync polarity for OLPC DCON
  video:da8xx-fb: Disable and reset sequence on version2 of LCDC
  OMAPDSS: DISPC: skip scaling calculations when not scaling
  OMAPFB: fix compilation warnings due to missing include
  OMAPDSS: HDMI: fix returned HDMI pixel clock
parents 06718f15 a3283969
...@@ -116,6 +116,7 @@ ...@@ -116,6 +116,7 @@
/* Clock registers available only on Version 2 */ /* Clock registers available only on Version 2 */
#define LCD_CLK_ENABLE_REG 0x6c #define LCD_CLK_ENABLE_REG 0x6c
#define LCD_CLK_RESET_REG 0x70 #define LCD_CLK_RESET_REG 0x70
#define LCD_CLK_MAIN_RESET BIT(3)
#define LCD_NUM_BUFFERS 2 #define LCD_NUM_BUFFERS 2
...@@ -244,6 +245,10 @@ static inline void lcd_enable_raster(void) ...@@ -244,6 +245,10 @@ static inline void lcd_enable_raster(void)
{ {
u32 reg; u32 reg;
/* Bring LCDC out of reset */
if (lcd_revision == LCD_VERSION_2)
lcdc_write(0, LCD_CLK_RESET_REG);
reg = lcdc_read(LCD_RASTER_CTRL_REG); reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (!(reg & LCD_RASTER_ENABLE)) if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
...@@ -257,6 +262,10 @@ static inline void lcd_disable_raster(void) ...@@ -257,6 +262,10 @@ static inline void lcd_disable_raster(void)
reg = lcdc_read(LCD_RASTER_CTRL_REG); reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (reg & LCD_RASTER_ENABLE) if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
if (lcd_revision == LCD_VERSION_2)
/* Write 1 to reset LCDC */
lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
} }
static void lcd_blit(int load_mode, struct da8xx_fb_par *par) static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
...@@ -584,8 +593,12 @@ static void lcd_reset(struct da8xx_fb_par *par) ...@@ -584,8 +593,12 @@ static void lcd_reset(struct da8xx_fb_par *par)
lcdc_write(0, LCD_DMA_CTRL_REG); lcdc_write(0, LCD_DMA_CTRL_REG);
lcdc_write(0, LCD_RASTER_CTRL_REG); lcdc_write(0, LCD_RASTER_CTRL_REG);
if (lcd_revision == LCD_VERSION_2) if (lcd_revision == LCD_VERSION_2) {
lcdc_write(0, LCD_INT_ENABLE_SET_REG); lcdc_write(0, LCD_INT_ENABLE_SET_REG);
/* Write 1 to reset */
lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
lcdc_write(0, LCD_CLK_RESET_REG);
}
} }
static void lcd_calc_clk_divider(struct da8xx_fb_par *par) static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
......
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
......
...@@ -1720,12 +1720,11 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane, ...@@ -1720,12 +1720,11 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
unsigned long fclk = 0; unsigned long fclk = 0;
if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { if (width == out_width && height == out_height)
if (width != out_width || height != out_height) return 0;
return -EINVAL;
else if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
return 0; return -EINVAL;
}
if (out_width < width / maxdownscale || if (out_width < width / maxdownscale ||
out_width > width * 8) out_width > width * 8)
......
...@@ -269,7 +269,7 @@ static void update_hdmi_timings(struct hdmi_config *cfg, ...@@ -269,7 +269,7 @@ static void update_hdmi_timings(struct hdmi_config *cfg,
unsigned long hdmi_get_pixel_clock(void) unsigned long hdmi_get_pixel_clock(void)
{ {
/* HDMI Pixel Clock in Mhz */ /* HDMI Pixel Clock in Mhz */
return hdmi.ip_data.cfg.timings.timings.pixel_clock * 10000; return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000;
} }
static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
......
...@@ -559,8 +559,8 @@ ...@@ -559,8 +559,8 @@
#define M1200X720_R60_VSP POSITIVE #define M1200X720_R60_VSP POSITIVE
/* 1200x900@60 Sync Polarity (DCON) */ /* 1200x900@60 Sync Polarity (DCON) */
#define M1200X900_R60_HSP NEGATIVE #define M1200X900_R60_HSP POSITIVE
#define M1200X900_R60_VSP NEGATIVE #define M1200X900_R60_VSP POSITIVE
/* 1280x600@60 Sync Polarity (GTF Mode) */ /* 1280x600@60 Sync Polarity (GTF Mode) */
#define M1280x600_R60_HSP NEGATIVE #define M1280x600_R60_HSP NEGATIVE
......
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