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Commit 69f1d1a6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc 

* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits)
  ARM: S5P64X0: External Interrupt Support
  ARM: EXYNOS4: Enable MFC on Samsung NURI
  ARM: EXYNOS4: Enable MFC on universal_c210
  ARM: S5PV210: Enable MFC on Goni
  ARM: S5P: Add support for MFC device
  ARM: EXYNOS4: Add support FIMD on SMDKC210
  ARM: EXYNOS4: Add platform device and helper functions for FIMD
  ARM: EXYNOS4: Add resource definition for FIMD
  ARM: EXYNOS4: Change devname for FIMD clkdev
  ARM: SAMSUNG: Add IRQ_I2S0 definition
  ARM: SAMSUNG: Add platform device for idma
  ARM: EXYNOS4: Add more registers to be saved and restored for PM
  ARM: EXYNOS4: Add more register addresses of CMU
  ARM: EXYNOS4: Add platform device for dwmci driver
  ARM: EXYNOS4: configure rtc-s3c on NURI
  ARM: EXYNOS4: configure MAX8903 secondary charger on NURI
  ARM: EXYNOS4: configure ADC on NURI
  ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI
  ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI
  ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs
  ...

Fix up tons of silly conflicts:
 - arch/arm/mach-davinci/include/mach/psc.h
 - arch/arm/mach-exynos4/Kconfig
 - arch/arm/mach-exynos4/mach-smdkc210.c
 - arch/arm/mach-exynos4/pm.c
 - arch/arm/mach-imx/mm-imx1.c
 - arch/arm/mach-imx/mm-imx21.c
 - arch/arm/mach-imx/mm-imx25.c
 - arch/arm/mach-imx/mm-imx27.c
 - arch/arm/mach-imx/mm-imx31.c
 - arch/arm/mach-imx/mm-imx35.c
 - arch/arm/mach-mx5/mm.c
 - arch/arm/mach-s5pv210/mach-goni.c
 - arch/arm/mm/Kconfig
parents 2d86a3f0 1e09939b
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Showing with 4530 additions and 1133 deletions
arch/arm/Kconfig
View file @ 69f1d1a6
......@@ -328,7 +328,7 @@ config ARCH_CLPS711X
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
select CPU_V6
select CPU_V6K
select GENERIC_CLOCKEVENTS
select ARM_GIC
select MIGHT_HAVE_PCI
......@@ -396,6 +396,7 @@ config ARCH_MXC
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
help
Support for Freescale MXC/iMX-based family of processors
......@@ -603,7 +604,6 @@ config ARCH_TEGRA
select GENERIC_GPIO
select HAVE_CLK
select HAVE_SCHED_CLOCK
select ARCH_HAS_BARRIERS if CACHE_L2X0
select ARCH_HAS_CPUFREQ
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
......@@ -630,6 +630,8 @@ config ARCH_PXA
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
select AUTO_ZRELADDR
select MULTI_IRQ_HANDLER
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
......@@ -768,6 +770,7 @@ config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
......@@ -786,6 +789,7 @@ config ARCH_EXYNOS4
bool "Samsung EXYNOS4"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
select CLKDEV_LOOKUP
......
arch/arm/common/gic.c
View file @ 69f1d1a6
......@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
/* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly;
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
/*
* Supported arch specific GIC irq extension.
* Default make them NULL.
......
arch/arm/configs/mxs_defconfig
View file @ 69f1d1a6
......@@ -22,6 +22,8 @@ CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXS=y
CONFIG_MACH_MX23EVK=y
CONFIG_MACH_MX28EVK=y
CONFIG_MACH_STMP378X_DEVB=y
CONFIG_MACH_TX28=y
# CONFIG_ARM_THUMB is not set
......
arch/arm/configs/u8500_defconfig
View file @ 69f1d1a6
......@@ -11,12 +11,12 @@ CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB5500=y
CONFIG_UX500_SOC_DB8500=y
CONFIG_MACH_U8500=y
CONFIG_MACH_SNOWBALL=y
CONFIG_MACH_U5500=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
......@@ -25,8 +25,13 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NETFILTER=y
CONFIG_PHONET=y
CONFIG_PHONET_PIPECTRLR=y
# CONFIG_WIRELESS is not set
CONFIG_CAIF=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
......@@ -35,6 +40,13 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_MISC_DEVICES=y
CONFIG_AB8500_PWM=y
CONFIG_SENSORS_BH1780=y
CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_SMSC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
......@@ -49,9 +61,9 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_AB8500_PONKEY=y
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_I2C=y
......@@ -64,14 +76,19 @@ CONFIG_GPIO_TC3589X=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_TC3589X=y
CONFIG_AB8500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AB8500=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_GADGET_MUSB_HDRC=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_GADGET=y
CONFIG_AB8500_USB=y
CONFIG_MMC=y
CONFIG_MMC_CLKGATE=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LP5521=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AB8500=y
......@@ -79,7 +96,6 @@ CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
CONFIG_STE_DMA40=y
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
......@@ -91,6 +107,8 @@ CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=m
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
......@@ -99,7 +117,5 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
arch/arm/include/asm/hardware/gic.h
View file @ 69f1d1a6
......@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
void gic_enable_ppi(unsigned int);
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
#endif
#endif
arch/arm/include/asm/irq.h
View file @ 69f1d1a6
......@@ -23,6 +23,7 @@ struct pt_regs;
extern void migrate_irqs(void);
extern void asm_do_IRQ(unsigned int, struct pt_regs *);
void handle_IRQ(unsigned int, struct pt_regs *);
void init_IRQ(void);
#endif
......
arch/arm/kernel/irq.c
View file @ 69f1d1a6
......@@ -67,12 +67,12 @@ int arch_show_interrupts(struct seq_file *p, int prec)
}
/*
* do_IRQ handles all hardware IRQ's. Decoded IRQs should not
* come via this function. Instead, they should provide their
* own 'handler'
* handle_IRQ handles all hardware IRQ's. Decoded IRQs should
* not come via this function. Instead, they should provide their
* own 'handler'. Used by platform code implementing C-based 1st
* level decoding.
*/
asmlinkage void __exception_irq_entry
asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
......@@ -97,6 +97,15 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
set_irq_regs(old_regs);
}
/*
* asm_do_IRQ is the interface to be used from assembly code.
*/
asmlinkage void __exception_irq_entry
asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
{
handle_IRQ(irq, regs);
}
void set_irq_flags(unsigned int irq, unsigned int iflags)
{
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
......
arch/arm/mach-cns3xxx/cns3420vb.c
View file @ 69f1d1a6
......@@ -169,6 +169,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = {
static void __init cns3420_init(void)
{
cns3xxx_l2x0_init();
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
cns3xxx_ahci_init();
......
arch/arm/mach-cns3xxx/core.c
View file @ 69f1d1a6
......@@ -16,6 +16,7 @@
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/cns3xxx.h>
#include "core.h"
......@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void)
struct sys_timer cns3xxx_timer = {
.init = cns3xxx_timer_init,
};
#ifdef CONFIG_CACHE_L2X0
void __init cns3xxx_l2x0_init(void)
{
void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
u32 val;
if (WARN_ON(!base))
return;
/*
* Tag RAM Control register
*
* bit[10:8] - 1 cycle of write accesses latency
* bit[6:4] - 1 cycle of read accesses latency
* bit[3:0] - 1 cycle of setup latency
*
* 1 cycle of latency for setup, read and write accesses
*/
val = readl(base + L2X0_TAG_LATENCY_CTRL);
val &= 0xfffff888;
writel(val, base + L2X0_TAG_LATENCY_CTRL);
/*
* Data RAM Control register
*
* bit[10:8] - 1 cycles of write accesses latency
* bit[6:4] - 1 cycles of read accesses latency
* bit[3:0] - 1 cycle of setup latency
*
* 1 cycle of latency for setup, read and write accesses
*/
val = readl(base + L2X0_DATA_LATENCY_CTRL);
val &= 0xfffff888;
writel(val, base + L2X0_DATA_LATENCY_CTRL);
/* 32 KiB, 8-way, parity disable */
l2x0_init(base, 0x00540000, 0xfe000fff);
}
#endif /* CONFIG_CACHE_L2X0 */
arch/arm/mach-cns3xxx/core.h
View file @ 69f1d1a6
......@@ -13,6 +13,12 @@
extern struct sys_timer cns3xxx_timer;
#ifdef CONFIG_CACHE_L2X0
void __init cns3xxx_l2x0_init(void);
#else
static inline void cns3xxx_l2x0_init(void) {}
#endif /* CONFIG_CACHE_L2X0 */
void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);
......
arch/arm/mach-davinci/board-da850-evm.c
View file @ 69f1d1a6
......@@ -1117,6 +1117,8 @@ static __init int da850_evm_init_cpufreq(void)
static __init int da850_evm_init_cpufreq(void) { return 0; }
#endif
#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
static __init void da850_evm_init(void)
{
int ret;
......@@ -1237,6 +1239,11 @@ static __init void da850_evm_init(void)
if (ret)
pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
ret);
ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
if (ret)
pr_warning("da850_evm_init: sata registration failed: %d\n",
ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
......
arch/arm/mach-davinci/clock.c
View file @ 69f1d1a6
......@@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
PSC_STATE_ENABLE);
true, clk->flags);
}
static void __clk_disable(struct clk *clk)
......@@ -54,8 +54,7 @@ static void __clk_disable(struct clk *clk)
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
(clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
(clk->flags & PSC_SWRSTDISABLE) ?
PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
false, clk->flags);
if (clk->parent)
__clk_disable(clk->parent);
}
......@@ -239,8 +238,7 @@ static int __init clk_disable_unused(void)
pr_debug("Clocks: disable unused %s\n", ck->name);
davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
(ck->flags & PSC_SWRSTDISABLE) ?
PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
false, ck->flags);
}
spin_unlock_irq(&clockfw_lock);
......
arch/arm/mach-davinci/clock.h
View file @ 69f1d1a6
......@@ -111,6 +111,7 @@ struct clk {
#define CLK_PLL BIT(4) /* PLL-derived clock */
#define PRE_PLL BIT(5) /* source is before PLL mult/div */
#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
#define PSC_FORCE BIT(7) /* Force module state transtition */
#define CLK(dev, con, ck) \
{ \
......
arch/arm/mach-davinci/da850.c
View file @ 69f1d1a6
......@@ -58,6 +58,7 @@ static struct pll_data pll0_data = {
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DA850_REF_FREQ,
.set_rate = davinci_simple_set_rate,
};
static struct clk pll0_clk = {
......@@ -373,6 +374,14 @@ static struct clk spi1_clk = {
.flags = DA850_CLK_ASYNC3,
};
static struct clk sata_clk = {
.name = "sata",
.parent = &pll0_sysclk2,
.lpsc = DA850_LPSC1_SATA,
.gpsc = 1,
.flags = PSC_FORCE,
};
static struct clk_lookup da850_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll0", &pll0_clk),
......@@ -419,6 +428,7 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("ahci", NULL, &sata_clk),
CLK(NULL, NULL, NULL),
};
......
arch/arm/mach-davinci/devices-da8xx.c
View file @ 69f1d1a6
......@@ -14,6 +14,8 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/ahci_platform.h>
#include <linux/clk.h>
#include <mach/cputype.h>
#include <mach/common.h>
......@@ -33,6 +35,7 @@
#define DA8XX_SPI0_BASE 0x01c41000
#define DA830_SPI1_BASE 0x01e12000
#define DA8XX_LCD_CNTRL_BASE 0x01e13000
#define DA850_SATA_BASE 0x01e18000
#define DA850_MMCSD1_BASE 0x01e1b000
#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
......@@ -842,3 +845,126 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
return platform_device_register(&da8xx_spi_device[instance]);
}
#ifdef CONFIG_ARCH_DAVINCI_DA850
static struct resource da850_sata_resources[] = {
{
.start = DA850_SATA_BASE,
.end = DA850_SATA_BASE + 0x1fff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA850_SATAINT,
.flags = IORESOURCE_IRQ,
},
};
/* SATA PHY Control Register offset from AHCI base */
#define SATA_P0PHYCR_REG 0x178
#define SATA_PHY_MPY(x) ((x) << 0)
#define SATA_PHY_LOS(x) ((x) << 6)
#define SATA_PHY_RXCDR(x) ((x) << 10)
#define SATA_PHY_RXEQ(x) ((x) << 13)
#define SATA_PHY_TXSWING(x) ((x) << 19)
#define SATA_PHY_ENPLL(x) ((x) << 31)
static struct clk *da850_sata_clk;
static unsigned long da850_sata_refclkpn;
/* Supported DA850 SATA crystal frequencies */
#define KHZ_TO_HZ(freq) ((freq) * 1000)
static unsigned long da850_sata_xtal[] = {
KHZ_TO_HZ(300000),
KHZ_TO_HZ(250000),
0, /* Reserved */
KHZ_TO_HZ(187500),
KHZ_TO_HZ(150000),
KHZ_TO_HZ(125000),
KHZ_TO_HZ(120000),
KHZ_TO_HZ(100000),
KHZ_TO_HZ(75000),
KHZ_TO_HZ(60000),
};
static int da850_sata_init(struct device *dev, void __iomem *addr)
{
int i, ret;
unsigned int val;
da850_sata_clk = clk_get(dev, NULL);
if (IS_ERR(da850_sata_clk))
return PTR_ERR(da850_sata_clk);
ret = clk_enable(da850_sata_clk);
if (ret)
goto err0;
/* Enable SATA clock receiver */
val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
val &= ~BIT(0);
__raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
/* Get the multiplier needed for 1.5GHz PLL output */
for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
if (da850_sata_xtal[i] == da850_sata_refclkpn)
break;
if (i == ARRAY_SIZE(da850_sata_xtal)) {
ret = -EINVAL;
goto err1;
}
val = SATA_PHY_MPY(i + 1) |
SATA_PHY_LOS(1) |
SATA_PHY_RXCDR(4) |
SATA_PHY_RXEQ(1) |
SATA_PHY_TXSWING(3) |
SATA_PHY_ENPLL(1);
__raw_writel(val, addr + SATA_P0PHYCR_REG);
return 0;
err1:
clk_disable(da850_sata_clk);
err0:
clk_put(da850_sata_clk);
return ret;
}
static void da850_sata_exit(struct device *dev)
{
clk_disable(da850_sata_clk);
clk_put(da850_sata_clk);
}
static struct ahci_platform_data da850_sata_pdata = {
.init = da850_sata_init,
.exit = da850_sata_exit,
};
static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
static struct platform_device da850_sata_device = {
.name = "ahci",
.id = -1,
.dev = {
.platform_data = &da850_sata_pdata,
.dma_mask = &da850_sata_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(da850_sata_resources),
.resource = da850_sata_resources,
};
int __init da850_register_sata(unsigned long refclkpn)
{
da850_sata_refclkpn = refclkpn;
if (!da850_sata_refclkpn)
return -EINVAL;
return platform_device_register(&da850_sata_device);
}
#endif
arch/arm/mach-davinci/include/mach/da8xx.h
View file @ 69f1d1a6
......@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed;
#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
#define DA8XX_DEEPSLEEP_REG 0x8
#define DA8XX_PWRDN_REG 0x18
#define DA8XX_PSC0_BASE 0x01c10000
#define DA8XX_PLL0_BASE 0x01c11000
......@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem * __init da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev);
int __init da850_register_sata(unsigned long refclkpn);
extern struct platform_device da8xx_serial_device;
extern struct emac_platform_data da8xx_emac_pdata;
......
arch/arm/mach-davinci/include/mach/psc.h
View file @ 69f1d1a6
......@@ -244,12 +244,13 @@
#define PSC_STATE_ENABLE 3
#define MDSTAT_STATE_MASK 0x1f
#define MDCTL_FORCE BIT(31)
#ifndef __ASSEMBLER__
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, u32 next_state);
unsigned int id, bool enable, u32 flags);
#endif
......
arch/arm/mach-davinci/psc.c
View file @ 69f1d1a6
......@@ -25,6 +25,8 @@
#include <mach/cputype.h>
#include <mach/psc.h>
#include "clock.h"
/* Return nonzero iff the domain's clock is active */
int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
{
......@@ -48,11 +50,12 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, u32 next_state)
unsigned int id, bool enable, u32 flags)
{
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
void __iomem *psc_base;
struct davinci_soc_info *soc_info = &davinci_soc_info;
u32 next_state = PSC_STATE_ENABLE;
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
......@@ -62,9 +65,18 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
if (!enable) {
if (flags & PSC_SWRSTDISABLE)
next_state = PSC_STATE_SWRSTDISABLE;
else
next_state = PSC_STATE_DISABLE;
}
mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
mdctl &= ~MDSTAT_STATE_MASK;
mdctl |= next_state;
if (flags & PSC_FORCE)
mdctl |= MDCTL_FORCE;
__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
pdstat = __raw_readl(psc_base + PDSTAT);
......
arch/arm/mach-exynos4/Kconfig
View file @ 69f1d1a6
......@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
Enable EXYNOS4210 CPU support
config EXYNOS4_MCT
bool "Kernel timer support by MCT"
bool
default y
help
Use MCT (Multi Core Timer) as kernel timers
......@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
config EXYNOS4_SETUP_FIMD0
bool
help
Common setup code for FIMD0.
config EXYNOS4_DEV_PD
bool
help
......@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
help
Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_DEV_DWMCI
bool
help
Compile in platform device definitions for DWMCI
config EXYNOS4_SETUP_I2C1
bool
help
......@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
......@@ -114,6 +126,7 @@ config MACH_SMDKC210
select SAMSUNG_DEV_BACKLIGHT
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
......@@ -122,6 +135,7 @@ config MACH_SMDKC210
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
......@@ -130,10 +144,12 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_BACKLIGHT
select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD
select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
......@@ -157,13 +173,22 @@ config MACH_ARMLEX4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210
select S5P_GPIO_INT
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
select S5P_DEV_FIMC3
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_ONENAND
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help
......@@ -180,13 +205,16 @@ config MACH_NURI
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_ADC
help
Machine support for Samsung Mobile NURI Board.
......
arch/arm/mach-exynos4/Makefile
View file @ 69f1d1a6
......@@ -13,18 +13,13 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y)
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_EXYNOS4_MCT) += mct.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
......@@ -42,8 +37,10 @@ obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
......
arch/arm/mach-exynos4/clock.c
View file @ 69f1d1a6
......@@ -527,6 +527,11 @@ static struct clk init_clocks_off[] = {
.name = "fimg2d",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "mfc",
.devname = "s5p-mfc",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.0",
......@@ -731,6 +736,52 @@ static struct clksrc_sources clkset_mout_g2d = {
.nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
};
static struct clk *clkset_mout_mfc0_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_mfc0 = {
.sources = clkset_mout_mfc0_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
};
static struct clksrc_clk clk_mout_mfc0 = {
.clk = {
.name = "mout_mfc0",
},
.sources = &clkset_mout_mfc0,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
};
static struct clk *clkset_mout_mfc1_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_sclk_vpll.clk,
};
static struct clksrc_sources clkset_mout_mfc1 = {
.sources = clkset_mout_mfc1_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
};
static struct clksrc_clk clk_mout_mfc1 = {
.clk = {
.name = "mout_mfc1",
},
.sources = &clkset_mout_mfc1,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
};
static struct clk *clkset_mout_mfc_list[] = {
[0] = &clk_mout_mfc0.clk,
[1] = &clk_mout_mfc1.clk,
};
static struct clksrc_sources clkset_mout_mfc = {
.sources = clkset_mout_mfc_list,
.nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
};
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
......@@ -972,6 +1023,14 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mfc",
.devname = "s5p-mfc",
},
.sources = &clkset_mout_mfc,
.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
......@@ -1049,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
&clk_dout_mmc2,
&clk_dout_mmc3,
&clk_dout_mmc4,
&clk_mout_mfc0,
&clk_mout_mfc1,
};
static int xtal_rate;
......
arch/arm/mach-exynos4/cpu.c
View file @ 69f1d1a6
......@@ -16,12 +16,16 @@
#include <asm/proc-fns.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/adc-core.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
......@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
}
}, {
.virtual = (unsigned long)S5P_VA_GIC_CPU,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GIC_DIST,
.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
.length = SZ_64K,
.type = MT_DEVICE,
},
};
static void exynos4_idle(void)
......@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
......@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
}
void __init exynos4_init_clocks(int xtal)
......@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
static void exynos4_gic_irq_eoi(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
}
void __init exynos4_init_irq(void)
{
int irq;
gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
/*
* From SPI(0) to SPI(39) and SPI(51), SPI(53) are
* connected to the interrupt combiner. These irqs
* should be initialized to support cascade interrupt.
*/
if ((irq >= 40) && !(irq == 51) && !(irq == 53))
continue;
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
......
arch/arm/mach-exynos4/dev-audio.c
View file @ 69f1d1a6
......@@ -21,6 +21,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
......@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
},
},
};
......
arch/arm/mach-exynos4/dev-dwmci.c 0 → 100644
View file @ 69f1d1a6
/*
* linux/arch/arm/mach-exynos4/dev-dwmci.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Platform device for Synopsys DesignWare Mobile Storage IP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
#include <mach/map.h>
static int exynos4_dwmci_get_bus_wd(u32 slot_id)
{
return 4;
}
static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
{
return 0;
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
};
static struct dw_mci_board exynos4_dwci_pdata = {
.num_slots = 1,
.quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
.bus_hz = 80 * 1000 * 1000,
.detect_delay_ms = 200,
.init = exynos4_dwmci_init,
.get_bus_wd = exynos4_dwmci_get_bus_wd,
};
static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
struct platform_device exynos4_device_dwmci = {
.name = "dw_mmc",
.id = -1,
.num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
.resource = exynos4_dwmci_resource,
.dev = {
.dma_mask = &exynos4_dwmci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &exynos4_dwci_pdata,
},
};
void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
{
struct dw_mci_board *npd;
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
&exynos4_device_dwmci);
if (!npd->init)
npd->init = exynos4_dwmci_init;
if (!npd->get_bus_wd)
npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
}
arch/arm/mach-exynos4/hotplug.c
View file @ 69f1d1a6
......@@ -13,9 +13,12 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <mach/regs-pmu.h>
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void)
......@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
/*
* there is no power-control hardware on this platform, so all
* we can do is put the core into WFI; this is safe as the calling
* code will have already disabled interrupts
*/
for (;;) {
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
/*
* here's the WFI
*/
......
arch/arm/mach-exynos4/localtimer.c → arch/arm/mach-exynos4/include/mach/dwmci.h
View file @ 69f1d1a6
/* linux/arch/arm/mach-exynos4/localtimer.c
/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
*
* Cloned from linux/arch/arm/mach-realview/localtimer.c
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
* Synopsys DesignWare Mobile Storage for EXYNOS4210
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#include <linux/clockchips.h>
#ifndef __ASM_ARM_ARCH_DWMCI_H
#define __ASM_ARM_ARCH_DWMCI_H __FILE__
#include <asm/irq.h>
#include <asm/localtimer.h>
#include <linux/mmc/dw_mmc.h>
/*
* Setup the local clock events for a CPU.
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
}
extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
#endif /* __ASM_ARM_ARCH_DWMCI_H */
arch/arm/mach-exynos4/include/mach/entry-macro.S
View file @ 69f1d1a6
......@@ -10,6 +10,7 @@
*/
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/hardware/gic.h>
.macro disable_fiq
......@@ -18,6 +19,10 @@
.macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
mrc p15, 0, \tmp, c0, c0, 5
and \tmp, \tmp, #3
cmp \tmp, #1
addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
.endm
.macro arch_ret_to_user, tmp1, tmp2
......@@ -75,10 +80,4 @@
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #29
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
arch/arm/mach-exynos4/include/mach/irqs.h
View file @ 69f1d1a6
......@@ -19,40 +19,105 @@
#define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_MCT1 IRQ_SPI(35)
#define IRQ_EINT0 IRQ_SPI(40)
#define IRQ_EINT1 IRQ_SPI(41)
#define IRQ_EINT2 IRQ_SPI(42)
#define IRQ_EINT3 IRQ_SPI(43)
#define IRQ_USB_HSOTG IRQ_SPI(44)
#define IRQ_USB_HOST IRQ_SPI(45)
#define IRQ_MODEM_IF IRQ_SPI(46)
#define IRQ_ROTATOR IRQ_SPI(47)
#define IRQ_JPEG IRQ_SPI(48)
#define IRQ_2D IRQ_SPI(49)
#define IRQ_PCIE IRQ_SPI(50)
#define IRQ_MCT0 IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52)
#define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56)
#define IRQ_KEYPAD IRQ_SPI(57)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
#define IRQ_SLIMBUS IRQ_SPI(59)
#define IRQ_PMU IRQ_SPI(60)
#define IRQ_TSI IRQ_SPI(61)
#define IRQ_SATA IRQ_SPI(62)
#define IRQ_GPS IRQ_SPI(63)
#define IRQ_EINT0 IRQ_SPI(16)
#define IRQ_EINT1 IRQ_SPI(17)
#define IRQ_EINT2 IRQ_SPI(18)
#define IRQ_EINT3 IRQ_SPI(19)
#define IRQ_EINT4 IRQ_SPI(20)
#define IRQ_EINT5 IRQ_SPI(21)
#define IRQ_EINT6 IRQ_SPI(22)
#define IRQ_EINT7 IRQ_SPI(23)
#define IRQ_EINT8 IRQ_SPI(24)
#define IRQ_EINT9 IRQ_SPI(25)
#define IRQ_EINT10 IRQ_SPI(26)
#define IRQ_EINT11 IRQ_SPI(27)
#define IRQ_EINT12 IRQ_SPI(28)
#define IRQ_EINT13 IRQ_SPI(29)
#define IRQ_EINT14 IRQ_SPI(30)
#define IRQ_EINT15 IRQ_SPI(31)
#define IRQ_EINT16_31 IRQ_SPI(32)
#define IRQ_PDMA0 IRQ_SPI(35)
#define IRQ_PDMA1 IRQ_SPI(36)
#define IRQ_TIMER0_VIC IRQ_SPI(37)
#define IRQ_TIMER1_VIC IRQ_SPI(38)
#define IRQ_TIMER2_VIC IRQ_SPI(39)
#define IRQ_TIMER3_VIC IRQ_SPI(40)
#define IRQ_TIMER4_VIC IRQ_SPI(41)
#define IRQ_MCT_L0 IRQ_SPI(42)
#define IRQ_WDT IRQ_SPI(43)
#define IRQ_RTC_ALARM IRQ_SPI(44)
#define IRQ_RTC_TIC IRQ_SPI(45)
#define IRQ_GPIO_XB IRQ_SPI(46)
#define IRQ_GPIO_XA IRQ_SPI(47)
#define IRQ_MCT_L1 IRQ_SPI(48)
#define IRQ_UART0 IRQ_SPI(52)
#define IRQ_UART1 IRQ_SPI(53)
#define IRQ_UART2 IRQ_SPI(54)
#define IRQ_UART3 IRQ_SPI(55)
#define IRQ_UART4 IRQ_SPI(56)
#define IRQ_MCT_G0 IRQ_SPI(57)
#define IRQ_IIC IRQ_SPI(58)
#define IRQ_IIC1 IRQ_SPI(59)
#define IRQ_IIC2 IRQ_SPI(60)
#define IRQ_IIC3 IRQ_SPI(61)
#define IRQ_IIC4 IRQ_SPI(62)
#define IRQ_IIC5 IRQ_SPI(63)
#define IRQ_IIC6 IRQ_SPI(64)
#define IRQ_IIC7 IRQ_SPI(65)
#define IRQ_USB_HOST IRQ_SPI(70)
#define IRQ_USB_HSOTG IRQ_SPI(71)
#define IRQ_MODEM_IF IRQ_SPI(72)
#define IRQ_HSMMC0 IRQ_SPI(73)
#define IRQ_HSMMC1 IRQ_SPI(74)
#define IRQ_HSMMC2 IRQ_SPI(75)
#define IRQ_HSMMC3 IRQ_SPI(76)
#define IRQ_DWMCI IRQ_SPI(77)
#define IRQ_MIPICSI0 IRQ_SPI(78)
#define IRQ_MIPICSI1 IRQ_SPI(80)
#define IRQ_ONENAND_AUDI IRQ_SPI(82)
#define IRQ_ROTATOR IRQ_SPI(83)
#define IRQ_FIMC0 IRQ_SPI(84)
#define IRQ_FIMC1 IRQ_SPI(85)
#define IRQ_FIMC2 IRQ_SPI(86)
#define IRQ_FIMC3 IRQ_SPI(87)
#define IRQ_JPEG IRQ_SPI(88)
#define IRQ_2D IRQ_SPI(89)
#define IRQ_PCIE IRQ_SPI(90)
#define IRQ_MFC IRQ_SPI(94)
#define IRQ_AUDIO_SS IRQ_SPI(96)
#define IRQ_I2S0 IRQ_SPI(97)
#define IRQ_I2S1 IRQ_SPI(98)
#define IRQ_I2S2 IRQ_SPI(99)
#define IRQ_AC97 IRQ_SPI(100)
#define IRQ_SPDIF IRQ_SPI(104)
#define IRQ_ADC0 IRQ_SPI(105)
#define IRQ_PEN0 IRQ_SPI(106)
#define IRQ_ADC1 IRQ_SPI(107)
#define IRQ_PEN1 IRQ_SPI(108)
#define IRQ_KEYPAD IRQ_SPI(109)
#define IRQ_PMU IRQ_SPI(110)
#define IRQ_GPS IRQ_SPI(111)
#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define IRQ_SLIMBUS IRQ_SPI(113)
#define IRQ_TSI IRQ_SPI(115)
#define IRQ_SATA IRQ_SPI(116)
#define MAX_IRQ_IN_COMBINER 8
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
......@@ -73,75 +138,14 @@
#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
#define IRQ_UART0 COMBINER_IRQ(26, 0)
#define IRQ_UART1 COMBINER_IRQ(26, 1)
#define IRQ_UART2 COMBINER_IRQ(26, 2)
#define IRQ_UART3 COMBINER_IRQ(26, 3)
#define IRQ_UART4 COMBINER_IRQ(26, 4)
#define IRQ_IIC COMBINER_IRQ(27, 0)
#define IRQ_IIC1 COMBINER_IRQ(27, 1)
#define IRQ_IIC2 COMBINER_IRQ(27, 2)
#define IRQ_IIC3 COMBINER_IRQ(27, 3)
#define IRQ_IIC4 COMBINER_IRQ(27, 4)
#define IRQ_IIC5 COMBINER_IRQ(27, 5)
#define IRQ_IIC6 COMBINER_IRQ(27, 6)
#define IRQ_IIC7 COMBINER_IRQ(27, 7)
#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
#define IRQ_EINT4 COMBINER_IRQ(37, 0)
#define IRQ_EINT5 COMBINER_IRQ(37, 1)
#define IRQ_EINT6 COMBINER_IRQ(37, 2)
#define IRQ_EINT7 COMBINER_IRQ(37, 3)
#define IRQ_EINT8 COMBINER_IRQ(38, 0)
#define IRQ_EINT9 COMBINER_IRQ(38, 1)
#define IRQ_EINT10 COMBINER_IRQ(38, 2)
#define IRQ_EINT11 COMBINER_IRQ(38, 3)
#define IRQ_EINT12 COMBINER_IRQ(38, 4)
#define IRQ_EINT13 COMBINER_IRQ(38, 5)
#define IRQ_EINT14 COMBINER_IRQ(38, 6)
#define IRQ_EINT15 COMBINER_IRQ(38, 7)
#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
#define IRQ_WDT COMBINER_IRQ(53, 0)
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
#define MAX_COMBINER_NR 16
#define MAX_COMBINER_NR 54
#define IRQ_ADC IRQ_ADC0
#define IRQ_TC IRQ_PEN0
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
......@@ -155,6 +159,6 @@
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_GPIO_END)
#define NR_IRQS (IRQ_GPIO_END + 64)
#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-exynos4/include/mach/map.h
View file @ 69f1d1a6
......@@ -57,12 +57,14 @@
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_COMBINER 0x10448000
#define EXYNOS4_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS4_GIC_BANK_OFFSET 0x8000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000
......@@ -93,7 +95,10 @@
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_FIMD0 0x11C00000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_DWMCI 0x12550000
#define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000
......@@ -103,11 +108,15 @@
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_HSPHY 0x125B0000
#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
......@@ -130,6 +139,8 @@
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
......@@ -140,10 +151,12 @@
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
......
arch/arm/mach-exynos4/include/mach/pm-core.h
View file @ 69f1d1a6
......@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{
/* nothing here yet */
}
static inline void s3c_pm_restored_gpios(void)
{
/* nothing here yet */
}
static inline void s3c_pm_saved_gpios(void)
{
/* nothing here yet */
}
arch/arm/mach-exynos4/include/mach/pmu.h 0 → 100644
View file @ 69f1d1a6
/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
#endif /* __ASM_ARCH_PMU_H */
arch/arm/mach-exynos4/include/mach/regs-audss.h 0 → 100644
View file @ 69f1d1a6
/* arch/arm/mach-exynos4/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* Exynos4 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
#endif /* _PLAT_REGS_AUDSS_H */
arch/arm/mach-exynos4/include/mach/regs-clock.h
View file @ 69f1d1a6
......@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
......@@ -33,7 +36,9 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
......@@ -61,6 +66,7 @@
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
......@@ -120,6 +126,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define S5P_EPLLCON0_ENABLE_SHIFT (31)
#define S5P_EPLLCON0_LOCKED_SHIFT (29)
#define S5P_VPLLCON0_ENABLE_SHIFT (31)
#define S5P_VPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
......
arch/arm/mach-exynos4/include/mach/regs-pmu.h
View file @ 69f1d1a6
......@@ -158,6 +158,7 @@
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD
......
arch/arm/mach-exynos4/mach-nuri.c
View file @ 69f1d1a6
This diff is collapsed.
arch/arm/mach-exynos4/mach-smdkc210.c
View file @ 69f1d1a6
......@@ -9,7 +9,9 @@
*/
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
......@@ -20,11 +22,15 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
......@@ -114,6 +120,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
/* fire nRESET on power up */
gpio_request(EXYNOS4_GPX0(6), "GPX0");
gpio_direction_output(EXYNOS4_GPX0(6), 1);
mdelay(100);
gpio_set_value(EXYNOS4_GPX0(6), 0);
mdelay(10);
gpio_set_value(EXYNOS4_GPX0(6), 1);
mdelay(10);
gpio_free(EXYNOS4_GPX0(6));
} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
gpio_free(EXYNOS4_GPD0(1));
#endif
}
}
static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
.set_power = lcd_lte480wv_set_power,
};
static struct platform_device smdkc210_lcd_lte480wv = {
.name = "platform-lcd",
.dev.parent = &s5p_device_fimd0.dev,
.dev.platform_data = &smdkc210_lcd_lte480wv_data,
};
static struct s3c_fb_pd_win smdkc210_fb_win0 = {
.win_mode = {
.left_margin = 13,
.right_margin = 8,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
.win[0] = &smdkc210_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
......@@ -168,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&s5p_device_fimd0,
&smdkc210_lcd_lte480wv,
&smdkc210_smsc911x,
};
......@@ -225,6 +294,7 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
}
......
arch/arm/mach-exynos4/mach-smdkv310.c
View file @ 69f1d1a6
......@@ -184,9 +184,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS],
&exynos4_device_spdif,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&samsung_asoc_idma,
&smdkv310_smsc911x,
&exynos4_device_ahci,
};
static void __init smdkv310_smsc911x_init(void)
......
arch/arm/mach-exynos4/mach-universal_c210.c
View file @ 69f1d1a6
......@@ -18,6 +18,9 @@
#include <linux/regulator/fixed.h>
#include <linux/regulator/max8952.h>
#include <linux/mmc/host.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/mcs.h>
#include <linux/i2c/atmel_mxt_ts.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......@@ -27,7 +30,10 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
#include <plat/mfc.h>
#include <plat/sdhci.h>
#include <plat/pd.h>
#include <mach/map.h>
......@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
},
};
/* I2C3 (TSP) */
static struct mxt_platform_data qt602240_platform_data = {
.x_line = 19,
.y_line = 11,
.x_size = 800,
.y_size = 480,
.blen = 0x11,
.threshold = 0x28,
.voltage = 2800000, /* 2.8V */
.orient = MXT_DIAGONAL,
};
static struct i2c_board_info i2c3_devs[] __initdata = {
{
I2C_BOARD_INFO("qt602240_ts", 0x4a),
.platform_data = &qt602240_platform_data,
},
};
static void __init universal_tsp_init(void)
{
int gpio;
/* TSP_LDO_ON: XMDMADDR_11 */
gpio = EXYNOS4_GPE2(3);
gpio_request(gpio, "TSP_LDO_ON");
gpio_direction_output(gpio, 1);
gpio_export(gpio, 0);
/* TSP_INT: XMDMADDR_7 */
gpio = EXYNOS4_GPE1(7);
gpio_request(gpio, "TSP_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
i2c3_devs[0].irq = gpio_to_irq(gpio);
}
/* GPIO I2C 12 (3 Touchkey) */
static uint32_t touchkey_keymap[] = {
/* MCS_KEY_MAP(value, keycode) */
MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
};
static struct mcs_platform_data touchkey_data = {
.keymap = touchkey_keymap,
.keymap_size = ARRAY_SIZE(touchkey_keymap),
.key_maxval = 2,
};
/* GPIO I2C 3_TOUCH 2.8V */
#define I2C_GPIO_BUS_12 12
static struct i2c_gpio_platform_data i2c_gpio12_data = {
.sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
.scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
};
static struct platform_device i2c_gpio12 = {
.name = "i2c-gpio",
.id = I2C_GPIO_BUS_12,
.dev = {
.platform_data = &i2c_gpio12_data,
},
};
static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
{
I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
.platform_data = &touchkey_data,
},
};
static void __init universal_touchkey_init(void)
{
int gpio;
gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
gpio_request(gpio, "3_TOUCH_INT");
s5p_register_gpio_interrupt(gpio);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
gpio_request(gpio, "3_TOUCH_EN");
gpio_direction_output(gpio, 1);
}
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
......@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5p_device_fimc3,
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c3,
&s3c_device_i2c5,
/* Universal Devices */
&i2c_gpio12,
&universal_gpio_keys,
&s5p_device_onenand,
&s5p_device_mfc,
&s5p_device_mfc_l,
&s5p_device_mfc_r,
&exynos4_device_pd[PD_MFC],
};
static void __init universal_map_io(void)
......@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
static void __init universal_reserve(void)
{
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}
static void __init universal_machine_init(void)
{
universal_sdhci_init();
......@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
universal_tsp_init();
s3c_i2c3_set_platdata(NULL);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
s3c_i2c5_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
universal_touchkey_init();
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
ARRAY_SIZE(i2c_gpio12_devs));
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
......@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.timer = &exynos4_timer,
.reserve = &universal_reserve,
MACHINE_END
arch/arm/mach-exynos4/mct.c
View file @ 69f1d1a6
......@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
irq_set_affinity(IRQ_MCT1, cpumask_of(1));
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
}
}
......
arch/arm/mach-exynos4/platsmp.c
View file @ 69f1d1a6
......@@ -28,9 +28,12 @@
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG S5P_VA_SYSRAM
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
......@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos4_gic_secondary_init(void)
{
void __iomem *dist_base = S5P_VA_GIC_DIST +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
void __iomem *cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
int i;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
__raw_writel(1, cpu_base + GIC_CPU_CTRL);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
......@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
exynos4_gic_secondary_init();
/*
* let the primary processor know we're out of the
......@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(cpu);
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
S5P_ARM_CORE1_CONFIGURATION);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
while ((__raw_readl(S5P_ARM_CORE1_STATUS)
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
mdelay(1);
}
if (timeout == 0) {
printk(KERN_ERR "cpu1 power enable failed");
spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
}
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
CPU1_BOOT_REG);
gic_raise_softirq(cpumask_of(cpu), 1);
if (pen_release == -1)
break;
......
arch/arm/mach-exynos4/pm.c
View file @ 69f1d1a6
This diff is collapsed.
arch/arm/mach-exynos4/pmu.c 0 → 100644
View file @ 69f1d1a6
/* linux/arch/arm/mach-exynos4/pmu.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - CPU PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/regs-clock.h>
#include <mach/pmu.h>
static void __iomem *sys_powerdown_reg[] = {
S5P_ARM_CORE0_LOWPWR,
S5P_DIS_IRQ_CORE0,
S5P_DIS_IRQ_CENTRAL0,
S5P_ARM_CORE1_LOWPWR,
S5P_DIS_IRQ_CORE1,
S5P_DIS_IRQ_CENTRAL1,
S5P_ARM_COMMON_LOWPWR,
S5P_L2_0_LOWPWR,
S5P_L2_1_LOWPWR,
S5P_CMU_ACLKSTOP_LOWPWR,
S5P_CMU_SCLKSTOP_LOWPWR,
S5P_CMU_RESET_LOWPWR,
S5P_APLL_SYSCLK_LOWPWR,
S5P_MPLL_SYSCLK_LOWPWR,
S5P_VPLL_SYSCLK_LOWPWR,
S5P_EPLL_SYSCLK_LOWPWR,
S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
S5P_CMU_RESET_GPSALIVE_LOWPWR,
S5P_CMU_CLKSTOP_CAM_LOWPWR,
S5P_CMU_CLKSTOP_TV_LOWPWR,
S5P_CMU_CLKSTOP_MFC_LOWPWR,
S5P_CMU_CLKSTOP_G3D_LOWPWR,
S5P_CMU_CLKSTOP_LCD0_LOWPWR,
S5P_CMU_CLKSTOP_LCD1_LOWPWR,
S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
S5P_CMU_CLKSTOP_GPS_LOWPWR,
S5P_CMU_RESET_CAM_LOWPWR,
S5P_CMU_RESET_TV_LOWPWR,
S5P_CMU_RESET_MFC_LOWPWR,
S5P_CMU_RESET_G3D_LOWPWR,
S5P_CMU_RESET_LCD0_LOWPWR,
S5P_CMU_RESET_LCD1_LOWPWR,
S5P_CMU_RESET_MAUDIO_LOWPWR,
S5P_CMU_RESET_GPS_LOWPWR,
S5P_TOP_BUS_LOWPWR,
S5P_TOP_RETENTION_LOWPWR,
S5P_TOP_PWR_LOWPWR,
S5P_LOGIC_RESET_LOWPWR,
S5P_ONENAND_MEM_LOWPWR,
S5P_MODIMIF_MEM_LOWPWR,
S5P_G2D_ACP_MEM_LOWPWR,
S5P_USBOTG_MEM_LOWPWR,
S5P_HSMMC_MEM_LOWPWR,
S5P_CSSYS_MEM_LOWPWR,
S5P_SECSS_MEM_LOWPWR,
S5P_PCIE_MEM_LOWPWR,
S5P_SATA_MEM_LOWPWR,
S5P_PAD_RETENTION_DRAM_LOWPWR,
S5P_PAD_RETENTION_MAUDIO_LOWPWR,
S5P_PAD_RETENTION_GPIO_LOWPWR,
S5P_PAD_RETENTION_UART_LOWPWR,
S5P_PAD_RETENTION_MMCA_LOWPWR,
S5P_PAD_RETENTION_MMCB_LOWPWR,
S5P_PAD_RETENTION_EBIA_LOWPWR,
S5P_PAD_RETENTION_EBIB_LOWPWR,
S5P_PAD_RETENTION_ISOLATION_LOWPWR,
S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
S5P_XUSBXTI_LOWPWR,
S5P_XXTI_LOWPWR,
S5P_EXT_REGULATOR_LOWPWR,
S5P_GPIO_MODE_LOWPWR,
S5P_GPIO_MODE_MAUDIO_LOWPWR,
S5P_CAM_LOWPWR,
S5P_TV_LOWPWR,
S5P_MFC_LOWPWR,
S5P_G3D_LOWPWR,
S5P_LCD0_LOWPWR,
S5P_LCD1_LOWPWR,
S5P_MAUDIO_LOWPWR,
S5P_GPS_LOWPWR,
S5P_GPS_ALIVE_LOWPWR,
};
static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
/* { AFTR, LPA, SLEEP }*/
{ 0, 0, 2 }, /* ARM_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
{ 0, 0, 2 }, /* ARM_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
{ 0, 0, 2 }, /* ARM_COMMON */
{ 2, 2, 3 }, /* ARM_CPU_L2_0 */
{ 2, 2, 3 }, /* ARM_CPU_L2_1 */
{ 1, 0, 0 }, /* CMU_ACLKSTOP */
{ 1, 0, 0 }, /* CMU_SCLKSTOP */
{ 1, 1, 0 }, /* CMU_RESET */
{ 1, 0, 0 }, /* APLL_SYSCLK */
{ 1, 0, 0 }, /* MPLL_SYSCLK */
{ 1, 0, 0 }, /* VPLL_SYSCLK */
{ 1, 1, 0 }, /* EPLL_SYSCLK */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
{ 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
{ 1, 1, 0 }, /* CMU_CLKSTOP_TV */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
{ 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
{ 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
{ 1, 1, 0 }, /* CMU_RESET_CAM */
{ 1, 1, 0 }, /* CMU_RESET_TV */
{ 1, 1, 0 }, /* CMU_RESET_MFC */
{ 1, 1, 0 }, /* CMU_RESET_G3D */
{ 1, 1, 0 }, /* CMU_RESET_LCD0 */
{ 1, 1, 0 }, /* CMU_RESET_LCD1 */
{ 1, 1, 0 }, /* CMU_RESET_MAUDIO */
{ 1, 1, 0 }, /* CMU_RESET_GPS */
{ 3, 0, 0 }, /* TOP_BUS */
{ 1, 0, 1 }, /* TOP_RETENTION */
{ 3, 0, 3 }, /* TOP_PWR */
{ 1, 1, 0 }, /* LOGIC_RESET */
{ 3, 0, 0 }, /* ONENAND_MEM */
{ 3, 0, 0 }, /* MODIMIF_MEM */
{ 3, 0, 0 }, /* G2D_ACP_MEM */
{ 3, 0, 0 }, /* USBOTG_MEM */
{ 3, 0, 0 }, /* HSMMC_MEM */
{ 3, 0, 0 }, /* CSSYS_MEM */
{ 3, 0, 0 }, /* SECSS_MEM */
{ 3, 0, 0 }, /* PCIE_MEM */
{ 3, 0, 0 }, /* SATA_MEM */
{ 1, 0, 0 }, /* PAD_RETENTION_DRAM */
{ 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
{ 1, 0, 0 }, /* PAD_RETENTION_GPIO */
{ 1, 0, 0 }, /* PAD_RETENTION_UART */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCA */
{ 1, 0, 0 }, /* PAD_RETENTION_MMCB */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIA */
{ 1, 0, 0 }, /* PAD_RETENTION_EBIB */
{ 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
{ 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
{ 1, 1, 0 }, /* XUSBXTI */
{ 1, 1, 0 }, /* XXTI */
{ 1, 1, 0 }, /* EXT_REGULATOR */
{ 1, 0, 0 }, /* GPIO_MODE */
{ 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
{ 7, 0, 0 }, /* CAM */
{ 7, 0, 0 }, /* TV */
{ 7, 0, 0 }, /* MFC */
{ 7, 0, 0 }, /* G3D */
{ 7, 0, 0 }, /* LCD0 */
{ 7, 0, 0 }, /* LCD1 */
{ 7, 7, 0 }, /* MAUDIO */
{ 7, 0, 0 }, /* GPS */
{ 7, 0, 0 }, /* GPS_ALIVE */
};
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
for (; count > 0; count--)
__raw_writel(sys_powerdown_val[count - 1][mode],
sys_powerdown_reg[count - 1]);
}
arch/arm/mach-exynos4/setup-fimd0.c 0 → 100644
View file @ 69f1d1a6
/* linux/arch/arm/mach-exynos4/setup-fimd0.c
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Base Exynos4 FIMD 0 configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/fb.h>
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-fb-v4.h>
#include <mach/map.h>
void exynos4_fimd0_gpio_setup_24bpp(void)
{
unsigned int reg;
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
/*
* Set DISPLAY_CONTROL register for Display path selection.
*
* DISPLAY_CONTROL[1:0]
* ---------------------
* 00 | MIE
* 01 | MDINE
* 10 | FIMD : selected
* 11 | FIMD
*/
reg = __raw_readl(S3C_VA_SYS + 0x0210);
reg |= (1 << 1);
__raw_writel(reg, S3C_VA_SYS + 0x0210);
}
arch/arm/mach-exynos4/time.c deleted 100644 → 0
View file @ 2d86a3f0
/* linux/arch/arm/mach-exynos4/time.c
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 (and compatible) HRT support
* PWM 2/4 is used for this feature
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <asm/smp_twd.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <asm/mach/time.h>
static unsigned long clock_count_per_tick;
static struct clk *tin2;
static struct clk *tin4;
static struct clk *tdiv2;
static struct clk *tdiv4;
static struct clk *timerclk;
static void exynos4_pwm_stop(unsigned int pwm_id)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon &= ~S3C2410_TCON_T2START;
break;
case 4:
tcon &= ~S3C2410_TCON_T4START;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
/* timers reload after counting zero, so reduce the count by 1 */
tcnt--;
/* ensure timer is stopped... */
switch (pwm_id) {
case 2:
tcon &= ~(0xf<<12);
tcon |= S3C2410_TCON_T2MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(2));
__raw_writel(tcnt, S3C2410_TCMPB(2));
__raw_writel(tcon, S3C2410_TCON);
break;
case 4:
tcon &= ~(7<<20);
tcon |= S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcnt, S3C2410_TCNTB(4));
__raw_writel(tcnt, S3C2410_TCMPB(4));
__raw_writel(tcon, S3C2410_TCON);
break;
default:
break;
}
}
static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
{
unsigned long tcon;
tcon = __raw_readl(S3C2410_TCON);
switch (pwm_id) {
case 2:
tcon |= S3C2410_TCON_T2START;
tcon &= ~S3C2410_TCON_T2MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T2RELOAD;
else
tcon &= ~S3C2410_TCON_T2RELOAD;
break;
case 4:
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
if (periodic)
tcon |= S3C2410_TCON_T4RELOAD;
else
tcon &= ~S3C2410_TCON_T4RELOAD;
break;
default:
break;
}
__raw_writel(tcon, S3C2410_TCON);
}
static int exynos4_pwm_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
exynos4_pwm_init(2, cycles);
exynos4_pwm_start(2, 0);
return 0;
}
static void exynos4_pwm_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
exynos4_pwm_stop(2);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
exynos4_pwm_init(2, clock_count_per_tick);
exynos4_pwm_start(2, 1);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device pwm_event_device = {
.name = "pwm_timer2",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.shift = 32,
.set_next_event = exynos4_pwm_set_next_event,
.set_mode = exynos4_pwm_set_mode,
};
irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = &pwm_event_device;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction exynos4_clock_event_irq = {
.name = "pwm_timer2_irq",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = exynos4_clock_event_isr,
};
static void __init exynos4_clockevent_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
struct clk *tscaler;
pclk = clk_get_rate(timerclk);
/* configure clock tick */
tscaler = clk_get_parent(tdiv2);
clk_set_rate(tscaler, pclk / 2);
clk_set_rate(tdiv2, pclk / 2);
clk_set_parent(tin2, tdiv2);
clock_rate = clk_get_rate(tin2);
clock_count_per_tick = clock_rate / HZ;
pwm_event_device.mult =
div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
pwm_event_device.max_delta_ns =
clockevent_delta2ns(-1, &pwm_event_device);
pwm_event_device.min_delta_ns =
clockevent_delta2ns(1, &pwm_event_device);
pwm_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&pwm_event_device);
setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
}
static cycle_t exynos4_pwm4_read(struct clocksource *cs)
{
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
#ifdef CONFIG_PM
static void exynos4_pwm4_resume(struct clocksource *cs)
{
unsigned long pclk;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
}
#endif
struct clocksource pwm_clocksource = {
.name = "pwm_timer4",
.rating = 250,
.read = exynos4_pwm4_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
#ifdef CONFIG_PM
.resume = exynos4_pwm4_resume,
#endif
};
static void __init exynos4_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
pclk = clk_get_rate(timerclk);
clk_set_rate(tdiv4, pclk / 2);
clk_set_parent(tin4, tdiv4);
clock_rate = clk_get_rate(tin4);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
if (clocksource_register_hz(&pwm_clocksource, clock_rate))
panic("%s: can't register clocksource\n", pwm_clocksource.name);
}
static void __init exynos4_timer_resources(void)
{
struct platform_device tmpdev;
tmpdev.dev.bus = &platform_bus_type;
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
panic("failed to get timers clock for system timer");
clk_enable(timerclk);
tmpdev.id = 2;
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv2))
panic("failed to get pwm-tdiv2 clock for system timer");
clk_enable(tin2);
tmpdev.id = 4;
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
if (IS_ERR(tdiv4))
panic("failed to get pwm-tdiv4 clock for system timer");
clk_enable(tin4);
}
static void __init exynos4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = S5P_VA_TWD;
#endif
exynos4_timer_resources();
exynos4_clockevent_init();
exynos4_clocksource_init();
}
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};
arch/arm/mach-imx/Kconfig
View file @ 69f1d1a6
......@@ -278,6 +278,7 @@ config MACH_MX27_3DS
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
......
arch/arm/mach-imx/mach-mx27_3ds.c
View file @ 69f1d1a6
......@@ -29,6 +29,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <linux/spi/l4f00242t03.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -47,7 +48,10 @@
#define SPI2_SS0 IMX_GPIO_NR(4, 21)
#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28))
#define PMIC_INT IMX_GPIO_NR(3, 14)
#define SPI1_SS0 IMX_GPIO_NR(4, 28)
#define SD1_CD IMX_GPIO_NR(2, 26)
#define LCD_RESET IMX_GPIO_NR(1, 3)
#define LCD_ENABLE IMX_GPIO_NR(1, 31)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
......@@ -96,6 +100,12 @@ static const int mx27pdk_pins[] __initconst = {
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* CSPI1 */
PD31_PF_CSPI1_MOSI,
PD30_PF_CSPI1_MISO,
PD29_PF_CSPI1_SCLK,
PD25_PF_CSPI1_RDY,
SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
/* CSPI2 */
PD22_PF_CSPI2_SCLK,
PD23_PF_CSPI2_MISO,
......@@ -106,6 +116,31 @@ static const int mx27pdk_pins[] __initconst = {
PD18_PF_I2C_CLK,
/* PMIC INT */
PMIC_INT | GPIO_GPIO | GPIO_IN,
/* LCD */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
LCD_RESET | GPIO_GPIO | GPIO_OUT,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
......@@ -258,10 +293,18 @@ static struct mc13xxx_platform_data mc13783_pdata = {
.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
},
.flags = MC13783_USE_REGULATOR,
.flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN |
MC13783_USE_RTC,
};
/* SPI */
static int spi1_chipselect[] = {SPI1_SS0};
static const struct spi_imx_master spi1_pdata __initconst = {
.chipselect = spi1_chipselect,
.num_chipselect = ARRAY_SIZE(spi1_chipselect),
};
static int spi2_chipselect[] = {SPI2_SS0};
static const struct spi_imx_master spi2_pdata __initconst = {
......@@ -269,6 +312,46 @@ static const struct spi_imx_master spi2_pdata __initconst = {
.num_chipselect = ARRAY_SIZE(spi2_chipselect),
};
static struct imx_fb_videomode mx27_3ds_modes[] = {
{ /* 480x640 @ 60 Hz */
.mode = {
.name = "Epson-VGA",
.refresh = 60,
.xres = 480,
.yres = 640,
.pixclock = 41701,
.left_margin = 20,
.right_margin = 41,
.upper_margin = 10,
.lower_margin = 5,
.hsync_len = 20,
.vsync_len = 10,
.sync = FB_SYNC_OE_ACT_HIGH |
FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
.bpp = 16,
.pcr = 0xFAC08B82,
},
};
static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
.mode = mx27_3ds_modes,
.num_modes = ARRAY_SIZE(mx27_3ds_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
/* LCD */
static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
.reset_gpio = LCD_RESET,
.data_enable_gpio = LCD_ENABLE,
.core_supply = "lcd_2v8",
.io_supply = "vdd_lcdio",
};
static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
{
.modalias = "mc13783",
......@@ -278,6 +361,12 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
.platform_data = &mc13783_pdata,
.irq = gpio_to_irq(PMIC_INT),
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
.max_speed_hz = 5000000,
.bus_num = 0,
.chip_select = 0, /* SS0 */
.platform_data = &mx27_3ds_lcd_pdata,
},
};
......@@ -311,12 +400,14 @@ static void __init mx27pdk_init(void)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
imx27_add_spi_imx1(&spi2_pdata);
imx27_add_spi_imx0(&spi1_pdata);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
imx27_add_imx_fb(&mx27_3ds_fb_data);
}
static void __init mx27pdk_timer_init(void)
......
arch/arm/mach-imx/mm-imx21.c
View file @ 69f1d1a6
......@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
......@@ -82,4 +83,6 @@ void __init imx21_soc_init(void)
mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
imx_add_imx_dma();
}
arch/arm/mach-imx/mm-imx25.c
View file @ 69f1d1a6
......@@ -24,6 +24,7 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
......@@ -61,6 +62,28 @@ void __init mx25_init_irq(void)
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx25_sdma_script __initdata = {
.ap_2_ap_addr = 729,
.uart_2_mcu_addr = 904,
.per_2_app_addr = 1255,
.mcu_2_app_addr = 834,
.uartsh_2_mcu_addr = 1120,
.per_2_shp_addr = 1329,
.mcu_2_shp_addr = 1048,
.ata_2_mcu_addr = 1560,
.mcu_2_ata_addr = 1479,
.app_2_per_addr = 1189,
.app_2_mcu_addr = 770,
.shp_2_per_addr = 1407,
.shp_2_mcu_addr = 979,
};
static struct sdma_platform_data imx25_sdma_pdata __initdata = {
.sdma_version = 2,
.fw_name = "sdma-imx25.bin",
.script_addrs = &imx25_sdma_script,
};
void __init imx25_soc_init(void)
{
/* i.mx25 has the i.mx31 type gpio */
......@@ -68,4 +91,6 @@ void __init imx25_soc_init(void)
mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
imx_add_imx_sdma(MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
}
arch/arm/mach-imx/mm-imx27.c
View file @ 69f1d1a6
......@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
......@@ -83,4 +84,6 @@ void __init imx27_soc_init(void)
mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
imx_add_imx_dma();
}
arch/arm/mach-imx/mm-imx31.c
View file @ 69f1d1a6
......@@ -24,6 +24,7 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
......@@ -57,9 +58,35 @@ void __init mx31_init_irq(void)
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
.per_2_per_addr = 1677,
};
static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
.ap_2_ap_addr = 423,
.ap_2_bp_addr = 829,
.bp_2_ap_addr = 1029,
};
static struct sdma_platform_data imx31_sdma_pdata __initdata = {
.sdma_version = 1,
.fw_name = "sdma-imx31-to2.bin",
.script_addrs = &imx31_to2_sdma_script,
};
void __init imx31_soc_init(void)
{
int to_version = mx31_revision() >> 4;
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
strlen(imx31_sdma_pdata.fw_name));
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
}
imx_add_imx_sdma(MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
}
arch/arm/mach-imx/mm-imx35.c
View file @ 69f1d1a6
......@@ -25,6 +25,7 @@
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
......@@ -54,10 +55,56 @@ void __init mx35_init_irq(void)
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
.ap_2_ap_addr = 642,
.uart_2_mcu_addr = 817,
.mcu_2_app_addr = 747,
.uartsh_2_mcu_addr = 1183,
.per_2_shp_addr = 1033,
.mcu_2_shp_addr = 961,
.ata_2_mcu_addr = 1333,
.mcu_2_ata_addr = 1252,
.app_2_mcu_addr = 683,
.shp_2_per_addr = 1111,
.shp_2_mcu_addr = 892,
};
static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
.ap_2_ap_addr = 729,
.uart_2_mcu_addr = 904,
.per_2_app_addr = 1597,
.mcu_2_app_addr = 834,
.uartsh_2_mcu_addr = 1270,
.per_2_shp_addr = 1120,
.mcu_2_shp_addr = 1048,
.ata_2_mcu_addr = 1429,
.mcu_2_ata_addr = 1339,
.app_2_per_addr = 1531,
.app_2_mcu_addr = 770,
.shp_2_per_addr = 1198,
.shp_2_mcu_addr = 979,
};
static struct sdma_platform_data imx35_sdma_pdata __initdata = {
.sdma_version = 2,
.fw_name = "sdma-imx35-to2.bin",
.script_addrs = &imx35_to2_sdma_script,
};
void __init imx35_soc_init(void)
{
int to_version = mx35_revision() >> 4;
/* i.mx35 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
strlen(imx35_sdma_pdata.fw_name));
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
}
imx_add_imx_sdma(MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
}
arch/arm/mach-lpc32xx/clock.c
View file @ 69f1d1a6
......@@ -1077,7 +1077,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
_REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
_REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
_REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
_REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
......
arch/arm/mach-lpc32xx/common.c
View file @ 69f1d1a6
......@@ -95,6 +95,48 @@ struct platform_device lpc32xx_i2c2_device = {
},
};
/* TSC (Touch Screen Controller) */
static struct resource lpc32xx_tsc_resources[] = {
{
.start = LPC32XX_ADC_BASE,
.end = LPC32XX_ADC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LPC32XX_TS_IRQ,
.end = IRQ_LPC32XX_TS_IRQ,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device lpc32xx_tsc_device = {
.name = "ts-lpc32xx",
.id = -1,
.num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
.resource = lpc32xx_tsc_resources,
};
/* RTC */
static struct resource lpc32xx_rtc_resources[] = {
{
.start = LPC32XX_RTC_BASE,
.end = LPC32XX_RTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},{
.start = IRQ_LPC32XX_RTC,
.end = IRQ_LPC32XX_RTC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device lpc32xx_rtc_device = {
.name = "rtc-lpc32xx",
.id = -1,
.num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
.resource = lpc32xx_rtc_resources,
};
/*
* Returns the unique ID for the device
*/
......
arch/arm/mach-lpc32xx/common.h
View file @ 69f1d1a6
......@@ -28,6 +28,8 @@ extern struct platform_device lpc32xx_watchdog_device;
extern struct platform_device lpc32xx_i2c0_device;
extern struct platform_device lpc32xx_i2c1_device;
extern struct platform_device lpc32xx_i2c2_device;
extern struct platform_device lpc32xx_tsc_device;
extern struct platform_device lpc32xx_rtc_device;
/*
* Other arch specific structures and functions
......
arch/arm/mach-mmp/Kconfig
View file @ 69f1d1a6
......@@ -77,6 +77,13 @@ config MACH_TETON_BGA
Say 'Y' here if you want to support the Marvell PXA168-based
Teton BGA Development Board.
config MACH_SHEEVAD
bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
GuruPlug Display (gplugD) Board
endmenu
config CPU_PXA168
......
arch/arm/mach-mmp/Makefile
View file @ 69f1d1a6
......@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
obj-$(CONFIG_MACH_SHEEVAD) += gplugd.o
arch/arm/mach-mmp/clock.c
View file @ 69f1d1a6
......@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
int ret = -EINVAL;
if (clk->ops->setrate) {
spin_lock_irqsave(&clocks_lock, flags);
ret = clk->ops->setrate(clk, rate);
spin_unlock_irqrestore(&clocks_lock, flags);
}
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
arch/arm/mach-mmp/clock.h
View file @ 69f1d1a6
......@@ -12,6 +12,7 @@ struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
int (*setrate)(struct clk *, unsigned long);
};
struct clk {
......
arch/arm/mach-mmp/gplugd.c 0 → 100644
View file @ 69f1d1a6
/*
* linux/arch/arm/mach-mmp/gplugd.c
*
* Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/gpio.h>
#include <mach/pxa168.h>
#include <mach/mfp-pxa168.h>
#include <mach/mfp-gplugd.h>
#include "common.h"
static unsigned long gplugd_pin_config[] __initdata = {
/* UART3 */
GPIO8_UART3_SOUT,
GPIO9_UART3_SIN,
GPI1O_UART3_CTS,
GPI11_UART3_RTS,
/* MMC2 */
GPIO28_MMC2_CMD,
GPIO29_MMC2_CLK,
GPIO30_MMC2_DAT0,
GPIO31_MMC2_DAT1,
GPIO32_MMC2_DAT2,
GPIO33_MMC2_DAT3,
/* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */
GPIO35_GPIO,
GPIO36_GPIO, /* CEC Interrupt */
/* MMC1 */
GPIO43_MMC1_CLK,
GPIO49_MMC1_CMD,
GPIO41_MMC1_DAT0,
GPIO40_MMC1_DAT1,
GPIO52_MMC1_DAT2,
GPIO51_MMC1_DAT3,
GPIO53_MMC1_CD,
/* LCD */
GPIO56_LCD_FCLK_RD,
GPIO57_LCD_LCLK_A0,
GPIO58_LCD_PCLK_WR,
GPIO59_LCD_DENA_BIAS,
GPIO60_LCD_DD0,
GPIO61_LCD_DD1,
GPIO62_LCD_DD2,
GPIO63_LCD_DD3,
GPIO64_LCD_DD4,
GPIO65_LCD_DD5,
GPIO66_LCD_DD6,
GPIO67_LCD_DD7,
GPIO68_LCD_DD8,
GPIO69_LCD_DD9,
GPIO70_LCD_DD10,
GPIO71_LCD_DD11,
GPIO72_LCD_DD12,
GPIO73_LCD_DD13,
GPIO74_LCD_DD14,
GPIO75_LCD_DD15,
GPIO76_LCD_DD16,
GPIO77_LCD_DD17,
GPIO78_LCD_DD18,
GPIO79_LCD_DD19,
GPIO80_LCD_DD20,
GPIO81_LCD_DD21,
GPIO82_LCD_DD22,
GPIO83_LCD_DD23,
/* GPIO */
GPIO84_GPIO,
GPIO85_GPIO,
/* Fast-Ethernet*/
GPIO86_TX_CLK,
GPIO87_TX_EN,
GPIO88_TX_DQ3,
GPIO89_TX_DQ2,
GPIO90_TX_DQ1,
GPIO91_TX_DQ0,
GPIO92_MII_CRS,
GPIO93_MII_COL,
GPIO94_RX_CLK,
GPIO95_RX_ER,
GPIO96_RX_DQ3,
GPIO97_RX_DQ2,
GPIO98_RX_DQ1,
GPIO99_RX_DQ0,
GPIO100_MII_MDC,
GPIO101_MII_MDIO,
GPIO103_RX_DV,
GPIO104_GPIO, /* Reset PHY */
/* RTC interrupt */
GPIO102_GPIO,
/* I2C */
GPIO105_CI2C_SDA,
GPIO106_CI2C_SCL,
/* Select JTAG */
GPIO109_GPIO,
/* I2S */
GPIO114_I2S_FRM,
GPIO115_I2S_BCLK,
GPIO116_I2S_TXD
};
static struct i2c_board_info gplugd_i2c_board_info[] = {
{
.type = "isl1208",
.addr = 0x6F,
}
};
/* Bring PHY out of reset by setting GPIO 104 */
static int gplugd_eth_init(void)
{
if (unlikely(gpio_request(104, "ETH_RESET_N"))) {
printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet "
"PHY out of reset\n");
return -EIO;
}
gpio_direction_output(104, 1);
gpio_free(104);
return 0;
}
struct pxa168_eth_platform_data gplugd_eth_platform_data = {
.port_number = 0,
.phy_addr = 0,
.speed = 0, /* Autonagotiation */
.init = gplugd_eth_init,
};
static void __init select_disp_freq(void)
{
/* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) {
printk(KERN_ERR "Can't get hold of GPIO 35 to select display "
"frequency\n");
} else {
gpio_direction_output(35, 1);
gpio_free(104);
}
if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
printk(KERN_ERR "Can't get hold of GPIO 85 to select display "
"frequency\n");
} else {
gpio_direction_output(85, 0);
gpio_free(104);
}
}
static void __init gplugd_init(void)
{
mfp_config(ARRAY_AND_SIZE(gplugd_pin_config));
select_disp_freq();
/* on-chip devices */
pxa168_add_uart(3);
pxa168_add_ssp(0);
pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
pxa168_add_eth(&gplugd_eth_platform_data);
}
MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform")
.map_io = mmp_map_io,
.nr_irqs = IRQ_BOARD_START,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = gplugd_init,
MACHINE_END
arch/arm/mach-mmp/include/mach/mfp-gplugd.h 0 → 100644
View file @ 69f1d1a6
/*
* linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
*
* MFP definitions used in gplugD
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_MFP_GPLUGD_H
#define __MACH_MFP_GPLUGD_H
#include <plat/mfp.h>
#include <mach/mfp.h>
/* UART3 */
#define GPIO8_UART3_SOUT MFP_CFG(GPIO8, AF2)
#define GPIO9_UART3_SIN MFP_CFG(GPIO9, AF2)
#define GPI1O_UART3_CTS MFP_CFG(GPIO10, AF2)
#define GPI11_UART3_RTS MFP_CFG(GPIO11, AF2)
/* MMC2 */
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
/* I2S */
#undef GPIO114_I2S_FRM
#undef GPIO115_I2S_BCLK
#define GPIO114_I2S_FRM MFP_CFG_DRV(GPIO114, AF1, FAST)
#define GPIO115_I2S_BCLK MFP_CFG_DRV(GPIO115, AF1, FAST)
#define GPIO116_I2S_TXD MFP_CFG_DRV(GPIO116, AF1, FAST)
/* MMC4 */
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
/* OTG GPIO */
#define GPIO_USB_OTG_PEN 18
#define GPIO_USB_OIDIR 20
/* Other GPIOs are 35, 84, 85 */
#endif /* __MACH_MFP_GPLUGD_H */
arch/arm/mach-mmp/include/mach/mfp-pxa168.h
View file @ 69f1d1a6
......@@ -305,4 +305,23 @@
#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
/* Fast Ethernet */
#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
#endif /* __ASM_MACH_MFP_PXA168_H */
arch/arm/mach-mmp/include/mach/pxa168.h
View file @ 69f1d1a6
......@@ -14,9 +14,11 @@ extern void pxa168_clear_keypad_wakeup(void);
#include <video/pxa168fb.h>
#include <plat/pxa27x_keypad.h>
#include <mach/cputype.h>
#include <linux/pxa168_eth.h>
extern struct pxa_device_desc pxa168_device_uart1;
extern struct pxa_device_desc pxa168_device_uart2;
extern struct pxa_device_desc pxa168_device_uart3;
extern struct pxa_device_desc pxa168_device_twsi0;
extern struct pxa_device_desc pxa168_device_twsi1;
extern struct pxa_device_desc pxa168_device_pwm1;
......@@ -31,6 +33,7 @@ extern struct pxa_device_desc pxa168_device_ssp5;
extern struct pxa_device_desc pxa168_device_nand;
extern struct pxa_device_desc pxa168_device_fb;
extern struct pxa_device_desc pxa168_device_keypad;
extern struct pxa_device_desc pxa168_device_eth;
static inline int pxa168_add_uart(int id)
{
......@@ -39,6 +42,7 @@ static inline int pxa168_add_uart(int id)
switch (id) {
case 1: d = &pxa168_device_uart1; break;
case 2: d = &pxa168_device_uart2; break;
case 3: d = &pxa168_device_uart3; break;
}
if (d == NULL)
......@@ -117,4 +121,8 @@ static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
}
static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
{
return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
}
#endif /* __ASM_MACH_PXA168_H */
arch/arm/mach-mmp/include/mach/regs-apmu.h
View file @ 69f1d1a6
......@@ -29,6 +29,7 @@
#define APMU_BUS APMU_REG(0x06c)
#define APMU_SDH2 APMU_REG(0x0e8)
#define APMU_SDH3 APMU_REG(0x0ec)
#define APMU_ETH APMU_REG(0x0fc)
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)
......
arch/arm/mach-mmp/pxa168.c
View file @ 69f1d1a6
......@@ -66,6 +66,7 @@ void __init pxa168_init_irq(void)
/* APB peripheral clocks */
static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
......@@ -81,11 +82,13 @@ static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
static APMU_CLK(eth, ETH, 0x09, 0);
/* device and clock bindings */
static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
......@@ -100,6 +103,7 @@ static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
};
static int __init pxa168_init(void)
......@@ -149,6 +153,7 @@ void pxa168_clear_keypad_wakeup(void)
/* on-chip devices */
PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
......@@ -163,3 +168,4 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
arch/arm/mach-mmp/ttc_dkb.c
View file @ 69f1d1a6
......@@ -15,6 +15,8 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/interrupt.h>
#include <linux/i2c/pca953x.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -25,7 +27,17 @@
#include "common.h"
#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24)
#define TTCDKB_GPIO_EXT0(x) (NR_BUILTIN_GPIO + ((x < 0) ? 0 : \
((x < 16) ? x : 15)))
#define TTCDKB_GPIO_EXT1(x) (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
((x < 16) ? x : 15)))
/*
* 16 board interrupts -- MAX7312 GPIO expander
* 16 board interrupts -- PCA9575 GPIO expander
* 24 board interrupts -- 88PM860x PMIC
*/
#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 16 + 16 + 24)
static unsigned long ttc_dkb_pin_config[] __initdata = {
/* UART2 */
......@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = {
&ttc_dkb_device_onenand,
};
static struct pca953x_platform_data max7312_data[] = {
{
.gpio_base = TTCDKB_GPIO_EXT0(0),
.irq_base = IRQ_BOARD_START,
},
};
static struct i2c_board_info ttc_dkb_i2c_info[] = {
{
.type = "max7312",
.addr = 0x23,
.irq = IRQ_GPIO(80),
.platform_data = &max7312_data,
},
};
static void __init ttc_dkb_init(void)
{
mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
......@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void)
pxa910_add_uart(1);
/* off-chip devices */
pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
}
......
arch/arm/mach-mx5/Kconfig
View file @ 69f1d1a6
......@@ -180,6 +180,7 @@ config MACH_MX53_EVK
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select LEDS_GPIO_REGISTER
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
......@@ -203,10 +204,23 @@ config MACH_MX53_LOCO
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
select LEDS_GPIO_REGISTER
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_ARD
bool "Support MX53 ARD platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
help
Include support for MX53 ARD platform. This includes specific
configurations for the board and its peripherals.
endif # ARCH_MX53_SUPPORTED
endif
arch/arm/mach-mx5/Makefile
View file @ 69f1d1a6
......@@ -6,12 +6,14 @@
obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
obj-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
......
arch/arm/mach-mx5/board-mx51_babbage.c
View file @ 69f1d1a6
......@@ -41,6 +41,10 @@
#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
#define BABBAGE_SD1_CD IMX_GPIO_NR(1, 0)
#define BABBAGE_SD1_WP IMX_GPIO_NR(1, 1)
#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
......@@ -142,6 +146,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
MX51_PAD_GPIO1_0__GPIO1_0,
MX51_PAD_GPIO1_1__GPIO1_1,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
......@@ -150,6 +156,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
MX51_PAD_GPIO1_6__GPIO1_6,
MX51_PAD_GPIO1_5__GPIO1_5,
/* eCSPI1 */
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
......@@ -331,6 +339,16 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};
static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
.cd_gpio = BABBAGE_SD1_CD,
.wp_gpio = BABBAGE_SD1_WP,
};
static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
.cd_gpio = BABBAGE_SD2_CD,
.wp_gpio = BABBAGE_SD2_WP,
};
/*
* Board specific initialization.
*/
......@@ -376,8 +394,8 @@ static void __init mx51_babbage_init(void)
mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, NULL);
imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
......
arch/arm/mach-mx5/board-mx53_ard.c 0 → 100644
View file @ 69f1d1a6
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "crm_regs.h"
#include "devices-imx53.h"
#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
#define ARD_HOME IMX_GPIO_NR(5, 10)
#define ARD_BACK IMX_GPIO_NR(5, 11)
#define ARD_PROG IMX_GPIO_NR(5, 12)
#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
static iomux_v3_cfg_t mx53_ard_pads[] = {
/* UART1 */
MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
/* WEIM for CS1 */
MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
MX53_PAD_EIM_D16__EMI_WEIM_D_16,
MX53_PAD_EIM_D17__EMI_WEIM_D_17,
MX53_PAD_EIM_D18__EMI_WEIM_D_18,
MX53_PAD_EIM_D19__EMI_WEIM_D_19,
MX53_PAD_EIM_D20__EMI_WEIM_D_20,
MX53_PAD_EIM_D21__EMI_WEIM_D_21,
MX53_PAD_EIM_D22__EMI_WEIM_D_22,
MX53_PAD_EIM_D23__EMI_WEIM_D_23,
MX53_PAD_EIM_D24__EMI_WEIM_D_24,
MX53_PAD_EIM_D25__EMI_WEIM_D_25,
MX53_PAD_EIM_D26__EMI_WEIM_D_26,
MX53_PAD_EIM_D27__EMI_WEIM_D_27,
MX53_PAD_EIM_D28__EMI_WEIM_D_28,
MX53_PAD_EIM_D29__EMI_WEIM_D_29,
MX53_PAD_EIM_D30__EMI_WEIM_D_30,
MX53_PAD_EIM_D31__EMI_WEIM_D_31,
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
MX53_PAD_EIM_OE__EMI_WEIM_OE,
MX53_PAD_EIM_RW__EMI_WEIM_RW,
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
/* SDHC1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
MX53_PAD_GPIO_1__GPIO1_1,
MX53_PAD_GPIO_9__GPIO1_9,
/* I2C2 */
MX53_PAD_EIM_EB2__I2C2_SCL,
MX53_PAD_KEY_ROW3__I2C2_SDA,
/* I2C3 */
MX53_PAD_GPIO_3__I2C3_SCL,
MX53_PAD_GPIO_16__I2C3_SDA,
/* GPIO */
MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
};
#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
{ \
.gpio = gpio_num, \
.type = EV_KEY, \
.code = ev_code, \
.active_low = act_low, \
.desc = "btn " descr, \
.wakeup = wake, \
}
static struct gpio_keys_button ard_buttons[] = {
GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
};
static const struct gpio_keys_platform_data ard_button_data __initconst = {
.buttons = ard_buttons,
.nbuttons = ARRAY_SIZE(ard_buttons),
};
static struct resource ard_smsc911x_resources[] = {
{
.start = MX53_CS1_64MB_BASE_ADDR,
.end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
},
{
.start = gpio_to_irq(ARD_ETHERNET_INT_B),
.end = gpio_to_irq(ARD_ETHERNET_INT_B),
.flags = IORESOURCE_IRQ,
},
};
struct smsc911x_platform_config ard_smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_32BIT,
};
static struct platform_device ard_smsc_lan9220_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(ard_smsc911x_resources),
.resource = ard_smsc911x_resources,
.dev = {
.platform_data = &ard_smsc911x_config,
},
};
static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
.cd_gpio = ARD_SD1_CD,
.wp_gpio = ARD_SD1_WP,
};
static struct imxi2c_platform_data mx53_ard_i2c2_data = {
.bitrate = 50000,
};
static struct imxi2c_platform_data mx53_ard_i2c3_data = {
.bitrate = 400000,
};
static void __init mx53_ard_io_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
ARRAY_SIZE(mx53_ard_pads));
gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
gpio_direction_input(ARD_ETHERNET_INT_B);
gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
gpio_direction_output(ARD_I2CPORTEXP_B, 1);
}
/* Config CS1 settings for ethernet controller */
static int weim_cs_config(void)
{
u32 reg;
void __iomem *weim_base, *iomuxc_base;
weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
if (!weim_base)
return -ENOMEM;
iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
if (!iomuxc_base)
return -ENOMEM;
/* CS1 timings for LAN9220 */
writel(0x20001, (weim_base + 0x18));
writel(0x0, (weim_base + 0x1C));
writel(0x16000202, (weim_base + 0x20));
writel(0x00000002, (weim_base + 0x24));
writel(0x16002082, (weim_base + 0x28));
writel(0x00000000, (weim_base + 0x2C));
writel(0x00000000, (weim_base + 0x90));
/* specify 64 MB on CS1 and CS0 on GPR1 */
reg = readl(iomuxc_base + 0x4);
reg &= ~0x3F;
reg |= 0x1B;
writel(reg, (iomuxc_base + 0x4));
iounmap(iomuxc_base);
iounmap(weim_base);
return 0;
}
static struct platform_device *devices[] __initdata = {
&ard_smsc_lan9220_device,
};
static void __init mx53_ard_board_init(void)
{
imx53_soc_init();
imx53_add_imx_uart(0, NULL);
mx53_ard_io_init();
weim_cs_config();
platform_add_devices(devices, ARRAY_SIZE(devices));
imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
imx_add_gpio_keys(&ard_button_data);
}
static void __init mx53_ard_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_ard_timer = {
.init = mx53_ard_timer_init,
};
MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.timer = &mx53_ard_timer,
.init_machine = mx53_ard_board_init,
MACHINE_END
arch/arm/mach-mx5/board-mx53_evk.c
View file @ 69f1d1a6
......@@ -35,6 +35,7 @@
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#define MX53EVK_LED IMX_GPIO_NR(7, 7)
#include "crm_regs.h"
#include "devices-imx53.h"
......@@ -58,12 +59,27 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
/* ecspi chip select lines */
MX53_PAD_EIM_EB2__GPIO2_30,
MX53_PAD_EIM_D19__GPIO3_19,
/* LED */
MX53_PAD_PATA_DA_1__GPIO7_7,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct gpio_led mx53evk_leds[] __initconst = {
{
.name = "green",
.default_trigger = "heartbeat",
.gpio = MX53EVK_LED,
},
};
static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
.leds = mx53evk_leds,
.num_leds = ARRAY_SIZE(mx53evk_leds),
};
static inline void mx53_evk_init_uart(void)
{
imx53_add_imx_uart(0, NULL);
......@@ -135,6 +151,7 @@ static void __init mx53_evk_board_init(void)
ARRAY_SIZE(mx53_evk_spi_board_info));
imx53_add_ecspi(0, &mx53_evk_spi_data);
imx53_add_imx2_wdt(0, NULL);
gpio_led_register_device(-1, &mx53evk_leds_data);
}
static void __init mx53_evk_timer_init(void)
......
arch/arm/mach-mx5/board-mx53_loco.c
View file @ 69f1d1a6
......@@ -38,6 +38,10 @@
#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define LOCO_LED IMX_GPIO_NR(7, 7)
#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
static iomux_v3_cfg_t mx53_loco_pads[] = {
/* FEC */
......@@ -70,6 +74,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
......@@ -163,7 +169,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
MX53_PAD_GPIO_7__SPDIF_PLOCK,
MX53_PAD_GPIO_17__SPDIF_OUT1,
/* GPIO */
MX53_PAD_PATA_DA_1__GPIO7_7,
MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
MX53_PAD_PATA_DA_2__GPIO7_8,
MX53_PAD_PATA_DATA5__GPIO2_5,
MX53_PAD_PATA_DATA6__GPIO2_6,
......@@ -202,6 +208,15 @@ static const struct gpio_keys_platform_data loco_button_data __initconst = {
.nbuttons = ARRAY_SIZE(loco_buttons),
};
static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
.cd_gpio = LOCO_SD1_CD,
};
static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
.cd_gpio = LOCO_SD3_CD,
.wp_gpio = LOCO_SD3_WP,
};
static inline void mx53_loco_fec_reset(void)
{
int ret;
......@@ -225,6 +240,19 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
.bitrate = 100000,
};
static const struct gpio_led mx53loco_leds[] __initconst = {
{
.name = "green",
.default_trigger = "heartbeat",
.gpio = LOCO_LED,
},
};
static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
.leds = mx53loco_leds,
.num_leds = ARRAY_SIZE(mx53loco_leds),
};
static void __init mx53_loco_board_init(void)
{
imx53_soc_init();
......@@ -237,9 +265,10 @@ static void __init mx53_loco_board_init(void)
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(2, NULL);
imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
imx_add_gpio_keys(&loco_button_data);
gpio_led_register_device(-1, &mx53loco_leds_data);
}
static void __init mx53_loco_timer_init(void)
......
arch/arm/mach-mx5/clock-mx51-mx53.c
View file @ 69f1d1a6
......@@ -1254,12 +1254,20 @@ DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, &ipg_clk, &aips_tz1_clk);
DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
NULL, NULL, &ipg_clk, &spba_clk);
DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
NULL, NULL, &ipg_clk, &spba_clk);
DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &ipg_clk, &spba_clk);
DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, &uart_root_clk, &uart4_ipg_clk);
DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
NULL, NULL, &uart_root_clk, &uart5_ipg_clk);
/* GPT */
DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
......@@ -1279,6 +1287,8 @@ DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
NULL, NULL, &ipg_perclk, NULL);
DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
NULL, NULL, &ipg_perclk, NULL);
/* FEC */
DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
......@@ -1463,11 +1473,14 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK("fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
......@@ -1479,6 +1492,11 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
_REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
_REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
};
static void clk_tree_init(void)
......
arch/arm/mach-mx5/crm_regs.h
View file @ 69f1d1a6
......@@ -114,6 +114,8 @@
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
/* Define the bits in register CCR */
......
arch/arm/mach-mx5/devices-imx53.h
View file @ 69f1d1a6
......@@ -32,3 +32,11 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
#define imx53_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
#define imx53_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
arch/arm/mach-mx5/mm.c
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arch/arm/mach-mxs/Kconfig
View file @ 69f1d1a6
......@@ -41,6 +41,7 @@ config MACH_MX23EVK
config MACH_MX28EVK
bool "Support MX28EVK Platform"
select SOC_IMX28
select LEDS_GPIO_REGISTER
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_FEC
......@@ -60,6 +61,7 @@ config MODULE_TX28
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_FEC
select MXS_HAVE_PLATFORM_MXS_I2C
select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXS_PWM
config MACH_TX28
......
arch/arm/mach-mxs/mach-mx28evk.c
View file @ 69f1d1a6
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arch/arm/mach-mxs/mach-tx28.c
View file @ 69f1d1a6
......@@ -139,6 +139,11 @@ static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
},
};
static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
.wp_gpio = -EINVAL,
.flags = SLOTF_4_BIT_CAPABLE,
};
static void __init tx28_stk5v3_init(void)
{
mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
......@@ -155,6 +160,7 @@ static void __init tx28_stk5v3_init(void)
mx28_add_mxs_i2c(0);
i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
}
static void __init tx28_timer_init(void)
......
arch/arm/mach-pxa/balloon3.c
View file @ 69f1d1a6
......@@ -825,6 +825,7 @@ MACHINE_START(BALLOON3, "Balloon3")
.map_io = balloon3_map_io,
.nr_irqs = BALLOON3_NR_IRQS,
.init_irq = balloon3_init_irq,
.handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = balloon3_init,
.boot_params = PLAT_PHYS_OFFSET + 0x100,
......
arch/arm/mach-pxa/capc7117.c
View file @ 69f1d1a6
......@@ -151,6 +151,7 @@ MACHINE_START(CAPC7117,
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = capc7117_init
MACHINE_END
arch/arm/mach-pxa/clock.c
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arch/arm/mach-pxa/clock.h
View file @ 69f1d1a6
......@@ -5,6 +5,7 @@ struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
int (*setrate)(struct clk *, unsigned long);
};
struct clk {
......
arch/arm/mach-pxa/cm-x2xx.c
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