Commit 6d1c2448 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As usual, the bulk of this release is again DT file contents.

  There's a huge number of changes here, and it's challenging to give a
  crisp overview of just what is in here.  To start with:

  New boards:

   - TI-based DM3730 from LogicPD (Torpedo)
   - Cosmic+ M4 (nommu) initial support (Freescale Vybrid)
   - Raspberry Pi 2 DT files
   - Watchdog on Meson8b
   - Veyron-mickey (ASUS Chromebit) DTS
   - Rockchip rk3228 SoC and eval board
   - Sigma Designs Tango4

  Improvements:

   - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files
   - Misc new devices for Rockchip rk3036 and rk3288
   - Allwinner updates for misc SoCs and systems

  ... and a _large_ number of other changes across the field.  Devices
  added to SoC DTSI and board DTS files for a number of SoC vendors, new
  product boards on already-supported SoCs, cleanups and refactorings of
  existing DTS/DTSI files and a bunch of other changes"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits)
  ARM: dts: compulab: add new board description
  ARM: versatile: add the syscon LEDs to the DT
  dts: vt8500: Fix errors in SDHC node for WM8505
  ARM: dts: imx6q: clean up unused ipu2grp
  ARM: dts: silk: Add compatible property to "partitions" node
  ARM: dts: gose: Add compatible property to "partitions" node
  ARM: dts: porter: Add compatible property to "partitions" node
  ARM: dts: koelsch: Add compatible property to "partitions" node
  ARM: dts: lager: Add compatible property to "partitions" node
  ARM: dts: bockw: Add compatible property to "partitions" node
  ARM: dts: meson8b: Add watchdog node
  Documentation: watchdog: Add new bindings for meson8b
  ARM: meson: Add status LED for Odroid-C1
  ARM: dts: uniphier: fix a typo in comment block
  ARM: bcm2835: Add the auxiliary clocks to the device tree.
  ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B
  ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT.
  ARM: bcm2835: Split the DT for peripherals from the DT for the CPU
  ARM: realview: set up cache correctly on the PB11MPCore
  ARM: dts: Unify G2D device node with other devices on exynos4
  ...
parents 1305eda7 4dd041b6
...@@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties: ...@@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties:
Required root node property: Required root node property:
bcm4708
compatible = "brcm,bcm4708"; compatible = "brcm,bcm4708";
bcm4709
compatible = "brcm,bcm4709";
bcm53012
compatible = "brcm,bcm53012";
Broadcom Northstar Plus SoC CPU Enable Method
---------------------------------------------
This binding defines the enable method used for starting secondary
CPU in the following Broadcom SoCs:
BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
The enable method is specified by defining the following required
properties in the corresponding secondary "cpu" device tree node:
- enable-method = "brcm,bcm-nsp-smp";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register which should hold the common
entry point for a secondary CPU. This entry is cpu node specific
and should be added per cpu. E.g., in case of NSP (BCM58625) which
is a dual core CPU SoC, this entry should be added to cpu1 node.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
enable-method = "brcm,bcm-nsp-smp";
secondary-boot-reg = <0xffff042c>;
reg = <1>;
};
};
CompuLab SB-SOM is a multi-module baseboard capable of carrying:
- CM-T43
- CM-T54
- CM-QS600
- CL-SOM-AM57x
- CL-SOM-iMX7
modules with minor modifications to the SB-SOM assembly.
Required root node properties:
- compatible = should be "compulab,sb-som"
Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
Required root node properties:
- compatible = "compulab,cl-som-imx7", "fsl,imx7d";
Compulab SBC-iMX7 is a single board computer based on the
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
the CL-SOM-iMX7 System-on-Module providing most of the functions,
and SB-SOM-iMX7 carrier board providing additional peripheral
functions and connectors.
Required root node properties:
- compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
...@@ -192,6 +192,7 @@ nodes to be present and contain the properties described below. ...@@ -192,6 +192,7 @@ nodes to be present and contain the properties described below.
"allwinner,sun8i-a23" "allwinner,sun8i-a23"
"arm,psci" "arm,psci"
"arm,realview-smp" "arm,realview-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15" "brcm,brahma-b15"
"marvell,armada-375-smp" "marvell,armada-375-smp"
"marvell,armada-380-smp" "marvell,armada-380-smp"
......
...@@ -24,6 +24,8 @@ board. Currently known boards are: ...@@ -24,6 +24,8 @@ board. Currently known boards are:
"buffalo,lswxl" "buffalo,lswxl"
"buffalo,lsxhl" "buffalo,lsxhl"
"buffalo,lsxl" "buffalo,lsxl"
"cloudengines,pogo02"
"cloudengines,pogoplugv4"
"dlink,dns-320" "dlink,dns-320"
"dlink,dns-320-a1" "dlink,dns-320-a1"
"dlink,dns-325" "dlink,dns-325"
......
...@@ -6,6 +6,7 @@ following property: ...@@ -6,6 +6,7 @@ following property:
Required root node property: Required root node property:
compatible: Must contain one of compatible: Must contain one of
"mediatek,mt2701"
"mediatek,mt6580" "mediatek,mt6580"
"mediatek,mt6589" "mediatek,mt6589"
"mediatek,mt6592" "mediatek,mt6592"
...@@ -17,6 +18,9 @@ compatible: Must contain one of ...@@ -17,6 +18,9 @@ compatible: Must contain one of
Supported boards: Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
- Evaluation board for MT6580: - Evaluation board for MT6580:
Required root node properties: Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
......
...@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. ...@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Also it uses the common reset controller binding from Also it uses the common reset controller binding from
Documentation/devicetree/bindings/reset/reset.txt. Documentation/devicetree/bindings/reset/reset.txt.
The available reset outputs are defined in The available reset outputs are defined in
dt-bindings/reset-controller/mt*-resets.h dt-bindings/reset/mt*-resets.h
Example: Example:
......
...@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h. ...@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Also it uses the common reset controller binding from Also it uses the common reset controller binding from
Documentation/devicetree/bindings/reset/reset.txt. Documentation/devicetree/bindings/reset/reset.txt.
The available reset outputs are defined in The available reset outputs are defined in
dt-bindings/reset-controller/mt*-resets.h dt-bindings/reset/mt*-resets.h
Example: Example:
......
...@@ -138,9 +138,21 @@ Boards: ...@@ -138,9 +138,21 @@ Boards:
- AM335X phyBOARD-WEGA: Single Board Computer dev kit - AM335X phyBOARD-WEGA: Single Board Computer dev kit
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx" compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4
compatible = "compulab,cm-t335", "ti,am33xx"
- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
- OMAP5 EVM : Evaluation Module - OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5" compatible = "ti,omap5-evm", "ti,omap5"
- AM437x CM-T43
compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
- AM437x SBC-T43
compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
- AM43x EPOS EVM - AM43x EPOS EVM
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
...@@ -150,6 +162,12 @@ Boards: ...@@ -150,6 +162,12 @@ Boards:
- AM437x SK EVM: AM437x StarterKit Evaluation Module - AM437x SK EVM: AM437x StarterKit Evaluation Module
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
- AM57XX CL-SOM-AM57x
compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- AM57XX SBC-AM57x
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- DRA742 EVM: Software Development Board for DRA742 - DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
......
Rockchip platforms device tree bindings Rockchip platforms device tree bindings
--------------------------------------- ---------------------------------------
- Kylin RK3036 board:
Required root node properties:
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
- MarsBoard RK3066 board: - MarsBoard RK3066 board:
Required root node properties: Required root node properties:
- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
...@@ -35,6 +39,11 @@ Rockchip platforms device tree bindings ...@@ -35,6 +39,11 @@ Rockchip platforms device tree bindings
Required root node properties: Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288"; - compatible = "netxeon,r89", "rockchip,rk3288";
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
"google,veyron", "rockchip,rk3288";
- Google Jaq (Haier Chromebook 11 and more): - Google Jaq (Haier Chromebook 11 and more):
Required root node properties: Required root node properties:
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
...@@ -49,6 +58,15 @@ Rockchip platforms device tree bindings ...@@ -49,6 +58,15 @@ Rockchip platforms device tree bindings
"google,veyron-jerry-rev3", "google,veyron-jerry", "google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288"; "google,veyron", "rockchip,rk3288";
- Google Mickey (Asus Chromebit CS10):
Required root node properties:
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
"google,veyron-mickey-rev0", "google,veyron-mickey",
"google,veyron", "rockchip,rk3288";
- Google Minnie (Asus Chromebook Flip C100P): - Google Minnie (Asus Chromebook Flip C100P):
Required root node properties: Required root node properties:
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
...@@ -72,3 +90,7 @@ Rockchip platforms device tree bindings ...@@ -72,3 +90,7 @@ Rockchip platforms device tree bindings
- Rockchip R88 board: - Rockchip R88 board:
Required root node properties: Required root node properties:
- compatible = "rockchip,r88", "rockchip,rk3368"; - compatible = "rockchip,r88", "rockchip,rk3368";
- Rockchip RK3228 Evaluation board:
Required root node properties:
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
...@@ -10,10 +10,13 @@ References: ...@@ -10,10 +10,13 @@ References:
Revision r2p0 Revision r2p0
- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
Revision r0p1 Revision r0p1
- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
Manial Revision r2p0
- compatible : Should be: - compatible : Should be:
"arm,cortex-a9-scu" "arm,cortex-a9-scu"
"arm,cortex-a5-scu" "arm,cortex-a5-scu"
"arm,arm11mp-scu"
- reg : Specify the base address and the size of the SCU register window. - reg : Specify the base address and the size of the SCU register window.
......
Technologic Systems Platforms Device Tree Bindings
--------------------------------------------------
TS-4800 board
Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51";
ARM System Controller ICST clocks
The ICS525 and ICS307 oscillators are produced by Integrated Devices
Technology (IDT). ARM integrated these oscillators deeply into their
reference designs by adding special control registers that manage such
oscillators to their system controllers.
The ARM system controller contains logic to serialize and initialize
an ICST clock request after a write to the 32 bit register at an offset
into the system controller. Furthermore, to even be able to alter one of
these frequencies, the system controller must first be unlocked by
writing a special token to another offset in the system controller.
The ICST oscillator must be provided inside a system controller node.
Required properties:
- lock-offset: the offset address into the system controller where the
unlocking register is located
- vco-offset: the offset address into the system controller where the
ICST control register is located (even 32 bit address)
- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
- #clock-cells: must be <0>
- clocks: parent clock, since the ICST needs a parent clock to derive its
frequency from, this attribute is compulsory.
Example:
syscon: syscon@10000000 {
compatible = "syscon";
reg = <0x10000000 0x1000>;
oscclk0: osc0@0c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0c>;
clocks = <&xtal24mhz>;
};
(...)
};
PLL divider based Dove clocks
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
high speed clocks for a number of peripherals. These dividers are part of
the PMU, and thus this node should be a child of the PMU node.
The following clocks are provided:
ID Clock
-------------
0 AXI bus clock
1 GPU clock
2 VMeta clock
3 LCD clock
Required properties:
- compatible : shall be "marvell,dove-divider-clock"
- reg : shall be the register address of the Core PLL and Clock Divider
Control 0 register. This will cover that register, as well as the
Core PLL and Clock Divider Control 1 register. Thus, it will have
a size of 8.
- #clock-cells : from common clock binding; shall be set to 1
divider_clk: core-clock@0064 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
};
...@@ -2,10 +2,9 @@ Device-Tree bindings for drm hdmi driver ...@@ -2,10 +2,9 @@ Device-Tree bindings for drm hdmi driver
Required properties: Required properties:
- compatible: value should be one among the following: - compatible: value should be one among the following:
1) "samsung,exynos5-hdmi" <DEPRECATED> 1) "samsung,exynos4210-hdmi"
2) "samsung,exynos4210-hdmi" 2) "samsung,exynos4212-hdmi"
3) "samsung,exynos4212-hdmi" 3) "samsung,exynos5420-hdmi"
4) "samsung,exynos5420-hdmi"
- reg: physical base address of the hdmi and length of memory mapped - reg: physical base address of the hdmi and length of memory mapped
region. region.
- interrupts: interrupt number to the cpu. - interrupts: interrupt number to the cpu.
......
Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel
Required properties:
- compatible: should be "startek,startek-kd050c"
...@@ -14,6 +14,7 @@ Required properties: ...@@ -14,6 +14,7 @@ Required properties:
"mediatek,mt6582-sysirq" "mediatek,mt6582-sysirq"
"mediatek,mt6580-sysirq" "mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq" "mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
- interrupt-controller : Identifies the node as an interrupt controller - interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in - #interrupt-cells : Use the same format as specified by GIC in
Documentation/devicetree/bindings/arm/gic.txt Documentation/devicetree/bindings/arm/gic.txt
......
...@@ -26,7 +26,11 @@ Example: ...@@ -26,7 +26,11 @@ Example:
ti,pmic-shutdown-controller; ti,pmic-shutdown-controller;
regulators { regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: dcdc1 { dcdc1_reg: dcdc1 {
reg = <0>;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-boot-on; regulator-boot-on;
...@@ -34,6 +38,7 @@ Example: ...@@ -34,6 +38,7 @@ Example:
}; };
dcdc2_reg: dcdc2 { dcdc2_reg: dcdc2 {
reg = <1>;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
...@@ -41,6 +46,7 @@ Example: ...@@ -41,6 +46,7 @@ Example:
}; };
dcdc3_reg: dcc3 { dcdc3_reg: dcc3 {
reg = <2>;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1500000>; regulator-max-microvolt = <1500000>;
regulator-boot-on; regulator-boot-on;
...@@ -48,6 +54,7 @@ Example: ...@@ -48,6 +54,7 @@ Example:
}; };
ldo1_reg: ldo1 { ldo1_reg: ldo1 {
reg = <3>;
regulator-min-microvolt = <1000000>; regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
...@@ -55,6 +62,7 @@ Example: ...@@ -55,6 +62,7 @@ Example:
}; };
ldo2_reg: ldo2 { ldo2_reg: ldo2 {
reg = <4>;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
...@@ -62,6 +70,7 @@ Example: ...@@ -62,6 +70,7 @@ Example:
}; };
ldo3_reg: ldo3 { ldo3_reg: ldo3 {
reg = <5>;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
...@@ -69,6 +78,7 @@ Example: ...@@ -69,6 +78,7 @@ Example:
}; };
ldo4_reg: ldo4 { ldo4_reg: ldo4 {
reg = <6>;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-boot-on; regulator-boot-on;
......
...@@ -2,15 +2,15 @@ ...@@ -2,15 +2,15 @@
Required properties: Required properties:
- compatible should contain: - compatible should contain:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt2701-uart" for MT2701 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
MT6589, MT6582, MT6580, MT6577)
- reg: The base address of the UART register bank. - reg: The base address of the UART register bank.
......
Device Tree bindings for Marvell PMU
Required properties:
- compatible: value should be "marvell,dove-pmu".
May also include "simple-bus" if there are child devices, in which
case the ranges node is required.
- reg: two base addresses and sizes of the PM controller and PMU.
- interrupts: single interrupt number for the PMU interrupt
- interrupt-controller: must be specified as the PMU itself is an
interrupt controller.
- #interrupt-cells: must be 1.
- #reset-cells: must be 1.
- domains: sub-node containing domain descriptions
Optional properties:
- ranges: defines the address mapping for child devices, as per the
standard property of this name. Required when compatible includes
"simple-bus".
Power domain descriptions are listed as child nodes of the "domains"
sub-node. Each domain has the following properties:
Required properties:
- #power-domain-cells: must be 0.
Optional properties:
- marvell,pmu_pwr_mask: specifies the mask value for PMU power register
- marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
- resets: points to the reset manager (PMU node) and reset index.
Example:
pmu: power-management@d0000 {
compatible = "marvell,dove-pmu";
reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
interrupts = <33>;
interrupt-controller;
#interrupt-cells = <1>;
#reset-cells = <1>;
domains {
vpu_domain: vpu-domain {
#power-domain-cells = <0>;
marvell,pmu_pwr_mask = <0x00000008>;
marvell,pmu_iso_mask = <0x00000001>;
resets = <&pmu 16>;
};
gpu_domain: gpu-domain {
#power-domain-cells = <0>;
marvell,pmu_pwr_mask = <0x00000004>;
marvell,pmu_iso_mask = <0x00000002>;
resets = <&pmu 18>;
};
};
};
...@@ -21,6 +21,18 @@ Required properties: ...@@ -21,6 +21,18 @@ Required properties:
These are the clocks which hardware needs to be enabled These are the clocks which hardware needs to be enabled
before enabling certain power domains. before enabling certain power domains.
Optional properties:
- vdec-supply: Power supply for the vdec power domain
- venc-supply: Power supply for the venc power domain
- isp-supply: Power supply for the isp power domain
- mm-supply: Power supply for the mm power domain
- venc_lt-supply: Power supply for the venc_lt power domain
- audio-supply: Power supply for the audio power domain
- usb-supply: Power supply for the usb power domain
- mfg_async-supply: Power supply for the mfg_async power domain
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
Example: Example:
scpsys: scpsys@10006000 { scpsys: scpsys@10006000 {
......
Qualcomm Shared Memory Point 2 Point binding
The Shared Memory Point to Point (SMP2P) protocol facilitates communication of
a single 32-bit value between two processors. Each value has a single writer
(the local side) and a single reader (the remote side). Values are uniquely
identified in the system by the directed edge (local processor ID to remote
processor ID) and a string identifier.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,smp2p"
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: one entry specifying the smp2p notification interrupt
- qcom,ipc:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote end of the smp2p edge:
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,smem:
Usage: required
Value type: <u32 array>
Definition: two identifiers of the inbound and outbound smem items used
for this edge
- qcom,local-pid:
Usage: required
Value type: <u32>
Definition: specifies the identfier of the local endpoint of this edge
- qcom,remote-pid:
Usage: required
Value type: <u32>
Definition: specifies the identfier of the remote endpoint of this edge
= SUBNODES
Each SMP2P pair contain a set of inbound and outbound entries, these are
described in subnodes of the smp2p device node. The node names are not
important.
- qcom,entry-name:
Usage: required
Value type: <string>
Definition: specifies the name of this entry, for inbound entries this
will be used to match against the remotely allocated entry
and for outbound entries this name is used for allocating
entries
- interrupt-controller:
Usage: required for incoming entries
Value type: <empty>
Definition: marks the entry as inbound; the node should be specified
as a two cell interrupt-controller as defined in
"../interrupt-controller/interrupts.txt"
If not specified this node will denote the outgoing entry
- #interrupt-cells:
Usage: required for incoming entries
Value type: <u32>
Definition: must be 2 - denoting the bit in the entry and IRQ flags
- #qcom,state-cells:
Usage: required for outgoing entries
Value type: <u32>
Definition: must be 1 - denoting the bit in the entry
= EXAMPLE
The following example shows the SMP2P setup with the wireless processor,
defined from the 8974 apps processor's point-of-view. It encompasses one
inbound and one outbound entry:
wcnss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <431>, <451>;
interrupts = <0 143 1>;
qcom,ipc = <&apcs 8 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
Qualcomm Shared Memory State Machine
The Shared Memory State Machine facilitates broadcasting of single bit state
information between the processors in a Qualcomm SoC. Each processor is
assigned 32 bits of state that can be modified. A processor can through a
matrix of bitmaps signal subscription of notifications upon changes to a
certain bit owned by a certain remote processor.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,smsm"
- qcom,ipc-N:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the N:th remote processor
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,local-host:
Usage: optional
Value type: <u32>
Definition: identifier of the local processor in the list of hosts, or
in other words specifier of the column in the subscription
matrix representing the local processor
defaults to host 0
- #address-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- #size-cells:
Usage: required
Value type: <u32>
Definition: must be 0
= SUBNODES
Each processor's state bits are described by a subnode of the smsm device node.
Nodes can either be flagged as an interrupt-controller to denote a remote
processor's state bits or the local processors bits. The node names are not
important.
- reg:
Usage: required
Value type: <u32>
Definition: specifies the offset, in words, of the first bit for this
entry
- #qcom,state-cells:
Usage: required for local entry
Value type: <u32>
Definition: must be 1 - denotes bit number
- interrupt-controller:
Usage: required for remote entries
Value type: <empty>
Definition: marks the entry as a interrupt-controller and the state bits
to belong to a remote processor
- #interrupt-cells:
Usage: required for remote entries
Value type: <u32>
Definition: must be 2 - denotes bit number and IRQ flags
- interrupts:
Usage: required for remote entries
Value type: <prop-encoded-array>
Definition: one entry specifying remote IRQ used by the remote processor
to signal changes of its state bits
= EXAMPLE
The following example shows the SMEM setup for controlling properties of the
wireless processor, defined from the 8974 apps processor's point-of-view. It
encompasses one outbound entry and the outgoing interrupt for the wireless
processor.
smsm {
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
qcom,ipc-3 = <&apcs 8 19>;
apps_smsm: apps@0 {
reg = <0>;
#qcom,state-cells = <1>;
};
wcnss_smsm: wcnss@7 {
reg = <7>;
interrupts = <0 144 1>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
...@@ -15,14 +15,32 @@ Recommended properties: ...@@ -15,14 +15,32 @@ Recommended properties:
- spi-max-frequency: Definition as per - spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt Documentation/devicetree/bindings/spi/spi-bus.txt
Optional properties:
- syscon-chipselects: Handle to system control region contains QSPI
chipselect register and offset of that register.
Example: Example:
For am4372:
qspi: qspi@4b300000 { qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi"; compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>; reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap"; reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
spi-max-frequency = <25000000>; spi-max-frequency = <25000000>;
ti,hwmods = "qspi"; ti,hwmods = "qspi";
}; };
For dra7xx:
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>,
<0x5c000000 0x4000000>,
reg-names = "qspi_base", "qspi_mmap";
syscon-chipselects = <&scm_conf 0x558>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <48000000>;
ti,hwmods = "qspi";
};
...@@ -3,6 +3,7 @@ Mediatek MT6577, MT6572 and MT6589 Timers ...@@ -3,6 +3,7 @@ Mediatek MT6577, MT6572 and MT6589 Timers
Required properties: Required properties:
- compatible should contain: - compatible should contain:
* "mediatek,mt2701-timer" for MT2701 compatible timers
* "mediatek,mt6580-timer" for MT6580 compatible timers * "mediatek,mt6580-timer" for MT6580 compatible timers
* "mediatek,mt6589-timer" for MT6589 compatible timers * "mediatek,mt6589-timer" for MT6589 compatible timers
* "mediatek,mt8127-timer" for MT8127 compatible timers * "mediatek,mt8127-timer" for MT8127 compatible timers
......
...@@ -124,6 +124,7 @@ jedec JEDEC Solid State Technology Association ...@@ -124,6 +124,7 @@ jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH karo Ka-Ro electronics GmbH
keymile Keymile GmbH keymile Keymile GmbH
kinetic Kinetic Technologies kinetic Kinetic Technologies
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation kyo Kyocera Corporation
lacie LaCie lacie LaCie
lantiq Lantiq Semiconductor lantiq Lantiq Semiconductor
...@@ -222,11 +223,13 @@ sony Sony Corporation ...@@ -222,11 +223,13 @@ sony Sony Corporation
spansion Spansion Inc. spansion Spansion Inc.
sprd Spreadtrum Communications Inc. sprd Spreadtrum Communications Inc.
st STMicroelectronics st STMicroelectronics
startek Startek
ste ST-Ericsson ste ST-Ericsson
stericsson ST-Ericsson stericsson ST-Ericsson
synology Synology, Inc. synology Synology, Inc.
tbs TBS Technologies tbs TBS Technologies
tcl Toby Churchill Ltd. tcl Toby Churchill Ltd.
technologic Technologic Systems
thine THine Electronics, Inc. thine THine Electronics, Inc.
ti Texas Instruments ti Texas Instruments
tlm Trusted Logic Mobility tlm Trusted Logic Mobility
......
...@@ -2,7 +2,7 @@ Meson SoCs Watchdog timer ...@@ -2,7 +2,7 @@ Meson SoCs Watchdog timer
Required properties: Required properties:
- compatible : should be "amlogic,meson6-wdt" - compatible : should be "amlogic,meson6-wdt" or "amlogic,meson8b-wdt"
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
Example: Example:
......
...@@ -2,7 +2,11 @@ Mediatek SoCs Watchdog timer ...@@ -2,7 +2,11 @@ Mediatek SoCs Watchdog timer
Required properties: Required properties:
- compatible : should be "mediatek,mt6589-wdt" - compatible should contain:
* "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers
* "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701,
MT6589)
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
Example: Example:
......
...@@ -48,8 +48,10 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ ...@@ -48,8 +48,10 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
sama5d34ek.dtb \ sama5d34ek.dtb \
sama5d35ek.dtb \ sama5d35ek.dtb \
sama5d36ek.dtb \ sama5d36ek.dtb \
at91-sama5d4_ma5d4evk.dtb \
at91-sama5d4_xplained.dtb \ at91-sama5d4_xplained.dtb \
at91-sama5d4ek.dtb at91-sama5d4ek.dtb \
at91-vinco.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += \ dtb-$(CONFIG_ARCH_ATLAS6) += \
atlas6-evb.dtb atlas6-evb.dtb
dtb-$(CONFIG_ARCH_ATLAS7) += \ dtb-$(CONFIG_ARCH_ATLAS7) += \
...@@ -60,7 +62,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ ...@@ -60,7 +62,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2835-rpi-b.dtb \ bcm2835-rpi-b.dtb \
bcm2835-rpi-b-rev2.dtb \ bcm2835-rpi-b-rev2.dtb \
bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-a-plus.dtb bcm2835-rpi-a-plus.dtb \
bcm2836-rpi-2-b.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \ bcm4708-asus-rt-ac68u.dtb \
...@@ -75,7 +78,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ ...@@ -75,7 +78,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-asus-rt-ac87u.dtb \ bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \ bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb bcm4709-netgear-r8000.dtb \
bcm94708.dtb \
bcm94709.dtb \
bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \ dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb bcm963138dvt.dtb
dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
...@@ -200,12 +206,14 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ ...@@ -200,12 +206,14 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ns2mini.dtb \ kirkwood-ns2mini.dtb \
kirkwood-nsa310.dtb \ kirkwood-nsa310.dtb \
kirkwood-nsa310a.dtb \ kirkwood-nsa310a.dtb \
kirkwood-nsa325.dtb \
kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a6.dtb \
kirkwood-openblocks_a7.dtb \ kirkwood-openblocks_a7.dtb \
kirkwood-openrd-base.dtb \ kirkwood-openrd-base.dtb \
kirkwood-openrd-client.dtb \ kirkwood-openrd-client.dtb \
kirkwood-openrd-ultimate.dtb \ kirkwood-openrd-ultimate.dtb \
kirkwood-pogo_e02.dtb \ kirkwood-pogo_e02.dtb \
kirkwood-pogoplug-series-4.dtb \
kirkwood-rd88f6192.dtb \ kirkwood-rd88f6192.dtb \
kirkwood-rd88f6281-z0.dtb \ kirkwood-rd88f6281-z0.dtb \
kirkwood-rd88f6281-a.dtb \ kirkwood-rd88f6281-a.dtb \
...@@ -268,7 +276,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ ...@@ -268,7 +276,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
imx51-apf51dev.dtb \ imx51-apf51dev.dtb \
imx51-babbage.dtb \ imx51-babbage.dtb \
imx51-digi-connectcore-jsk.dtb \ imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb imx51-eukrea-mbimxsd51-baseboard.dtb \
imx51-ts4800.dtb
dtb-$(CONFIG_SOC_IMX53) += \ dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \ imx53-ard.dtb \
imx53-m53evk.dtb \ imx53-m53evk.dtb \
...@@ -325,6 +334,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -325,6 +334,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-hummingboard.dtb \ imx6q-hummingboard.dtb \
imx6q-nitrogen6x.dtb \ imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \ imx6q-nitrogen6_max.dtb \
imx6q-novena.dtb \
imx6q-phytec-pbab01.dtb \ imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \ imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \ imx6q-sabreauto.dtb \
...@@ -350,6 +360,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ ...@@ -350,6 +360,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
dtb-$(CONFIG_SOC_IMX6UL) += \ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb imx6ul-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb imx7d-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \ dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \ ls1021a-qds.dtb \
...@@ -359,6 +371,7 @@ dtb-$(CONFIG_SOC_VF610) += \ ...@@ -359,6 +371,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610-colibri-eval-v3.dtb \ vf610-colibri-eval-v3.dtb \
vf610m4-colibri.dtb \ vf610m4-colibri.dtb \
vf610-cosmic.dtb \ vf610-cosmic.dtb \
vf610m4-cosmic.dtb \
vf610-twr.dtb vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += \ dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \ imx23-evk.dtb \
...@@ -452,20 +465,24 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ ...@@ -452,20 +465,24 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
dtb-$(CONFIG_SOC_TI81XX) += \ dtb-$(CONFIG_SOC_TI81XX) += \
dm8148-evm.dtb \ dm8148-evm.dtb \
dm8148-t410.dtb \ dm8148-t410.dtb \
dm8168-evm.dtb dm8168-evm.dtb \
dra62x-j5eco-evm.dtb
dtb-$(CONFIG_SOC_AM33XX) += \ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-baltos-ir5221.dtb \ am335x-baltos-ir5221.dtb \
am335x-base0033.dtb \ am335x-base0033.dtb \
am335x-bone.dtb \ am335x-bone.dtb \
am335x-boneblack.dtb \ am335x-boneblack.dtb \
am335x-bonegreen.dtb \ am335x-bonegreen.dtb \
am335x-sl50.dtb \ am335x-chiliboard.dtb \
am335x-cm-t335.dtb \
am335x-evm.dtb \ am335x-evm.dtb \
am335x-evmsk.dtb \ am335x-evmsk.dtb \
am335x-lxm.dtb \
am335x-nano.dtb \ am335x-nano.dtb \
am335x-pepper.dtb \ am335x-pepper.dtb \
am335x-lxm.dtb \ am335x-shc.dtb \
am335x-chiliboard.dtb \ am335x-sbc-t335.dtb \
am335x-sl50.dtb \
am335x-wega-rdk.dtb am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \ dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-duovero-parlor.dtb \ omap4-duovero-parlor.dtb \
...@@ -478,17 +495,21 @@ dtb-$(CONFIG_ARCH_OMAP4) += \ ...@@ -478,17 +495,21 @@ dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-var-stk-om44.dtb omap4-var-stk-om44.dtb
dtb-$(CONFIG_SOC_AM43XX) += \ dtb-$(CONFIG_SOC_AM43XX) += \
am43x-epos-evm.dtb \ am43x-epos-evm.dtb \
am437x-sk-evm.dtb \ am437x-cm-t43.dtb \
am437x-gp-evm.dtb \
am437x-idk-evm.dtb \ am437x-idk-evm.dtb \
am437x-gp-evm.dtb am437x-sbc-t43.dtb \
am437x-sk-evm.dtb
dtb-$(CONFIG_SOC_OMAP5) += \ dtb-$(CONFIG_SOC_OMAP5) += \
omap5-cm-t54.dtb \ omap5-cm-t54.dtb \
omap5-igep0050.dtb \ omap5-igep0050.dtb \
omap5-sbc-t54.dtb \ omap5-sbc-t54.dtb \
omap5-uevm.dtb omap5-uevm.dtb
dtb-$(CONFIG_SOC_DRA7XX) += \ dtb-$(CONFIG_SOC_DRA7XX) += \
dra7-evm.dtb \
am57xx-beagle-x15.dtb \ am57xx-beagle-x15.dtb \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
dra7-evm.dtb \
dra72-evm.dtb dra72-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-lacie-d2-network.dtb \ orion5x-lacie-d2-network.dtb \
...@@ -502,6 +523,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \ ...@@ -502,6 +523,7 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \
dtb-$(CONFIG_ARCH_QCOM) += \ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \ qcom-apq8064-ifc6410.dtb \
qcom-apq8064-sony-xperia-yuga.dtb \
qcom-apq8074-dragonboard.dtb \ qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \ qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \ qcom-apq8084-mtp.dtb \
...@@ -510,12 +532,16 @@ dtb-$(CONFIG_ARCH_QCOM) += \ ...@@ -510,12 +532,16 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8960-cdp.dtb \ qcom-msm8960-cdp.dtb \
qcom-msm8974-sony-xperia-honami.dtb qcom-msm8974-sony-xperia-honami.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \ rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \ rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \ rk3066a-rayeager.dtb \
rk3188-radxarock.dtb \ rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3288-evb-act8846.dtb \ rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \ rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \ rk3288-firefly-beta.dtb \
...@@ -523,8 +549,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ ...@@ -523,8 +549,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-popmetal.dtb \ rk3288-popmetal.dtb \
rk3288-r89.dtb \ rk3288-r89.dtb \
rk3288-rock2-square.dtb \ rk3288-rock2-square.dtb \
rk3288-veyron-brain.dtb \
rk3288-veyron-jaq.dtb \ rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \ rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \ rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \ rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb rk3288-veyron-speedy.dtb
...@@ -547,7 +575,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ ...@@ -547,7 +575,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7778-bockw.dtb \ r8a7778-bockw.dtb \
r8a7779-marzen.dtb \ r8a7779-marzen.dtb \
r8a7790-lager.dtb \ r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \ r8a7791-koelsch.dtb \
r8a7791-porter.dtb \ r8a7791-porter.dtb \
r8a7793-gose.dtb \ r8a7793-gose.dtb \
...@@ -557,6 +584,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ ...@@ -557,6 +584,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
dtb-$(CONFIG_ARCH_SOCFPGA) += \ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \ socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_de0_sockit.dtb \
socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_sockit.dtb \
...@@ -612,6 +640,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ ...@@ -612,6 +640,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \ sun5i-a10s-wobo-i5.dtb \
sun5i-a13-empire-electronix-d709.dtb \
sun5i-a13-hsg-h702.dtb \ sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-98v-rev2.dtb \ sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino.dtb \
...@@ -638,6 +667,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ ...@@ -638,6 +667,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubietruck.dtb \ sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \ sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \ sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-m3.dtb \ sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \ sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \ sun7i-a20-olimex-som-evb.dtb \
...@@ -660,10 +690,13 @@ dtb-$(CONFIG_MACH_SUN8I) += \ ...@@ -660,10 +690,13 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \ sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb sun8i-a33-sinlinx-sina33.dtb \
sun8i-h3-orangepi-plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \ sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-harmony.dtb \ tegra20-harmony.dtb \
tegra20-iris-512.dtb \ tegra20-iris-512.dtb \
...@@ -748,6 +781,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ ...@@ -748,6 +781,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \ armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \ armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \ armada-385-linksys-cobra.dtb \
armada-388-clearfog.dtb \
armada-388-db.dtb \ armada-388-db.dtb \
armada-388-gp.dtb \ armada-388-gp.dtb \
armada-388-rd.dtb armada-388-rd.dtb
...@@ -771,6 +805,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ ...@@ -771,6 +805,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
dove-dove-db.dtb \ dove-dove-db.dtb \
dove-sbc-a510.dtb dove-sbc-a510.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt2701-evb.dtb \
mt6580-evbp1.dtb \ mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \ mt6589-aquaris5.dtb \
mt6592-evb.dtb \ mt6592-evb.dtb \
......
This diff is collapsed.
...@@ -67,112 +67,112 @@ &am33xx_pinmux { ...@@ -67,112 +67,112 @@ &am33xx_pinmux {
user_leds_s0: user_leds_s0 { user_leds_s0: user_leds_s0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
>; >;
}; };
i2c0_pins: pinmux_i2c0_pins { i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>; >;
}; };
i2c2_pins: pinmux_i2c2_pins { i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>; >;
}; };
uart0_pins: pinmux_uart0_pins { uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>; >;
}; };
clkout2_pin: pinmux_clkout2_pin { clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>; >;
}; };
cpsw_default: cpsw_default { cpsw_default: cpsw_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 */ /* Slave 1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
>; >;
}; };
cpsw_sleep: cpsw_sleep { cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 reset value */ /* Slave 1 reset value */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>; >;
}; };
davinci_mdio_default: davinci_mdio_default { davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO */ /* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>; >;
}; };
davinci_mdio_sleep: davinci_mdio_sleep { davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO reset value */ /* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>; >;
}; };
mmc1_pins: pinmux_mmc1_pins { mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
>; >;
}; };
emmc_pins: pinmux_emmc_pins { emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>; >;
}; };
}; };
...@@ -285,10 +285,8 @@ cape3_data: cape_data@0 { ...@@ -285,10 +285,8 @@ cape3_data: cape_data@0 {
}; };
}; };
/include/ "tps65217.dtsi"
&tps { &tps {
compatible = "ti,tps65217";
/* /*
* Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
* mode") at poweroff. Most BeagleBone versions do not support RTC-only * mode") at poweroff. Most BeagleBone versions do not support RTC-only
...@@ -309,12 +307,17 @@ &tps { ...@@ -309,12 +307,17 @@ &tps {
ti,pmic-shutdown-controller; ti,pmic-shutdown-controller;
regulators { regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 { dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr"; regulator-name = "vdds_dpr";
regulator-always-on; regulator-always-on;
}; };
dcdc2_reg: regulator@1 { dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu"; regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -324,6 +327,7 @@ dcdc2_reg: regulator@1 { ...@@ -324,6 +327,7 @@ dcdc2_reg: regulator@1 {
}; };
dcdc3_reg: regulator@2 { dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core"; regulator-name = "vdd_core";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -333,21 +337,25 @@ dcdc3_reg: regulator@2 { ...@@ -333,21 +337,25 @@ dcdc3_reg: regulator@2 {
}; };
ldo1_reg: regulator@3 { ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds"; regulator-name = "vio,vrtc,vdds";
regulator-always-on; regulator-always-on;
}; };
ldo2_reg: regulator@4 { ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux"; regulator-name = "vdd_3v3aux";
regulator-always-on; regulator-always-on;
}; };
ldo3_reg: regulator@5 { ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8"; regulator-name = "vdd_1v8";
regulator-always-on; regulator-always-on;
}; };
ldo4_reg: regulator@6 { ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3a"; regulator-name = "vdd_3v3a";
regulator-always-on; regulator-always-on;
}; };
......
...@@ -36,32 +36,32 @@ &mmc2 { ...@@ -36,32 +36,32 @@ &mmc2 {
&am33xx_pinmux { &am33xx_pinmux {
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */
0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>; >;
}; };
nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */
>; >;
}; };
}; };
......
...@@ -36,8 +36,8 @@ &mmc2 { ...@@ -36,8 +36,8 @@ &mmc2 {
&am33xx_pinmux { &am33xx_pinmux {
uart2_pins: uart2_pins { uart2_pins: uart2_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
>; >;
}; };
}; };
......
...@@ -37,26 +37,26 @@ led1 { ...@@ -37,26 +37,26 @@ led1 {
&am33xx_pinmux { &am33xx_pinmux {
usb1_drvvbus: usb1_drvvbus { usb1_drvvbus: usb1_drvvbus {
pinctrl-single,pins = < pinctrl-single,pins = <
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
>; >;
}; };
sd_pins: pinmux_sd_card { sd_pins: pinmux_sd_card {
pinctrl-single,pins = < pinctrl-single,pins = <
0xf0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0xf4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0xf8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0xfc (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>; >;
}; };
led_gpio_pins: led_gpio_pins { led_gpio_pins: led_gpio_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1e4 (PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
0x1e8 (PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
>; >;
}; };
}; };
......
...@@ -29,81 +29,81 @@ &am33xx_pinmux { ...@@ -29,81 +29,81 @@ &am33xx_pinmux {
i2c0_pins: pinmux_i2c0_pins { i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>; >;
}; };
uart0_pins: pinmux_uart0_pins { uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>; >;
}; };
cpsw_default: cpsw_default { cpsw_default: cpsw_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 */ /* Slave 1 */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
>; >;
}; };
cpsw_sleep: cpsw_sleep { cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 reset value */ /* Slave 1 reset value */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>; >;
}; };
davinci_mdio_default: davinci_mdio_default { davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* mdio_data.mdio_data */ /* mdio_data.mdio_data */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */ /* mdio_clk.mdio_clk */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>; >;
}; };
davinci_mdio_sleep: davinci_mdio_sleep { davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO reset value */ /* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>; >;
}; };
nandflash_pins: nandflash_pins { nandflash_pins: nandflash_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>; >;
}; };
}; };
...@@ -128,16 +128,21 @@ tps: tps@24 { ...@@ -128,16 +128,21 @@ tps: tps@24 {
}; };
/include/ "tps65217.dtsi"
&tps { &tps {
compatible = "ti,tps65217";
regulators { regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 { dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr"; regulator-name = "vdds_dpr";
regulator-always-on; regulator-always-on;
}; };
dcdc2_reg: regulator@1 { dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu"; regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -147,6 +152,7 @@ dcdc2_reg: regulator@1 { ...@@ -147,6 +152,7 @@ dcdc2_reg: regulator@1 {
}; };
dcdc3_reg: regulator@2 { dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core"; regulator-name = "vdd_core";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -156,24 +162,28 @@ dcdc3_reg: regulator@2 { ...@@ -156,24 +162,28 @@ dcdc3_reg: regulator@2 {
}; };
ldo1_reg: regulator@3 { ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds"; regulator-name = "vio,vrtc,vdds";
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo2_reg: regulator@4 { ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux"; regulator-name = "vdd_3v3aux";
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo3_reg: regulator@5 { ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8"; regulator-name = "vdd_1v8";
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
}; };
ldo4_reg: regulator@6 { ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3d"; regulator-name = "vdd_3v3d";
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -46,109 +46,109 @@ vmmcsd_fixed: fixedregulator@1 { ...@@ -46,109 +46,109 @@ vmmcsd_fixed: fixedregulator@1 {
&am33xx_pinmux { &am33xx_pinmux {
mmc1_pins: pinmux_mmc1_pins { mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
>; >;
}; };
i2c0_pins: pinmux_i2c0_pins { i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>; >;
}; };
cpsw_default: cpsw_default { cpsw_default: cpsw_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 */ /* Slave 1 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */ AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */
/* Slave 2 */ /* Slave 2 */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
>; >;
}; };
cpsw_sleep: cpsw_sleep { cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* Slave 1 reset value */ /* Slave 1 reset value */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */ AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */
/* Slave 2 reset value*/ /* Slave 2 reset value*/
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */ AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */ AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */ AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */
>; >;
}; };
davinci_mdio_default: davinci_mdio_default { davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO */ /* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>; >;
}; };
davinci_mdio_sleep: davinci_mdio_sleep { davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO reset value */ /* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>; >;
}; };
emmc_pins: pinmux_emmc_pins { emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>; >;
}; };
uart0_pins: pinmux_uart0_pins { uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>; >;
}; };
}; };
......
This diff is collapsed.
This diff is collapsed.
...@@ -56,22 +56,22 @@ &sham { ...@@ -56,22 +56,22 @@ &sham {
&am33xx_pinmux { &am33xx_pinmux {
ethernet0_pins: pinmux_ethernet0 { ethernet0_pins: pinmux_ethernet0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>; >;
}; };
mdio_pins: pinmux_mdio { mdio_pins: pinmux_mdio {
pinctrl-single,pins = < pinctrl-single,pins = <
/* MDIO */ /* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>; >;
}; };
}; };
...@@ -103,8 +103,8 @@ &phy_sel { ...@@ -103,8 +103,8 @@ &phy_sel {
&am33xx_pinmux { &am33xx_pinmux {
i2c0_pins: pinmux_i2c0 { i2c0_pins: pinmux_i2c0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>; >;
}; };
}; };
...@@ -137,20 +137,20 @@ i2c_rtc: rtc@68 { ...@@ -137,20 +137,20 @@ i2c_rtc: rtc@68 {
&am33xx_pinmux { &am33xx_pinmux {
nandflash_pins: pinmux_nandflash { nandflash_pins: pinmux_nandflash {
pinctrl-single,pins = < pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>; >;
}; };
}; };
...@@ -324,10 +324,10 @@ vmmc_reg: regulator@12 { ...@@ -324,10 +324,10 @@ vmmc_reg: regulator@12 {
&am33xx_pinmux { &am33xx_pinmux {
spi0_pins: pinmux_spi0 { spi0_pins: pinmux_spi0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>; >;
}; };
}; };
......
/*
* am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335
*
* Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am335x-cm-t335.dts"
/ {
model = "CompuLab CM-T335 on SB-T335";
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx";
/* DRM display driver */
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
/* Timing selection performed by U-Boot */
timing0: lcd {/* 800x480p62 */
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <39>;
hback-porch = <39>;
hsync-len = <47>;
vback-porch = <29>;
vfront-porch = <13>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
};
timing1: dvi { /* 1024x768p60 */
clock-frequency = <65000000>;
hactive = <1024>;
hfront-porch = <24>;
hback-porch = <160>;
hsync-len = <136>;
vactive = <768>;
vfront-porch = <3>;
vback-porch = <29>;
vsync-len = <6>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&am33xx_pinmux {
/* Display */
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
/* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)
/* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
/* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
/* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
/* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)
/* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)
/* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)
/* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)
/* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)
>;
};
lcd_pins_sleep: lcd_pins_sleep {
pinctrl-single,pins = <
/* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)
/* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)
/* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)
/* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)
/* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)
/* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)
/* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)
/* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)
/* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)
/* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)
/* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)
/* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)
/* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)
/* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)
/* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)
/* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)
/* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
};
&i2c0 {
/* GPIO extender */
gpio_ext: pca9555@26 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
dvi_ena {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dvi-enable";
};
lcd_ena {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "lcd-enable";
};
};
};
/* Display */
&lcdc {
status = "okay";
};
This diff is collapsed.
...@@ -375,16 +375,19 @@ &uart4 { ...@@ -375,16 +375,19 @@ &uart4 {
pinctrl-0 = <&uart4_pins>; pinctrl-0 = <&uart4_pins>;
}; };
#include "tps65217.dtsi"
&tps { &tps {
compatible = "ti,tps65217";
ti,pmic-shutdown-controller; ti,pmic-shutdown-controller;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <7>; /* NNMI */ interrupts = <7>; /* NNMI */
regulators { regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 { dcdc1_reg: regulator@0 {
reg = <0>;
/* VDDS_DDR */ /* VDDS_DDR */
regulator-min-microvolt = <1500000>; regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>; regulator-max-microvolt = <1500000>;
...@@ -392,6 +395,7 @@ dcdc1_reg: regulator@0 { ...@@ -392,6 +395,7 @@ dcdc1_reg: regulator@0 {
}; };
dcdc2_reg: regulator@1 { dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu"; regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -401,6 +405,7 @@ dcdc2_reg: regulator@1 { ...@@ -401,6 +405,7 @@ dcdc2_reg: regulator@1 {
}; };
dcdc3_reg: regulator@2 { dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core"; regulator-name = "vdd_core";
regulator-min-microvolt = <925000>; regulator-min-microvolt = <925000>;
...@@ -410,6 +415,7 @@ dcdc3_reg: regulator@2 { ...@@ -410,6 +415,7 @@ dcdc3_reg: regulator@2 {
}; };
ldo1_reg: regulator@3 { ldo1_reg: regulator@3 {
reg = <3>;
/* VRTC / VIO / VDDS*/ /* VRTC / VIO / VDDS*/
regulator-always-on; regulator-always-on;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
...@@ -417,6 +423,7 @@ ldo1_reg: regulator@3 { ...@@ -417,6 +423,7 @@ ldo1_reg: regulator@3 {
}; };
ldo2_reg: regulator@4 { ldo2_reg: regulator@4 {
reg = <4>;
/* VDD_3V3AUX */ /* VDD_3V3AUX */
regulator-always-on; regulator-always-on;
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
...@@ -424,6 +431,7 @@ ldo2_reg: regulator@4 { ...@@ -424,6 +431,7 @@ ldo2_reg: regulator@4 {
}; };
ldo3_reg: regulator@5 { ldo3_reg: regulator@5 {
reg = <5>;
/* VDD_1V8 */ /* VDD_1V8 */
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
...@@ -431,6 +439,7 @@ ldo3_reg: regulator@5 { ...@@ -431,6 +439,7 @@ ldo3_reg: regulator@5 {
}; };
ldo4_reg: regulator@6 { ldo4_reg: regulator@6 {
reg = <6>;
/* VDD_3V3A */ /* VDD_3V3A */
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
......
...@@ -28,8 +28,8 @@ vcc3v3: fixedregulator@1 { ...@@ -28,8 +28,8 @@ vcc3v3: fixedregulator@1 {
&am33xx_pinmux { &am33xx_pinmux {
dcan1_pins: pinmux_dcan1 { dcan1_pins: pinmux_dcan1 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
>; >;
}; };
}; };
...@@ -44,20 +44,20 @@ &dcan1 { ...@@ -44,20 +44,20 @@ &dcan1 {
&am33xx_pinmux { &am33xx_pinmux {
ethernet1_pins: pinmux_ethernet1 { ethernet1_pins: pinmux_ethernet1 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x40 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
0x48 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
0x4c (PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
0x50 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
0x54 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
>; >;
}; };
}; };
...@@ -79,13 +79,13 @@ &mac { ...@@ -79,13 +79,13 @@ &mac {
&am33xx_pinmux { &am33xx_pinmux {
mmc1_pins: pinmux_mmc1 { mmc1_pins: pinmux_mmc1 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
>; >;
}; };
}; };
...@@ -103,17 +103,17 @@ &mmc1 { ...@@ -103,17 +103,17 @@ &mmc1 {
&am33xx_pinmux { &am33xx_pinmux {
uart0_pins: pinmux_uart0 { uart0_pins: pinmux_uart0 {
pinctrl-single,pins = < pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>; >;
}; };
uart1_pins: pinmux_uart1_pins { uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
>; >;
}; };
}; };
......
...@@ -161,6 +161,14 @@ wkup_m3_ipc: wkup_m3_ipc@1324 { ...@@ -161,6 +161,14 @@ wkup_m3_ipc: wkup_m3_ipc@1324 {
mboxes = <&mailbox &mbox_wkupm3>; mboxes = <&mailbox &mbox_wkupm3>;
}; };
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <32>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains { scm_clockdomains: clockdomains {
}; };
}; };
...@@ -174,12 +182,44 @@ intc: interrupt-controller@48200000 { ...@@ -174,12 +182,44 @@ intc: interrupt-controller@48200000 {
}; };
edma: edma@49000000 { edma: edma@49000000 {
compatible = "ti,edma3"; compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>, reg = <0x49000000 0x10000>;
<0x44e10f90 0x40>; reg-names = "edma3_cc";
interrupts = <12 13 14>; interrupts = <12 13 14>;
#dma-cells = <1>; interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <20 21>;
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
}; };
gpio0: gpio@44e07000 { gpio0: gpio@44e07000 {
...@@ -233,7 +273,7 @@ uart0: serial@44e09000 { ...@@ -233,7 +273,7 @@ uart0: serial@44e09000 {
reg = <0x44e09000 0x2000>; reg = <0x44e09000 0x2000>;
interrupts = <72>; interrupts = <72>;
status = "disabled"; status = "disabled";
dmas = <&edma 26>, <&edma 27>; dmas = <&edma 26 0>, <&edma 27 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -244,7 +284,7 @@ uart1: serial@48022000 { ...@@ -244,7 +284,7 @@ uart1: serial@48022000 {
reg = <0x48022000 0x2000>; reg = <0x48022000 0x2000>;
interrupts = <73>; interrupts = <73>;
status = "disabled"; status = "disabled";
dmas = <&edma 28>, <&edma 29>; dmas = <&edma 28 0>, <&edma 29 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -255,7 +295,7 @@ uart2: serial@48024000 { ...@@ -255,7 +295,7 @@ uart2: serial@48024000 {
reg = <0x48024000 0x2000>; reg = <0x48024000 0x2000>;
interrupts = <74>; interrupts = <74>;
status = "disabled"; status = "disabled";
dmas = <&edma 30>, <&edma 31>; dmas = <&edma 30 0>, <&edma 31 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -322,8 +362,8 @@ mmc1: mmc@48060000 { ...@@ -322,8 +362,8 @@ mmc1: mmc@48060000 {
ti,dual-volt; ti,dual-volt;
ti,needs-special-reset; ti,needs-special-reset;
ti,needs-special-hs-handling; ti,needs-special-hs-handling;
dmas = <&edma 24 dmas = <&edma_xbar 24 0 0
&edma 25>; &edma_xbar 25 0 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
interrupts = <64>; interrupts = <64>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
...@@ -335,8 +375,8 @@ mmc2: mmc@481d8000 { ...@@ -335,8 +375,8 @@ mmc2: mmc@481d8000 {
compatible = "ti,omap4-hsmmc"; compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2"; ti,hwmods = "mmc2";
ti,needs-special-reset; ti,needs-special-reset;
dmas = <&edma 2 dmas = <&edma 2 0
&edma 3>; &edma 3 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
interrupts = <28>; interrupts = <28>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
...@@ -474,10 +514,10 @@ spi0: spi@48030000 { ...@@ -474,10 +514,10 @@ spi0: spi@48030000 {
interrupts = <65>; interrupts = <65>;
ti,spi-num-cs = <2>; ti,spi-num-cs = <2>;
ti,hwmods = "spi0"; ti,hwmods = "spi0";
dmas = <&edma 16 dmas = <&edma 16 0
&edma 17 &edma 17 0
&edma 18 &edma 18 0
&edma 19>; &edma 19 0>;
dma-names = "tx0", "rx0", "tx1", "rx1"; dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled"; status = "disabled";
}; };
...@@ -490,10 +530,10 @@ spi1: spi@481a0000 { ...@@ -490,10 +530,10 @@ spi1: spi@481a0000 {
interrupts = <125>; interrupts = <125>;
ti,spi-num-cs = <2>; ti,spi-num-cs = <2>;
ti,hwmods = "spi1"; ti,hwmods = "spi1";
dmas = <&edma 42 dmas = <&edma 42 0
&edma 43 &edma 43 0
&edma 44 &edma 44 0
&edma 45>; &edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1"; dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled"; status = "disabled";
}; };
...@@ -819,6 +859,8 @@ gpmc: gpmc@50000000 { ...@@ -819,6 +859,8 @@ gpmc: gpmc@50000000 {
ti,no-idle-on-init; ti,no-idle-on-init;
reg = <0x50000000 0x2000>; reg = <0x50000000 0x2000>;
interrupts = <100>; interrupts = <100>;
dmas = <&edma 52>;
dma-names = "rxtx";
gpmc,num-cs = <7>; gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>; gpmc,num-waitpins = <2>;
#address-cells = <2>; #address-cells = <2>;
...@@ -831,7 +873,7 @@ sham: sham@53100000 { ...@@ -831,7 +873,7 @@ sham: sham@53100000 {
ti,hwmods = "sham"; ti,hwmods = "sham";
reg = <0x53100000 0x200>; reg = <0x53100000 0x200>;
interrupts = <109>; interrupts = <109>;
dmas = <&edma 36>; dmas = <&edma 36 0>;
dma-names = "rx"; dma-names = "rx";
}; };
...@@ -840,8 +882,8 @@ aes: aes@53500000 { ...@@ -840,8 +882,8 @@ aes: aes@53500000 {
ti,hwmods = "aes"; ti,hwmods = "aes";
reg = <0x53500000 0xa0>; reg = <0x53500000 0xa0>;
interrupts = <103>; interrupts = <103>;
dmas = <&edma 6>, dmas = <&edma 6 0>,
<&edma 5>; <&edma 5 0>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -854,8 +896,8 @@ mcasp0: mcasp@48038000 { ...@@ -854,8 +896,8 @@ mcasp0: mcasp@48038000 {
interrupts = <80>, <81>; interrupts = <80>, <81>;
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 8>, dmas = <&edma 8 2>,
<&edma 9>; <&edma 9 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
...@@ -868,8 +910,8 @@ mcasp1: mcasp@4803C000 { ...@@ -868,8 +910,8 @@ mcasp1: mcasp@4803C000 {
interrupts = <82>, <83>; interrupts = <82>, <83>;
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
status = "disabled"; status = "disabled";
dmas = <&edma 10>, dmas = <&edma 10 2>,
<&edma 11>; <&edma 11 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
......
...@@ -77,7 +77,7 @@ &mmc3 { ...@@ -77,7 +77,7 @@ &mmc3 {
&omap3_pmx_core { &omap3_pmx_core {
tps_pins: pinmux_tps_pins { tps_pins: pinmux_tps_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
>; >;
}; };
}; };
......
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...@@ -127,7 +127,7 @@ i2c@11000 { ...@@ -127,7 +127,7 @@ i2c@11000 {
isl12057: isl12057@68 { isl12057: isl12057@68 {
compatible = "isil,isl12057"; compatible = "isil,isl12057";
reg = <0x68>; reg = <0x68>;
isil,irq2-can-wakeup-machine; wakeup-source;
}; };
g762: g762@3e { g762: g762@3e {
......
...@@ -133,7 +133,7 @@ i2c@11000 { ...@@ -133,7 +133,7 @@ i2c@11000 {
isl12057: isl12057@68 { isl12057: isl12057@68 {
compatible = "isil,isl12057"; compatible = "isil,isl12057";
reg = <0x68>; reg = <0x68>;
isil,irq2-can-wakeup-machine; wakeup-source;
}; };
g762: g762@3e { g762: g762@3e {
......
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...@@ -303,16 +303,6 @@ reg_usb2_1_vbus: v5-vbus1 { ...@@ -303,16 +303,6 @@ reg_usb2_1_vbus: v5-vbus1 {
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
}; };
reg_usb2_1_vbus: v5-vbus1 {
compatible = "regulator-fixed";
regulator-name = "v5.0-vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
reg_sata0: pwr-sata0 { reg_sata0: pwr-sata0 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0"; regulator-name = "pwr_en_sata0";
......
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...@@ -141,7 +141,7 @@ g751: g751@4c { ...@@ -141,7 +141,7 @@ g751: g751@4c {
isl12057: isl12057@68 { isl12057: isl12057@68 {
compatible = "isil,isl12057"; compatible = "isil,isl12057";
reg = <0x68>; reg = <0x68>;
isil,irq2-can-wakeup-machine; wakeup-source;
}; };
}; };
......
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/dts-v1/; /dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi" #include "bcm2835-rpi.dtsi"
/ { / {
......
/dts-v1/; /dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi" #include "bcm2835-rpi.dtsi"
/ { / {
......
/dts-v1/; /dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi" #include "bcm2835-rpi.dtsi"
/ { / {
......
/dts-v1/; /dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi" #include "bcm2835-rpi.dtsi"
/ { / {
......
#include "bcm2835.dtsi"
/ { / {
memory { memory {
reg = <0 0x10000000>; reg = <0 0x10000000>;
......
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...@@ -28,3 +28,11 @@ serial2: serial@1d0d000 { ...@@ -28,3 +28,11 @@ serial2: serial@1d0d000 {
}; };
}; };
}; };
&edma0 {
ti,edma-reserved-slot-ranges = <32 50>;
};
&edma1 {
ti,edma-reserved-slot-ranges = <32 90>;
};
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