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Commit 7552d1b9 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-stm', 'clk-renesas', 'clk-scmi' and 'clk-allwinner' into clk-next 

 - STM32MP257 SoC clk driver
 - Allocate clk_ops dynamically for SCMI clk driver

* clk-stm:
  dt-bindings: clocks: stm32mp25: add access-controllers description
  clk: stm32: introduce clocks for STM32MP257 platform
  dt-bindings: clocks: stm32mp25: add description of all parents
  clk: stm32mp13: use platform device APIs

* clk-renesas:
  clk: renesas: r9a08g045: Add support for power domains
  clk: renesas: rzg2l: Extend power domain support
  dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
  dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
  clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
  clk: renesas: r8a7740: Remove unused div4_clk.flags field
  clk: renesas: r9a07g043: Add clock and reset entry for PLIC
  clk: renesas: r8a779h0: Add INTC-EX clock
  clk: renesas: r8a779h0: Add MSIOF clocks
  clk: renesas: r8a779a0: Fix CANFD parent clock
  clk: rs9: fix wrong default value for clock amplitude
  clk: renesas: r8a779h0: Add timer clocks
  clk: renesas: r8a779h0: Add SCIF clocks
  clk: renesas: r9a07g044: Mark resets array as const
  clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
  clk: renesas: r8a779h0: Add thermal clock
  dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks

* clk-scmi:
  clk: scmi: Add support for get/set duty_cycle operations
  clk: scmi: Add support for re-parenting restricted clocks
  clk: scmi: Add support for rate change restricted clocks
  clk: scmi: Add support for state control restricted clocks
  clk: scmi: Allocate CLK operations dynamically

* clk-allwinner:
  clk: sunxi-ng: fix module autoloading
  clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
  clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
parents 5aabfd91 12b52b83 8beff788 87af9481 19149b31
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Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View file @ 7552d1b9
......@@ -57,7 +57,8 @@ properties:
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
const: 0
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
be used to reference individual CPG power domains.
'#reset-cells':
description:
......@@ -76,6 +77,21 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-cpg
then:
properties:
'#power-domain-cells':
const: 1
else:
properties:
'#power-domain-cells':
const: 0
examples:
- |
cpg: clock-controller@11010000 {
......
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
View file @ 7552d1b9
......@@ -38,14 +38,85 @@ properties:
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
- description: CK_SCMI_ICN_VID Video interconnect bus clock
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
- description: CK_SCMI_FLEXGEN_15 flexgen clock 15
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
- description: CK_SCMI_FLEXGEN_28 flexgen clock 28
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
- description: CK_SCMI_FLEXGEN_32 flexgen clock 32
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
- description: CK_SCMI_FLEXGEN_34 flexgen clock 34
- description: CK_SCMI_FLEXGEN_35 flexgen clock 35
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
- description: CK_SCMI_FLEXGEN_49 flexgen clock 49
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
- description: CK_SCMI_FLEXGEN_59 flexgen clock 59
- description: CK_SCMI_FLEXGEN_60 flexgen clock 60
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
- description: CK_SCMI_PLL3 PLL3 clock
- description: clk_dsi_txbyte DSI byte clock
clock-names:
items:
- const: hse
- const: hsi
- const: msi
- const: lse
- const: lsi
access-controllers:
minItems: 1
maxItems: 2
required:
- compatible
......@@ -53,7 +124,6 @@ required:
- '#clock-cells'
- '#reset-cells'
- clocks
- clock-names
additionalProperties: false
......@@ -66,11 +136,85 @@ examples:
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "msi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_ICN_VID>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_15>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_28>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_32>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_34>,
<&scmi_clk CK_SCMI_FLEXGEN_35>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_49>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_59>,
<&scmi_clk CK_SCMI_FLEXGEN_60>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
};
...
drivers/clk/clk-renesas-pcie.c
View file @ 7552d1b9
......@@ -25,10 +25,12 @@
#define RS9_REG_SS_AMP_0V7 0x1
#define RS9_REG_SS_AMP_0V8 0x2
#define RS9_REG_SS_AMP_0V9 0x3
#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
#define RS9_REG_SS_AMP_MASK 0x3
#define RS9_REG_SS_SSC_100 0
#define RS9_REG_SS_SSC_M025 (1 << 3)
#define RS9_REG_SS_SSC_M050 (3 << 3)
#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
#define RS9_REG_SS_SSC_MASK (3 << 3)
#define RS9_REG_SS_SSC_LOCK BIT(5)
#define RS9_REG_SR 0x2
......@@ -205,8 +207,8 @@ static int rs9_get_common_config(struct rs9_driver_data *rs9)
int ret;
/* Set defaults */
rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
rs9->pll_ssc = RS9_REG_SS_SSC_100;
rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
/* Output clock amplitude */
ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
......@@ -247,13 +249,13 @@ static void rs9_update_config(struct rs9_driver_data *rs9)
int i;
/* If amplitude is non-default, update it. */
if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
rs9->pll_amplitude);
}
/* If SSC is non-default, update it. */
if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
rs9->pll_ssc);
}
......
drivers/clk/clk-scmi.c
View file @ 7552d1b9
......@@ -2,9 +2,10 @@
/*
* System Control and Power Interface (SCMI) Protocol based clock driver
*
* Copyright (C) 2018-2022 ARM Ltd.
* Copyright (C) 2018-2024 ARM Ltd.
*/
#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
......@@ -16,6 +17,17 @@
#define NOT_ATOMIC false
#define ATOMIC true
enum scmi_clk_feats {
SCMI_CLK_ATOMIC_SUPPORTED,
SCMI_CLK_STATE_CTRL_SUPPORTED,
SCMI_CLK_RATE_CTRL_SUPPORTED,
SCMI_CLK_PARENT_CTRL_SUPPORTED,
SCMI_CLK_DUTY_CYCLE_SUPPORTED,
SCMI_CLK_FEATS_COUNT
};
#define SCMI_MAX_CLK_OPS BIT(SCMI_CLK_FEATS_COUNT)
static const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
struct scmi_clk {
......@@ -158,41 +170,44 @@ static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)
return !!enabled;
}
/*
* We can provide enable/disable/is_enabled atomic callbacks only if the
* underlying SCMI transport for an SCMI instance is configured to handle
* SCMI commands in an atomic manner.
*
* When no SCMI atomic transport support is available we instead provide only
* the prepare/unprepare API, as allowed by the clock framework when atomic
* calls are not available.
*
* Two distinct sets of clk_ops are provided since we could have multiple SCMI
* instances with different underlying transport quality, so they cannot be
* shared.
*/
static const struct clk_ops scmi_clk_ops = {
.recalc_rate = scmi_clk_recalc_rate,
.round_rate = scmi_clk_round_rate,
.set_rate = scmi_clk_set_rate,
.prepare = scmi_clk_enable,
.unprepare = scmi_clk_disable,
.set_parent = scmi_clk_set_parent,
.get_parent = scmi_clk_get_parent,
.determine_rate = scmi_clk_determine_rate,
};
static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
int ret;
u32 val;
struct scmi_clk *clk = to_scmi_clk(hw);
static const struct clk_ops scmi_atomic_clk_ops = {
.recalc_rate = scmi_clk_recalc_rate,
.round_rate = scmi_clk_round_rate,
.set_rate = scmi_clk_set_rate,
.enable = scmi_clk_atomic_enable,
.disable = scmi_clk_atomic_disable,
.is_enabled = scmi_clk_atomic_is_enabled,
.set_parent = scmi_clk_set_parent,
.get_parent = scmi_clk_get_parent,
.determine_rate = scmi_clk_determine_rate,
};
ret = scmi_proto_clk_ops->config_oem_get(clk->ph, clk->id,
SCMI_CLOCK_CFG_DUTY_CYCLE,
&val, NULL, false);
if (!ret) {
duty->num = val;
duty->den = 100;
} else {
dev_warn(clk->dev,
"Failed to get duty cycle for clock ID %d\n", clk->id);
}
return ret;
}
static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
int ret;
u32 val;
struct scmi_clk *clk = to_scmi_clk(hw);
/* SCMI OEM Duty Cycle is expressed as a percentage */
val = (duty->num * 100) / duty->den;
ret = scmi_proto_clk_ops->config_oem_set(clk->ph, clk->id,
SCMI_CLOCK_CFG_DUTY_CYCLE,
val, false);
if (ret)
dev_warn(clk->dev,
"Failed to set duty cycle(%u/%u) for clock ID %d\n",
duty->num, duty->den, clk->id);
return ret;
}
static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
const struct clk_ops *scmi_ops)
......@@ -230,17 +245,153 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
return ret;
}
/**
* scmi_clk_ops_alloc() - Alloc and configure clock operations
* @dev: A device reference for devres
* @feats_key: A bitmap representing the desired clk_ops capabilities
*
* Allocate and configure a proper set of clock operations depending on the
* specifically required SCMI clock features.
*
* Return: A pointer to the allocated and configured clk_ops on success,
* or NULL on allocation failure.
*/
static const struct clk_ops *
scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
{
struct clk_ops *ops;
ops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);
if (!ops)
return NULL;
/*
* We can provide enable/disable/is_enabled atomic callbacks only if the
* underlying SCMI transport for an SCMI instance is configured to
* handle SCMI commands in an atomic manner.
*
* When no SCMI atomic transport support is available we instead provide
* only the prepare/unprepare API, as allowed by the clock framework
* when atomic calls are not available.
*/
if (feats_key & BIT(SCMI_CLK_STATE_CTRL_SUPPORTED)) {
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
ops->enable = scmi_clk_atomic_enable;
ops->disable = scmi_clk_atomic_disable;
} else {
ops->prepare = scmi_clk_enable;
ops->unprepare = scmi_clk_disable;
}
}
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))
ops->is_enabled = scmi_clk_atomic_is_enabled;
/* Rate ops */
ops->recalc_rate = scmi_clk_recalc_rate;
ops->round_rate = scmi_clk_round_rate;
ops->determine_rate = scmi_clk_determine_rate;
if (feats_key & BIT(SCMI_CLK_RATE_CTRL_SUPPORTED))
ops->set_rate = scmi_clk_set_rate;
/* Parent ops */
ops->get_parent = scmi_clk_get_parent;
if (feats_key & BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED))
ops->set_parent = scmi_clk_set_parent;
/* Duty cycle */
if (feats_key & BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED)) {
ops->get_duty_cycle = scmi_clk_get_duty_cycle;
ops->set_duty_cycle = scmi_clk_set_duty_cycle;
}
return ops;
}
/**
* scmi_clk_ops_select() - Select a proper set of clock operations
* @sclk: A reference to an SCMI clock descriptor
* @atomic_capable: A flag to indicate if atomic mode is supported by the
* transport
* @atomic_threshold_us: Platform atomic threshold value in microseconds:
* clk_ops are atomic when clock enable latency is less
* than this threshold
* @clk_ops_db: A reference to the array used as a database to store all the
* created clock operations combinations.
* @db_size: Maximum number of entries held by @clk_ops_db
*
* After having built a bitmap descriptor to represent the set of features
* needed by this SCMI clock, at first use it to lookup into the set of
* previously allocated clk_ops to check if a suitable combination of clock
* operations was already created; when no match is found allocate a brand new
* set of clk_ops satisfying the required combination of features and save it
* for future references.
*
* In this way only one set of clk_ops is ever created for each different
* combination that is effectively needed by a driver instance.
*
* Return: A pointer to the allocated and configured clk_ops on success, or
* NULL otherwise.
*/
static const struct clk_ops *
scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
unsigned int atomic_threshold_us,
const struct clk_ops **clk_ops_db, size_t db_size)
{
const struct scmi_clock_info *ci = sclk->info;
unsigned int feats_key = 0;
const struct clk_ops *ops;
/*
* Note that when transport is atomic but SCMI protocol did not
* specify (or support) an enable_latency associated with a
* clock, we default to use atomic operations mode.
*/
if (atomic_capable && ci->enable_latency <= atomic_threshold_us)
feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
if (!ci->state_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_STATE_CTRL_SUPPORTED);
if (!ci->rate_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_RATE_CTRL_SUPPORTED);
if (!ci->parent_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED);
if (ci->extended_config)
feats_key |= BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED);
if (WARN_ON(feats_key >= db_size))
return NULL;
/* Lookup previously allocated ops */
ops = clk_ops_db[feats_key];
if (ops)
return ops;
/* Did not find a pre-allocated clock_ops */
ops = scmi_clk_ops_alloc(sclk->dev, feats_key);
if (!ops)
return NULL;
/* Store new ops combinations */
clk_ops_db[feats_key] = ops;
return ops;
}
static int scmi_clocks_probe(struct scmi_device *sdev)
{
int idx, count, err;
unsigned int atomic_threshold;
bool is_atomic;
unsigned int atomic_threshold_us;
bool transport_is_atomic;
struct clk_hw **hws;
struct clk_hw_onecell_data *clk_data;
struct device *dev = &sdev->dev;
struct device_node *np = dev->of_node;
const struct scmi_handle *handle = sdev->handle;
struct scmi_protocol_handle *ph;
const struct clk_ops *scmi_clk_ops_db[SCMI_MAX_CLK_OPS] = {};
if (!handle)
return -ENODEV;
......@@ -264,7 +415,8 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
clk_data->num = count;
hws = clk_data->hws;
is_atomic = handle->is_transport_atomic(handle, &atomic_threshold);
transport_is_atomic = handle->is_transport_atomic(handle,
&atomic_threshold_us);
for (idx = 0; idx < count; idx++) {
struct scmi_clk *sclk;
......@@ -286,15 +438,17 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
sclk->dev = dev;
/*
* Note that when transport is atomic but SCMI protocol did not
* specify (or support) an enable_latency associated with a
* clock, we default to use atomic operations mode.
* Note that the scmi_clk_ops_db is on the stack, not global,
* because it cannot be shared between mulitple probe-sequences
* to avoid sharing the devm_ allocated clk_ops between multiple
* SCMI clk driver instances.
*/
if (is_atomic &&
sclk->info->enable_latency <= atomic_threshold)
scmi_ops = &scmi_atomic_clk_ops;
else
scmi_ops = &scmi_clk_ops;
scmi_ops = scmi_clk_ops_select(sclk, transport_is_atomic,
atomic_threshold_us,
scmi_clk_ops_db,
ARRAY_SIZE(scmi_clk_ops_db));
if (!scmi_ops)
return -ENOMEM;
/* Initialize clock parent data. */
if (sclk->info->num_parents > 0) {
......@@ -318,8 +472,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
} else {
dev_dbg(dev, "Registered clock:%s%s\n",
sclk->info->name,
scmi_ops == &scmi_atomic_clk_ops ?
" (atomic ops)" : "");
scmi_ops->enable ? " (atomic ops)" : "");
hws[idx] = &sclk->hw;
}
}
......
drivers/clk/renesas/clk-r8a73a4.c
View file @ 7552d1b9
......@@ -30,8 +30,6 @@ struct r8a73a4_cpg {
#define CPG_PLL2HCR 0xe4
#define CPG_PLL2SCR 0xf4
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
unsigned int reg;
......
drivers/clk/renesas/clk-r8a7740.c
View file @ 7552d1b9
......@@ -26,28 +26,25 @@ struct r8a7740_cpg {
#define CPG_USBCKCR 0x8c
#define CPG_FRQCRC 0xe0
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
unsigned int reg;
unsigned int shift;
int flags;
};
static struct div4_clk div4_clks[] = {
{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
{ "hp", CPG_FRQCRB, 4, 0 },
{ "hpp", CPG_FRQCRC, 20, 0 },
{ "usbp", CPG_FRQCRC, 16, 0 },
{ "s", CPG_FRQCRC, 12, 0 },
{ "zb", CPG_FRQCRC, 8, 0 },
{ "m3", CPG_FRQCRC, 4, 0 },
{ "cp", CPG_FRQCRC, 0, 0 },
{ NULL, 0, 0, 0 },
{ "i", CPG_FRQCRA, 20 },
{ "zg", CPG_FRQCRA, 16 },
{ "b", CPG_FRQCRA, 8 },
{ "m1", CPG_FRQCRA, 4 },
{ "hp", CPG_FRQCRB, 4 },
{ "hpp", CPG_FRQCRC, 20 },
{ "usbp", CPG_FRQCRC, 16 },
{ "s", CPG_FRQCRC, 12 },
{ "zb", CPG_FRQCRC, 8 },
{ "m3", CPG_FRQCRC, 4 },
{ "cp", CPG_FRQCRC, 0 },
{ NULL, 0, 0 },
};
static const struct clk_div_table div4_div_table[] = {
......
drivers/clk/renesas/clk-sh73a0.c
View file @ 7552d1b9
......@@ -34,8 +34,6 @@ struct sh73a0_cpg {
#define CPG_DSI0PHYCR 0x6c
#define CPG_DSI1PHYCR 0x70
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
const char *parent;
......
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View file @ 7552d1b9
......@@ -139,7 +139,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
......
drivers/clk/renesas/r8a779h0-cpg-mssr.c
View file @ 7552d1b9
......@@ -184,14 +184,35 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
};
/*
......
drivers/clk/renesas/r9a07g043-cpg.c
View file @ 7552d1b9
......@@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
#endif
};
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
#ifdef CONFIG_ARM64
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0x514, 0),
......@@ -280,9 +280,13 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x5a8, 1),
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0x5ac, 0),
#ifdef CONFIG_RISCV
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
0x608, 0),
#endif
};
static struct rzg2l_reset r9a07g043_resets[] = {
static const struct rzg2l_reset r9a07g043_resets[] = {
#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
......@@ -338,6 +342,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
#ifdef CONFIG_RISCV
DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
#endif
};
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
......@@ -347,6 +355,7 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
#endif
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
};
......
drivers/clk/renesas/r9a07g044-cpg.c
View file @ 7552d1b9
......@@ -368,7 +368,7 @@ static const struct {
#endif
};
static struct rzg2l_reset r9a07g044_resets[] = {
static const struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
......
drivers/clk/renesas/r9a08g045-cpg.c
View file @ 7552d1b9
......@@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
/* Keep always-on domain on the first position for proper domains registration. */
DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
DEF_REG_CONF(0, 0),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("gic", R9A08G045_PD_GIC,
DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("ia55", R9A08G045_PD_IA55,
DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("dmac", R9A08G045_PD_DMAC,
DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("wdt0", R9A08G045_PD_WDT0,
DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
RZG2L_PD_F_NONE),
DEF_PD("eth0", R9A08G045_PD_ETHER0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
RZG2L_PD_F_NONE),
DEF_PD("eth1", R9A08G045_PD_ETHER1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
RZG2L_PD_F_NONE),
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
};
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
......@@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
/* Power domains */
.pm_domains = r9a08g045_pm_domains,
.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
.has_clk_mon_regs = true,
};
drivers/clk/renesas/rzg2l-cpg.c
View file @ 7552d1b9
......@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
* @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
......@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
struct generic_pm_domain genpd;
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
......@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
return true;
}
/**
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
* @onecell_data: cell data
* @domains: generic PM domains
*/
struct rzg2l_cpg_pm_domains {
struct genpd_onecell_data onecell_data;
struct generic_pm_domain *domains[];
};
/**
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
* @genpd: generic PM domain
* @priv: pointer to CPG private data structure
* @conf: CPG PM domain configuration info
* @id: RZ/G2L power domain ID
*/
struct rzg2l_cpg_pd {
struct generic_pm_domain genpd;
struct rzg2l_cpg_priv *priv;
struct rzg2l_cpg_pm_domain_conf conf;
u16 id;
};
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_priv *priv = pd->priv;
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
......@@ -1617,31 +1639,180 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
}
static void rzg2l_cpg_genpd_remove(void *data)
{
struct genpd_onecell_data *celldata = data;
for (unsigned int i = 0; i < celldata->num_domains; i++)
pm_genpd_remove(celldata->domains[i]);
}
static void rzg2l_cpg_genpd_remove_simple(void *data)
{
pm_genpd_remove(data);
}
static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask << 16, priv->base + mstop.off);
return 0;
}
static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
return 0;
}
static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
{
struct dev_power_governor *governor;
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
if (always_on) {
pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
governor = &pm_domain_always_on_gov;
} else {
pd->genpd.power_on = rzg2l_cpg_power_on;
pd->genpd.power_off = rzg2l_cpg_power_off;
governor = &simple_qos_governor;
}
return pm_genpd_init(&pd->genpd, governor, !always_on);
}
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd = &priv->genpd;
struct rzg2l_cpg_pd *pd;
int ret;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = np->name;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd, true);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, &pd->genpd);
}
static struct generic_pm_domain *
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
{
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
struct genpd_onecell_data *genpd = data;
if (spec->args_count != 1)
return ERR_PTR(-EINVAL);
for (unsigned int i = 0; i < genpd->num_domains; i++) {
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
genpd);
if (pd->id == spec->args[0]) {
domain = &pd->genpd;
break;
}
}
return domain;
}
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
{
const struct rzg2l_cpg_info *info = priv->info;
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct rzg2l_cpg_pm_domains *domains;
struct generic_pm_domain *parent;
u32 ncells;
int ret;
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
if (ret)
return ret;
/* For backward compatibility. */
if (!ncells)
return rzg2l_cpg_add_clk_domain(priv);
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
GFP_KERNEL);
if (!domains)
return -ENOMEM;
domains->onecell_data.domains = domains->domains;
domains->onecell_data.num_domains = info->num_pm_domains;
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
struct rzg2l_cpg_pd *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = info->pm_domains[i].name;
pd->conf = info->pm_domains[i].conf;
pd->id = info->pm_domains[i].id;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd, always_on);
if (ret)
return ret;
if (always_on) {
ret = rzg2l_cpg_power_on(&pd->genpd);
if (ret)
return ret;
}
domains->domains[i] = &pd->genpd;
/* Parent should be on the very first entry of info->pm_domains[]. */
if (!i) {
parent = &pd->genpd;
continue;
}
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
if (ret)
return ret;
}
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, genpd);
return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
......@@ -1697,7 +1868,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
error = rzg2l_cpg_add_clk_domain(priv);
error = rzg2l_cpg_add_pm_domains(priv);
if (error)
return error;
......
drivers/clk/renesas/rzg2l-cpg.h
View file @ 7552d1b9
......@@ -27,6 +27,18 @@
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
#define CPG_BUS_ACPU_MSTOP (0xB60)
#define CPG_BUS_MCPU1_MSTOP (0xB64)
#define CPG_BUS_MCPU2_MSTOP (0xB68)
#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
#define CPG_BUS_REG0_MSTOP (0xB7C)
#define CPG_BUS_REG1_MSTOP (0xB80)
#define CPG_BUS_TZCDDR_MSTOP (0xB84)
#define CPG_MHU_MSTOP (0xB88)
#define CPG_BUS_MCPU3_MSTOP (0xB90)
#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
......@@ -234,6 +246,55 @@ struct rzg2l_reset {
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
/**
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
* @off: register offset
* @mask: register mask
*/
struct rzg2l_cpg_reg_conf {
u16 off;
u16 mask;
};
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
/**
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
* @mstop: MSTOP register configuration
*/
struct rzg2l_cpg_pm_domain_conf {
struct rzg2l_cpg_reg_conf mstop;
};
/**
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
* @name: PM domain name
* @conf: PM domain configuration
* @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
* @id: PM domain ID (similar to the ones defined in
* include/dt-bindings/clock/<soc-id>-cpg.h)
*/
struct rzg2l_cpg_pm_domain_init_data {
const char * const name;
struct rzg2l_cpg_pm_domain_conf conf;
u32 flags;
u16 id;
};
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
{ \
.name = (_name), \
.id = (_id), \
.conf = { \
.mstop = (_mstop_conf), \
}, \
.flags = (_flags), \
}
/* Power domain flags. */
#define RZG2L_PD_F_ALWAYS_ON BIT(0)
#define RZG2L_PD_F_NONE (0)
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
......@@ -252,6 +313,8 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
* @pm_domains: PM domains init data array
* @num_pm_domains: Number of PM domains
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
......@@ -278,6 +341,10 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
/* Power domain. */
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
unsigned int num_pm_domains;
bool has_clk_mon_regs;
};
......
drivers/clk/stm32/Kconfig
View file @ 7552d1b9
......@@ -25,5 +25,12 @@ config COMMON_CLK_STM32MP157
help
Support for stm32mp15x SoC family clocks.
config COMMON_CLK_STM32MP257
bool "Clock driver for stm32mp25x clocks"
depends on ARM64 || COMPILE_TEST
default y
help
Support for stm32mp25x SoC family clocks.
endif
drivers/clk/stm32/Makefile
View file @ 7552d1b9
obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
drivers/clk/stm32/clk-stm32-core.c
View file @ 7552d1b9
......@@ -25,7 +25,6 @@ static int stm32_rcc_clock_init(struct device *dev,
{
const struct stm32_rcc_match_data *data = match->data;
struct clk_hw_onecell_data *clk_data = data->hw_clks;
struct device_node *np = dev_of_node(dev);
struct clk_hw **hws;
int n, max_binding;
......@@ -64,7 +63,7 @@ static int stm32_rcc_clock_init(struct device *dev,
hws[cfg_clock->id] = hw;
}
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
}
int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
......@@ -638,7 +637,7 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev,
mux->lock = lock;
mux->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -659,7 +658,7 @@ struct clk_hw *clk_stm32_gate_register(struct device *dev,
gate->lock = lock;
gate->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -680,7 +679,7 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
div->lock = lock;
div->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -701,7 +700,7 @@ struct clk_hw *clk_stm32_composite_register(struct device *dev,
composite->lock = lock;
composite->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......
drivers/clk/stm32/clk-stm32mp13.c
View file @ 7552d1b9
......@@ -1536,77 +1536,16 @@ static const struct of_device_id stm32mp13_match_data[] = {
};
MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
static int stm32mp1_rcc_init(struct device *dev)
{
void __iomem *rcc_base;
int ret = -ENOMEM;
rcc_base = of_iomap(dev_of_node(dev), 0);
if (!rcc_base) {
dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
goto out;
}
ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
out:
if (ret) {
if (rcc_base)
iounmap(rcc_base);
of_node_put(dev_of_node(dev));
}
return ret;
}
static int get_clock_deps(struct device *dev)
{
static const char * const clock_deps_name[] = {
"hsi", "hse", "csi", "lsi", "lse",
};
size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
struct clk **clk_deps;
int i;
clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
if (!clk_deps)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
clock_deps_name[i]);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
return PTR_ERR(clk);
} else {
/* Device gets a reference count on the clock */
clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
clk_put(clk);
}
}
return 0;
}
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret = get_clock_deps(dev);
void __iomem *base;
if (!ret)
ret = stm32mp1_rcc_init(dev);
return ret;
}
static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev_of_node(dev);
base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base)))
return PTR_ERR(base);
for_each_available_child_of_node(np, child)
of_clk_del_provider(child);
return stm32_rcc_init(dev, stm32mp13_match_data, base);
}
static struct platform_driver stm32mp13_rcc_clocks_driver = {
......@@ -1615,7 +1554,6 @@ static struct platform_driver stm32mp13_rcc_clocks_driver = {
.of_match_table = stm32mp13_match_data,
},
.probe = stm32mp1_rcc_clocks_probe,
.remove_new = stm32mp1_rcc_clocks_remove,
};
static int __init stm32mp13_clocks_init(void)
......
drivers/clk/stm32/clk-stm32mp25.c 0 → 100644
View file @ 7552d1b9
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-stm32-core.h"
#include "reset-stm32.h"
#include "stm32mp25_rcc.h"
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
enum {
HSE,
HSI,
MSI,
LSE,
LSI,
HSE_DIV2,
ICN_HS_MCU,
ICN_LS_MCU,
ICN_SDMMC,
ICN_DDR,
ICN_DISPLAY,
ICN_HSL,
ICN_NIC,
ICN_VID,
FLEXGEN_07,
FLEXGEN_08,
FLEXGEN_09,
FLEXGEN_10,
FLEXGEN_11,
FLEXGEN_12,
FLEXGEN_13,
FLEXGEN_14,
FLEXGEN_15,
FLEXGEN_16,
FLEXGEN_17,
FLEXGEN_18,
FLEXGEN_19,
FLEXGEN_20,
FLEXGEN_21,
FLEXGEN_22,
FLEXGEN_23,
FLEXGEN_24,
FLEXGEN_25,
FLEXGEN_26,
FLEXGEN_27,
FLEXGEN_28,
FLEXGEN_29,
FLEXGEN_30,
FLEXGEN_31,
FLEXGEN_32,
FLEXGEN_33,
FLEXGEN_34,
FLEXGEN_35,
FLEXGEN_36,
FLEXGEN_37,
FLEXGEN_38,
FLEXGEN_39,
FLEXGEN_40,
FLEXGEN_41,
FLEXGEN_42,
FLEXGEN_43,
FLEXGEN_44,
FLEXGEN_45,
FLEXGEN_46,
FLEXGEN_47,
FLEXGEN_48,
FLEXGEN_49,
FLEXGEN_50,
FLEXGEN_51,
FLEXGEN_52,
FLEXGEN_53,
FLEXGEN_54,
FLEXGEN_55,
FLEXGEN_56,
FLEXGEN_57,
FLEXGEN_58,
FLEXGEN_59,
FLEXGEN_60,
FLEXGEN_61,
FLEXGEN_62,
FLEXGEN_63,
ICN_APB1,
ICN_APB2,
ICN_APB3,
ICN_APB4,
ICN_APBDBG,
TIMG1,
TIMG2,
PLL3,
DSI_TXBYTE,
};
static const struct clk_parent_data adc12_src[] = {
{ .index = FLEXGEN_46 },
{ .index = ICN_LS_MCU },
};
static const struct clk_parent_data adc3_src[] = {
{ .index = FLEXGEN_47 },
{ .index = ICN_LS_MCU },
{ .index = FLEXGEN_46 },
};
static const struct clk_parent_data usb2phy1_src[] = {
{ .index = FLEXGEN_57 },
{ .index = HSE_DIV2 },
};
static const struct clk_parent_data usb2phy2_src[] = {
{ .index = FLEXGEN_58 },
{ .index = HSE_DIV2 },
};
static const struct clk_parent_data usb3pciphy_src[] = {
{ .index = FLEXGEN_34 },
{ .index = HSE_DIV2 },
};
static struct clk_stm32_gate ck_ker_ltdc;
static const struct clk_parent_data dsiblane_src[] = {
{ .index = DSI_TXBYTE },
{ .hw = &ck_ker_ltdc.hw },
};
static const struct clk_parent_data dsiphy_src[] = {
{ .index = FLEXGEN_28 },
{ .index = HSE },
};
static const struct clk_parent_data lvdsphy_src[] = {
{ .index = FLEXGEN_32 },
{ .index = HSE },
};
static const struct clk_parent_data dts_src[] = {
{ .index = HSI },
{ .index = HSE },
{ .index = MSI },
};
static const struct clk_parent_data mco1_src[] = {
{ .index = FLEXGEN_61 },
};
static const struct clk_parent_data mco2_src[] = {
{ .index = FLEXGEN_62 },
};
enum enum_mux_cfg {
MUX_ADC12,
MUX_ADC3,
MUX_DSIBLANE,
MUX_DSIPHY,
MUX_DTS,
MUX_LVDSPHY,
MUX_MCO1,
MUX_MCO2,
MUX_USB2PHY1,
MUX_USB2PHY2,
MUX_USB3PCIEPHY,
MUX_NB
};
#define MUX_CFG(id, _offset, _shift, _witdh) \
[id] = { \
.offset = (_offset), \
.shift = (_shift), \
.width = (_witdh), \
}
static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = {
MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1),
MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2),
MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1),
MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1),
MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2),
MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1),
MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1),
MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1),
MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1),
MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1),
MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1),
};
enum enum_gate_cfg {
GATE_ADC12,
GATE_ADC3,
GATE_ADF1,
GATE_CCI,
GATE_CRC,
GATE_CRYP1,
GATE_CRYP2,
GATE_CSI,
GATE_DCMIPP,
GATE_DSI,
GATE_DTS,
GATE_ETH1,
GATE_ETH1MAC,
GATE_ETH1RX,
GATE_ETH1STP,
GATE_ETH1TX,
GATE_ETH2,
GATE_ETH2MAC,
GATE_ETH2RX,
GATE_ETH2STP,
GATE_ETH2TX,
GATE_ETHSW,
GATE_ETHSWACMCFG,
GATE_ETHSWACMMSG,
GATE_ETHSWMAC,
GATE_ETHSWREF,
GATE_FDCAN,
GATE_GPU,
GATE_HASH,
GATE_HDP,
GATE_I2C1,
GATE_I2C2,
GATE_I2C3,
GATE_I2C4,
GATE_I2C5,
GATE_I2C6,
GATE_I2C7,
GATE_I2C8,
GATE_I3C1,
GATE_I3C2,
GATE_I3C3,
GATE_I3C4,
GATE_IS2M,
GATE_IWDG1,
GATE_IWDG2,
GATE_IWDG3,
GATE_IWDG4,
GATE_IWDG5,
GATE_LPTIM1,
GATE_LPTIM2,
GATE_LPTIM3,
GATE_LPTIM4,
GATE_LPTIM5,
GATE_LPUART1,
GATE_LTDC,
GATE_LVDS,
GATE_MCO1,
GATE_MCO2,
GATE_MDF1,
GATE_OSPIIOM,
GATE_PCIE,
GATE_PKA,
GATE_RNG,
GATE_SAES,
GATE_SAI1,
GATE_SAI2,
GATE_SAI3,
GATE_SAI4,
GATE_SDMMC1,
GATE_SDMMC2,
GATE_SDMMC3,
GATE_SERC,
GATE_SPDIFRX,
GATE_SPI1,
GATE_SPI2,
GATE_SPI3,
GATE_SPI4,
GATE_SPI5,
GATE_SPI6,
GATE_SPI7,
GATE_SPI8,
GATE_TIM1,
GATE_TIM10,
GATE_TIM11,
GATE_TIM12,
GATE_TIM13,
GATE_TIM14,
GATE_TIM15,
GATE_TIM16,
GATE_TIM17,
GATE_TIM2,
GATE_TIM20,
GATE_TIM3,
GATE_TIM4,
GATE_TIM5,
GATE_TIM6,
GATE_TIM7,
GATE_TIM8,
GATE_UART4,
GATE_UART5,
GATE_UART7,
GATE_UART8,
GATE_UART9,
GATE_USART1,
GATE_USART2,
GATE_USART3,
GATE_USART6,
GATE_USBH,
GATE_USB2PHY1,
GATE_USB2PHY2,
GATE_USB3DR,
GATE_USB3PCIEPHY,
GATE_USBTC,
GATE_VDEC,
GATE_VENC,
GATE_VREF,
GATE_WWDG1,
GATE_WWDG2,
GATE_NB
};
#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \
[id] = { \
.offset = (_offset), \
.bit_idx = (_bit_idx), \
.set_clr = (_offset_clr), \
}
static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = {
GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0),
GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0),
GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0),
GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0),
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0),
GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0),
GATE_CFG(GATE_ETHSWACMCFG, RCC_ETHSWACMCFGR, 1, 0),
GATE_CFG(GATE_ETHSWACMMSG, RCC_ETHSWACMMSGCFGR, 1, 0),
GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0),
GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0),
GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0),
GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0),
GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0),
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0),
GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0),
GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0),
GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0),
GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0),
GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0),
GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0),
GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0),
GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0),
};
#define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags) \
(&(struct clk_init_data) { \
.flags = _flags, \
.name = _name, \
.parent_data = (const struct clk_parent_data[]) { \
{ .index = _parent }, \
}, \
.num_parents = 1, \
.ops = _ops, \
})
/* ADC */
static struct clk_stm32_gate ck_icn_p_adc12 = {
.gate_id = GATE_ADC12,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc12", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_composite ck_ker_adc12 = {
.gate_id = GATE_ADC12,
.mux_id = MUX_ADC12,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc12", adc12_src, &clk_stm32_composite_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_adc3 = {
.gate_id = GATE_ADC3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_composite ck_ker_adc3 = {
.gate_id = GATE_ADC3,
.mux_id = MUX_ADC3,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc3", adc3_src, &clk_stm32_composite_ops, 0),
};
/* ADF */
static struct clk_stm32_gate ck_icn_p_adf1 = {
.gate_id = GATE_ADF1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_adf1 = {
.gate_id = GATE_ADF1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),
};
/* DCMI */
static struct clk_stm32_gate ck_icn_p_cci = {
.gate_id = GATE_CCI,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cci", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* CSI-HOST */
static struct clk_stm32_gate ck_icn_p_csi = {
.gate_id = GATE_CSI,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_csi = {
.gate_id = GATE_CSI,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_csitxesc = {
.gate_id = GATE_CSI,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),
};
/* CSI-PHY */
static struct clk_stm32_gate ck_ker_csiphy = {
.gate_id = GATE_CSI,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0),
};
/* DCMIPP */
static struct clk_stm32_gate ck_icn_p_dcmipp = {
.gate_id = GATE_DCMIPP,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0),
};
/* CRC */
static struct clk_stm32_gate ck_icn_p_crc = {
.gate_id = GATE_CRC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* CRYP */
static struct clk_stm32_gate ck_icn_p_cryp1 = {
.gate_id = GATE_CRYP1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_cryp2 = {
.gate_id = GATE_CRYP2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* DBG & TRACE*/
/* Trace and debug clocks are managed by SCMI */
/* LTDC */
static struct clk_stm32_gate ck_icn_p_ltdc = {
.gate_id = GATE_LTDC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_ltdc = {
.gate_id = GATE_LTDC,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
/* DSI */
static struct clk_stm32_gate ck_icn_p_dsi = {
.gate_id = GATE_DSI,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dsi", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_composite clk_lanebyte = {
.gate_id = GATE_DSI,
.mux_id = MUX_DSIBLANE,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_lanebyte", dsiblane_src,
&clk_stm32_composite_ops, 0),
};
/* LVDS */
static struct clk_stm32_gate ck_icn_p_lvds = {
.gate_id = GATE_LVDS,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lvds", ICN_APB4, &clk_stm32_gate_ops, 0),
};
/* DSI PHY */
static struct clk_stm32_composite clk_phy_dsi = {
.gate_id = GATE_DSI,
.mux_id = MUX_DSIPHY,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_phy_dsi", dsiphy_src,
&clk_stm32_composite_ops, 0),
};
/* LVDS PHY */
static struct clk_stm32_composite ck_ker_lvdsphy = {
.gate_id = GATE_LVDS,
.mux_id = MUX_LVDSPHY,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_lvdsphy", lvdsphy_src,
&clk_stm32_composite_ops, 0),
};
/* DTS */
static struct clk_stm32_composite ck_ker_dts = {
.gate_id = GATE_DTS,
.mux_id = MUX_DTS,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src,
&clk_stm32_composite_ops, 0),
};
/* ETHERNET */
static struct clk_stm32_gate ck_icn_p_eth1 = {
.gate_id = GATE_ETH1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1stp = {
.gate_id = GATE_ETH1STP,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1 = {
.gate_id = GATE_ETH1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1ptp = {
.gate_id = GATE_ETH1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1mac = {
.gate_id = GATE_ETH1MAC,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1tx = {
.gate_id = GATE_ETH1TX,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth1rx = {
.gate_id = GATE_ETH1RX,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_eth2 = {
.gate_id = GATE_ETH2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2stp = {
.gate_id = GATE_ETH2STP,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2 = {
.gate_id = GATE_ETH2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2ptp = {
.gate_id = GATE_ETH2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2mac = {
.gate_id = GATE_ETH2MAC,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2tx = {
.gate_id = GATE_ETH2TX,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_eth2rx = {
.gate_id = GATE_ETH2RX,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_ethsw = {
.gate_id = GATE_ETHSWMAC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_ethsw = {
.gate_id = GATE_ETHSW,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ethsw", FLEXGEN_54, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_ethswref = {
.gate_id = GATE_ETHSWREF,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ethswref", FLEXGEN_60, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_ethsw_acm_cfg = {
.gate_id = GATE_ETHSWACMCFG,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_cfg", ICN_LS_MCU,
&clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_ethsw_acm_msg = {
.gate_id = GATE_ETHSWACMMSG,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_msg", ICN_LS_MCU,
&clk_stm32_gate_ops, 0),
};
/* FDCAN */
static struct clk_stm32_gate ck_icn_p_fdcan = {
.gate_id = GATE_FDCAN,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_fdcan = {
.gate_id = GATE_FDCAN,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0),
};
/* GPU */
static struct clk_stm32_gate ck_icn_m_gpu = {
.gate_id = GATE_GPU,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_gpu", FLEXGEN_59, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_gpu = {
.gate_id = GATE_GPU,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),
};
/* HASH */
static struct clk_stm32_gate ck_icn_p_hash = {
.gate_id = GATE_HASH,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* HDP */
static struct clk_stm32_gate ck_icn_p_hdp = {
.gate_id = GATE_HDP,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0),
};
/* I2C */
static struct clk_stm32_gate ck_icn_p_i2c8 = {
.gate_id = GATE_I2C8,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c1 = {
.gate_id = GATE_I2C1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c2 = {
.gate_id = GATE_I2C2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c3 = {
.gate_id = GATE_I2C3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c4 = {
.gate_id = GATE_I2C4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c4", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c5 = {
.gate_id = GATE_I2C5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c5", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c6 = {
.gate_id = GATE_I2C6,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c6", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i2c7 = {
.gate_id = GATE_I2C7,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c7", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c1 = {
.gate_id = GATE_I2C1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c2 = {
.gate_id = GATE_I2C2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c3 = {
.gate_id = GATE_I2C3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c5 = {
.gate_id = GATE_I2C5,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c5", FLEXGEN_13, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c4 = {
.gate_id = GATE_I2C4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c4", FLEXGEN_14, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c6 = {
.gate_id = GATE_I2C6,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c6", FLEXGEN_14, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c7 = {
.gate_id = GATE_I2C7,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c7", FLEXGEN_15, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i2c8 = {
.gate_id = GATE_I2C8,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c8", FLEXGEN_38, &clk_stm32_gate_ops, 0),
};
/* I3C */
static struct clk_stm32_gate ck_icn_p_i3c1 = {
.gate_id = GATE_I3C1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i3c2 = {
.gate_id = GATE_I3C2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i3c3 = {
.gate_id = GATE_I3C3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_i3c4 = {
.gate_id = GATE_I3C4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i3c1 = {
.gate_id = GATE_I3C1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i3c2 = {
.gate_id = GATE_I3C2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i3c3 = {
.gate_id = GATE_I3C3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_i3c4 = {
.gate_id = GATE_I3C4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c4", FLEXGEN_36, &clk_stm32_gate_ops, 0),
};
/* I2S */
static struct clk_stm32_gate ck_icn_p_is2m = {
.gate_id = GATE_IS2M,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_is2m", ICN_APB3, &clk_stm32_gate_ops, 0),
};
/* IWDG */
static struct clk_stm32_gate ck_icn_p_iwdg2 = {
.gate_id = GATE_IWDG2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_iwdg3 = {
.gate_id = GATE_IWDG3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_iwdg4 = {
.gate_id = GATE_IWDG4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_iwdg5 = {
.gate_id = GATE_IWDG5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* LPTIM */
static struct clk_stm32_gate ck_icn_p_lptim1 = {
.gate_id = GATE_LPTIM1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_lptim2 = {
.gate_id = GATE_LPTIM2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_lptim3 = {
.gate_id = GATE_LPTIM3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_lptim4 = {
.gate_id = GATE_LPTIM4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_lptim5 = {
.gate_id = GATE_LPTIM5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lptim1 = {
.gate_id = GATE_LPTIM1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lptim2 = {
.gate_id = GATE_LPTIM2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lptim3 = {
.gate_id = GATE_LPTIM3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lptim4 = {
.gate_id = GATE_LPTIM4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lptim5 = {
.gate_id = GATE_LPTIM5,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_41, &clk_stm32_gate_ops, 0),
};
/* LPUART */
static struct clk_stm32_gate ck_icn_p_lpuart1 = {
.gate_id = GATE_LPUART1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_lpuart1 = {
.gate_id = GATE_LPUART1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0),
};
/* MCO1 & MCO2 */
static struct clk_stm32_composite ck_mco1 = {
.gate_id = GATE_MCO1,
.mux_id = MUX_MCO1,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0),
};
static struct clk_stm32_composite ck_mco2 = {
.gate_id = GATE_MCO2,
.mux_id = MUX_MCO2,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0),
};
/* MDF */
static struct clk_stm32_gate ck_icn_p_mdf1 = {
.gate_id = GATE_MDF1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_mdf1 = {
.gate_id = GATE_MDF1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_23, &clk_stm32_gate_ops, 0),
};
/* OSPI */
static struct clk_stm32_gate ck_icn_p_ospiiom = {
.gate_id = GATE_OSPIIOM,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ospiiom", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* PCIE */
static struct clk_stm32_gate ck_icn_p_pcie = {
.gate_id = GATE_PCIE,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pcie", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
/* SAI */
static struct clk_stm32_gate ck_icn_p_sai1 = {
.gate_id = GATE_SAI1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_sai2 = {
.gate_id = GATE_SAI2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_sai3 = {
.gate_id = GATE_SAI3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_sai4 = {
.gate_id = GATE_SAI4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_sai1 = {
.gate_id = GATE_SAI1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_23, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_sai2 = {
.gate_id = GATE_SAI2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_24, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_sai3 = {
.gate_id = GATE_SAI3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_25, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_sai4 = {
.gate_id = GATE_SAI4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
/* SDMMC */
static struct clk_stm32_gate ck_icn_m_sdmmc1 = {
.gate_id = GATE_SDMMC1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_m_sdmmc2 = {
.gate_id = GATE_SDMMC2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_m_sdmmc3 = {
.gate_id = GATE_SDMMC3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_sdmmc1 = {
.gate_id = GATE_SDMMC1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_sdmmc2 = {
.gate_id = GATE_SDMMC2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_sdmmc3 = {
.gate_id = GATE_SDMMC3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),
};
/* SPDIF */
static struct clk_stm32_gate ck_icn_p_spdifrx = {
.gate_id = GATE_SPDIFRX,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spdifrx = {
.gate_id = GATE_SPDIFRX,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_11, &clk_stm32_gate_ops, 0),
};
/* SPI */
static struct clk_stm32_gate ck_icn_p_spi1 = {
.gate_id = GATE_SPI1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi2 = {
.gate_id = GATE_SPI2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi3 = {
.gate_id = GATE_SPI3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi4 = {
.gate_id = GATE_SPI4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi5 = {
.gate_id = GATE_SPI5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi6 = {
.gate_id = GATE_SPI6,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi7 = {
.gate_id = GATE_SPI7,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi7", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_spi8 = {
.gate_id = GATE_SPI8,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spi1 = {
.gate_id = GATE_SPI1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_spi2 = {
.gate_id = GATE_SPI2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_spi3 = {
.gate_id = GATE_SPI3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_10, &clk_stm32_gate_ops,
CLK_SET_RATE_PARENT),
};
static struct clk_stm32_gate ck_ker_spi4 = {
.gate_id = GATE_SPI4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spi5 = {
.gate_id = GATE_SPI5,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spi6 = {
.gate_id = GATE_SPI6,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_18, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spi7 = {
.gate_id = GATE_SPI7,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi7", FLEXGEN_18, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_spi8 = {
.gate_id = GATE_SPI8,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi8", FLEXGEN_37, &clk_stm32_gate_ops, 0),
};
/* Timers */
static struct clk_stm32_gate ck_icn_p_tim2 = {
.gate_id = GATE_TIM2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim3 = {
.gate_id = GATE_TIM3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim4 = {
.gate_id = GATE_TIM4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim5 = {
.gate_id = GATE_TIM5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim6 = {
.gate_id = GATE_TIM6,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim7 = {
.gate_id = GATE_TIM7,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim10 = {
.gate_id = GATE_TIM10,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim11 = {
.gate_id = GATE_TIM11,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim12 = {
.gate_id = GATE_TIM12,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim13 = {
.gate_id = GATE_TIM13,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim14 = {
.gate_id = GATE_TIM14,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim1 = {
.gate_id = GATE_TIM1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim8 = {
.gate_id = GATE_TIM8,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim15 = {
.gate_id = GATE_TIM15,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim16 = {
.gate_id = GATE_TIM16,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim17 = {
.gate_id = GATE_TIM17,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_tim20 = {
.gate_id = GATE_TIM20,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim20", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim2 = {
.gate_id = GATE_TIM2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim3 = {
.gate_id = GATE_TIM3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim4 = {
.gate_id = GATE_TIM4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim5 = {
.gate_id = GATE_TIM5,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim6 = {
.gate_id = GATE_TIM6,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim7 = {
.gate_id = GATE_TIM7,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim10 = {
.gate_id = GATE_TIM10,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim11 = {
.gate_id = GATE_TIM11,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim12 = {
.gate_id = GATE_TIM12,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim13 = {
.gate_id = GATE_TIM13,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim14 = {
.gate_id = GATE_TIM14,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim1 = {
.gate_id = GATE_TIM1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim8 = {
.gate_id = GATE_TIM8,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim15 = {
.gate_id = GATE_TIM15,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim16 = {
.gate_id = GATE_TIM16,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim17 = {
.gate_id = GATE_TIM17,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_tim20 = {
.gate_id = GATE_TIM20,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim20", TIMG2, &clk_stm32_gate_ops, 0),
};
/* UART/USART */
static struct clk_stm32_gate ck_icn_p_usart2 = {
.gate_id = GATE_USART2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_usart3 = {
.gate_id = GATE_USART3,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_uart4 = {
.gate_id = GATE_UART4,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_uart5 = {
.gate_id = GATE_UART5,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_usart1 = {
.gate_id = GATE_USART1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_usart6 = {
.gate_id = GATE_USART6,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_uart7 = {
.gate_id = GATE_UART7,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_uart8 = {
.gate_id = GATE_UART8,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart8", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_uart9 = {
.gate_id = GATE_UART9,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart9", ICN_APB2, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usart2 = {
.gate_id = GATE_USART2,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_uart4 = {
.gate_id = GATE_UART4,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usart3 = {
.gate_id = GATE_USART3,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_uart5 = {
.gate_id = GATE_UART5,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usart1 = {
.gate_id = GATE_USART1,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_19, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usart6 = {
.gate_id = GATE_USART6,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_20, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_uart7 = {
.gate_id = GATE_UART7,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_21, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_uart8 = {
.gate_id = GATE_UART8,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart8", FLEXGEN_21, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_uart9 = {
.gate_id = GATE_UART9,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart9", FLEXGEN_22, &clk_stm32_gate_ops, 0),
};
/* USB2PHY1 */
static struct clk_stm32_composite ck_ker_usb2phy1 = {
.gate_id = GATE_USB2PHY1,
.mux_id = MUX_USB2PHY1,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src,
&clk_stm32_composite_ops, 0),
};
/* USB2H */
static struct clk_stm32_gate ck_icn_m_usb2ehci = {
.gate_id = GATE_USBH,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ehci", ICN_HSL, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_m_usb2ohci = {
.gate_id = GATE_USBH,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ohci", ICN_HSL, &clk_stm32_gate_ops, 0),
};
/* USB2PHY2 */
static struct clk_stm32_composite ck_ker_usb2phy2_en = {
.gate_id = GATE_USB2PHY2,
.mux_id = MUX_USB2PHY2,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src,
&clk_stm32_composite_ops, 0),
};
/* USB3 PCIe COMBOPHY */
static struct clk_stm32_gate ck_icn_p_usb3pciephy = {
.gate_id = GATE_USB3PCIEPHY,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usb3pciephy", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_composite ck_ker_usb3pciephy = {
.gate_id = GATE_USB3PCIEPHY,
.mux_id = MUX_USB3PCIEPHY,
.div_id = NO_STM32_DIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb3pciephy", usb3pciphy_src,
&clk_stm32_composite_ops, 0),
};
/* USB3 DRD */
static struct clk_stm32_gate ck_icn_m_usb3dr = {
.gate_id = GATE_USB3DR,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb3dr", ICN_HSL, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usb2phy2 = {
.gate_id = GATE_USB3DR,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usb2phy2", FLEXGEN_58, &clk_stm32_gate_ops, 0),
};
/* USBTC */
static struct clk_stm32_gate ck_icn_p_usbtc = {
.gate_id = GATE_USBTC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usbtc", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_ker_usbtc = {
.gate_id = GATE_USBTC,
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usbtc", FLEXGEN_35, &clk_stm32_gate_ops, 0),
};
/* VDEC / VENC */
static struct clk_stm32_gate ck_icn_p_vdec = {
.gate_id = GATE_VDEC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vdec", ICN_APB4, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_venc = {
.gate_id = GATE_VENC,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_venc", ICN_APB4, &clk_stm32_gate_ops, 0),
};
/* VREF */
static struct clk_stm32_gate ck_icn_p_vref = {
.gate_id = GATE_VREF,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0),
};
/* WWDG */
static struct clk_stm32_gate ck_icn_p_wwdg1 = {
.gate_id = GATE_WWDG1,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
};
static struct clk_stm32_gate ck_icn_p_wwdg2 = {
.gate_id = GATE_WWDG2,
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
};
#define SECF_NONE -1
static const struct clock_config stm32mp25_clock_cfg[] = {
STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_PCIE, ck_icn_p_pcie, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ETHSW, ck_icn_p_ethsw, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ADC12, ck_icn_p_adc12, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ADC3, ck_icn_p_adc3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_CCI, ck_icn_p_cci, SECF_NONE),
STM32_GATE_CFG(CK_BUS_CRC, ck_icn_p_crc, SECF_NONE),
STM32_GATE_CFG(CK_BUS_MDF1, ck_icn_p_mdf1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_OSPIIOM, ck_icn_p_ospiiom, SECF_NONE),
STM32_GATE_CFG(CK_BUS_HASH, ck_icn_p_hash, SECF_NONE),
STM32_GATE_CFG(CK_BUS_CRYP1, ck_icn_p_cryp1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_CRYP2, ck_icn_p_cryp2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ADF1, ck_icn_p_adf1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI8, ck_icn_p_spi8, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPUART1, ck_icn_p_lpuart1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C8, ck_icn_p_i2c8, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPTIM3, ck_icn_p_lptim3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPTIM4, ck_icn_p_lptim4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPTIM5, ck_icn_p_lptim5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_IWDG5, ck_icn_p_iwdg5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_WWDG2, ck_icn_p_wwdg2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I3C4, ck_icn_p_i3c4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SDMMC1, ck_icn_m_sdmmc1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SDMMC2, ck_icn_m_sdmmc2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SDMMC3, ck_icn_m_sdmmc3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USB2OHCI, ck_icn_m_usb2ohci, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USB2EHCI, ck_icn_m_usb2ehci, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USB3DR, ck_icn_m_usb3dr, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM2, ck_icn_p_tim2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM3, ck_icn_p_tim3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM4, ck_icn_p_tim4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM5, ck_icn_p_tim5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM6, ck_icn_p_tim6, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM7, ck_icn_p_tim7, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM10, ck_icn_p_tim10, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM11, ck_icn_p_tim11, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM12, ck_icn_p_tim12, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM13, ck_icn_p_tim13, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM14, ck_icn_p_tim14, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPTIM1, ck_icn_p_lptim1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LPTIM2, ck_icn_p_lptim2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI2, ck_icn_p_spi2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI3, ck_icn_p_spi3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPDIFRX, ck_icn_p_spdifrx, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USART2, ck_icn_p_usart2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USART3, ck_icn_p_usart3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_UART4, ck_icn_p_uart4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_UART5, ck_icn_p_uart5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C1, ck_icn_p_i2c1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C2, ck_icn_p_i2c2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C3, ck_icn_p_i2c3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C4, ck_icn_p_i2c4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C5, ck_icn_p_i2c5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C6, ck_icn_p_i2c6, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I2C7, ck_icn_p_i2c7, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I3C1, ck_icn_p_i3c1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I3C2, ck_icn_p_i3c2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_I3C3, ck_icn_p_i3c3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM1, ck_icn_p_tim1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM8, ck_icn_p_tim8, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM15, ck_icn_p_tim15, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM16, ck_icn_p_tim16, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM17, ck_icn_p_tim17, SECF_NONE),
STM32_GATE_CFG(CK_BUS_TIM20, ck_icn_p_tim20, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SAI1, ck_icn_p_sai1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SAI2, ck_icn_p_sai2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SAI3, ck_icn_p_sai3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SAI4, ck_icn_p_sai4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USART1, ck_icn_p_usart1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USART6, ck_icn_p_usart6, SECF_NONE),
STM32_GATE_CFG(CK_BUS_UART7, ck_icn_p_uart7, SECF_NONE),
STM32_GATE_CFG(CK_BUS_UART8, ck_icn_p_uart8, SECF_NONE),
STM32_GATE_CFG(CK_BUS_UART9, ck_icn_p_uart9, SECF_NONE),
STM32_GATE_CFG(CK_BUS_FDCAN, ck_icn_p_fdcan, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI1, ck_icn_p_spi1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI4, ck_icn_p_spi4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI5, ck_icn_p_spi5, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI6, ck_icn_p_spi6, SECF_NONE),
STM32_GATE_CFG(CK_BUS_SPI7, ck_icn_p_spi7, SECF_NONE),
STM32_GATE_CFG(CK_BUS_IWDG2, ck_icn_p_iwdg2, SECF_NONE),
STM32_GATE_CFG(CK_BUS_IWDG3, ck_icn_p_iwdg3, SECF_NONE),
STM32_GATE_CFG(CK_BUS_IWDG4, ck_icn_p_iwdg4, SECF_NONE),
STM32_GATE_CFG(CK_BUS_WWDG1, ck_icn_p_wwdg1, SECF_NONE),
STM32_GATE_CFG(CK_BUS_VREF, ck_icn_p_vref, SECF_NONE),
STM32_GATE_CFG(CK_BUS_HDP, ck_icn_p_hdp, SECF_NONE),
STM32_GATE_CFG(CK_BUS_IS2M, ck_icn_p_is2m, SECF_NONE),
STM32_GATE_CFG(CK_BUS_DSI, ck_icn_p_dsi, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LTDC, ck_icn_p_ltdc, SECF_NONE),
STM32_GATE_CFG(CK_BUS_CSI, ck_icn_p_csi, SECF_NONE),
STM32_GATE_CFG(CK_BUS_DCMIPP, ck_icn_p_dcmipp, SECF_NONE),
STM32_GATE_CFG(CK_BUS_LVDS, ck_icn_p_lvds, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USBTC, ck_icn_p_usbtc, SECF_NONE),
STM32_GATE_CFG(CK_BUS_USB3PCIEPHY, ck_icn_p_usb3pciephy, SECF_NONE),
STM32_GATE_CFG(CK_BUS_VDEC, ck_icn_p_vdec, SECF_NONE),
STM32_GATE_CFG(CK_BUS_VENC, ck_icn_p_venc, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM2, ck_ker_tim2, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM3, ck_ker_tim3, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM4, ck_ker_tim4, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM5, ck_ker_tim5, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM6, ck_ker_tim6, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM7, ck_ker_tim7, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM10, ck_ker_tim10, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM11, ck_ker_tim11, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM12, ck_ker_tim12, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM13, ck_ker_tim13, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM14, ck_ker_tim14, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM1, ck_ker_tim1, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM8, ck_ker_tim8, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM15, ck_ker_tim15, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM16, ck_ker_tim16, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM17, ck_ker_tim17, SECF_NONE),
STM32_GATE_CFG(CK_KER_TIM20, ck_ker_tim20, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPTIM1, ck_ker_lptim1, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPTIM2, ck_ker_lptim2, SECF_NONE),
STM32_GATE_CFG(CK_KER_USART2, ck_ker_usart2, SECF_NONE),
STM32_GATE_CFG(CK_KER_UART4, ck_ker_uart4, SECF_NONE),
STM32_GATE_CFG(CK_KER_USART3, ck_ker_usart3, SECF_NONE),
STM32_GATE_CFG(CK_KER_UART5, ck_ker_uart5, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI2, ck_ker_spi2, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI3, ck_ker_spi3, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPDIFRX, ck_ker_spdifrx, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C1, ck_ker_i2c1, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C2, ck_ker_i2c2, SECF_NONE),
STM32_GATE_CFG(CK_KER_I3C1, ck_ker_i3c1, SECF_NONE),
STM32_GATE_CFG(CK_KER_I3C2, ck_ker_i3c2, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C3, ck_ker_i2c3, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C5, ck_ker_i2c5, SECF_NONE),
STM32_GATE_CFG(CK_KER_I3C3, ck_ker_i3c3, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C4, ck_ker_i2c4, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C6, ck_ker_i2c6, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C7, ck_ker_i2c7, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI1, ck_ker_spi1, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI4, ck_ker_spi4, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI5, ck_ker_spi5, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI6, ck_ker_spi6, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI7, ck_ker_spi7, SECF_NONE),
STM32_GATE_CFG(CK_KER_USART1, ck_ker_usart1, SECF_NONE),
STM32_GATE_CFG(CK_KER_USART6, ck_ker_usart6, SECF_NONE),
STM32_GATE_CFG(CK_KER_UART7, ck_ker_uart7, SECF_NONE),
STM32_GATE_CFG(CK_KER_UART8, ck_ker_uart8, SECF_NONE),
STM32_GATE_CFG(CK_KER_UART9, ck_ker_uart9, SECF_NONE),
STM32_GATE_CFG(CK_KER_MDF1, ck_ker_mdf1, SECF_NONE),
STM32_GATE_CFG(CK_KER_SAI1, ck_ker_sai1, SECF_NONE),
STM32_GATE_CFG(CK_KER_SAI2, ck_ker_sai2, SECF_NONE),
STM32_GATE_CFG(CK_KER_SAI3, ck_ker_sai3, SECF_NONE),
STM32_GATE_CFG(CK_KER_SAI4, ck_ker_sai4, SECF_NONE),
STM32_GATE_CFG(CK_KER_FDCAN, ck_ker_fdcan, SECF_NONE),
STM32_GATE_CFG(CK_KER_CSI, ck_ker_csi, SECF_NONE),
STM32_GATE_CFG(CK_KER_CSITXESC, ck_ker_csitxesc, SECF_NONE),
STM32_GATE_CFG(CK_KER_CSIPHY, ck_ker_csiphy, SECF_NONE),
STM32_GATE_CFG(CK_KER_USBTC, ck_ker_usbtc, SECF_NONE),
STM32_GATE_CFG(CK_KER_I3C4, ck_ker_i3c4, SECF_NONE),
STM32_GATE_CFG(CK_KER_SPI8, ck_ker_spi8, SECF_NONE),
STM32_GATE_CFG(CK_KER_I2C8, ck_ker_i2c8, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPUART1, ck_ker_lpuart1, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPTIM3, ck_ker_lptim3, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPTIM4, ck_ker_lptim4, SECF_NONE),
STM32_GATE_CFG(CK_KER_LPTIM5, ck_ker_lptim5, SECF_NONE),
STM32_GATE_CFG(CK_KER_ADF1, ck_ker_adf1, SECF_NONE),
STM32_GATE_CFG(CK_KER_SDMMC1, ck_ker_sdmmc1, SECF_NONE),
STM32_GATE_CFG(CK_KER_SDMMC2, ck_ker_sdmmc2, SECF_NONE),
STM32_GATE_CFG(CK_KER_SDMMC3, ck_ker_sdmmc3, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETH1, ck_ker_eth1, SECF_NONE),
STM32_GATE_CFG(CK_ETH1_STP, ck_ker_eth1stp, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETHSW, ck_ker_ethsw, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETH2, ck_ker_eth2, SECF_NONE),
STM32_GATE_CFG(CK_ETH2_STP, ck_ker_eth2stp, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETH1PTP, ck_ker_eth1ptp, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETH2PTP, ck_ker_eth2ptp, SECF_NONE),
STM32_GATE_CFG(CK_BUS_GPU, ck_icn_m_gpu, SECF_NONE),
STM32_GATE_CFG(CK_KER_GPU, ck_ker_gpu, SECF_NONE),
STM32_GATE_CFG(CK_KER_ETHSWREF, ck_ker_ethswref, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ETHSWACMCFG, ck_icn_p_ethsw_acm_cfg, SECF_NONE),
STM32_GATE_CFG(CK_BUS_ETHSWACMMSG, ck_icn_p_ethsw_acm_msg, SECF_NONE),
STM32_GATE_CFG(CK_ETH1_MAC, ck_ker_eth1mac, SECF_NONE),
STM32_GATE_CFG(CK_ETH1_TX, ck_ker_eth1tx, SECF_NONE),
STM32_GATE_CFG(CK_ETH1_RX, ck_ker_eth1rx, SECF_NONE),
STM32_GATE_CFG(CK_ETH2_MAC, ck_ker_eth2mac, SECF_NONE),
STM32_GATE_CFG(CK_ETH2_TX, ck_ker_eth2tx, SECF_NONE),
STM32_GATE_CFG(CK_ETH2_RX, ck_ker_eth2rx, SECF_NONE),
STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_NONE),
STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_ADC12, ck_ker_adc12, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_ADC3, ck_ker_adc3, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SECF_NONE),
STM32_GATE_CFG(CK_KER_USB2PHY2, ck_ker_usb2phy2, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_USB3PCIEPHY, ck_ker_usb3pciephy, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_DSIBLANE, clk_lanebyte, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_DSIPHY, clk_phy_dsi, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_LVDSPHY, ck_ker_lvdsphy, SECF_NONE),
STM32_COMPOSITE_CFG(CK_KER_DTS, ck_ker_dts, SECF_NONE),
STM32_GATE_CFG(CK_KER_LTDC, ck_ker_ltdc, SECF_NONE),
};
#define RESET_MP25(id, _offset, _bit_idx, _set_clr) \
[id] = &(struct stm32_reset_cfg){ \
.offset = (_offset), \
.bit_idx = (_bit_idx), \
.set_clr = (_set_clr), \
}
static const struct stm32_reset_cfg *stm32mp25_reset_cfg[STM32MP25_LAST_RESET] = {
RESET_MP25(TIM1_R, RCC_TIM1CFGR, 0, 0),
RESET_MP25(TIM2_R, RCC_TIM2CFGR, 0, 0),
RESET_MP25(TIM3_R, RCC_TIM3CFGR, 0, 0),
RESET_MP25(TIM4_R, RCC_TIM4CFGR, 0, 0),
RESET_MP25(TIM5_R, RCC_TIM5CFGR, 0, 0),
RESET_MP25(TIM6_R, RCC_TIM6CFGR, 0, 0),
RESET_MP25(TIM7_R, RCC_TIM7CFGR, 0, 0),
RESET_MP25(TIM8_R, RCC_TIM8CFGR, 0, 0),
RESET_MP25(TIM10_R, RCC_TIM10CFGR, 0, 0),
RESET_MP25(TIM11_R, RCC_TIM11CFGR, 0, 0),
RESET_MP25(TIM12_R, RCC_TIM12CFGR, 0, 0),
RESET_MP25(TIM13_R, RCC_TIM13CFGR, 0, 0),
RESET_MP25(TIM14_R, RCC_TIM14CFGR, 0, 0),
RESET_MP25(TIM15_R, RCC_TIM15CFGR, 0, 0),
RESET_MP25(TIM16_R, RCC_TIM16CFGR, 0, 0),
RESET_MP25(TIM17_R, RCC_TIM17CFGR, 0, 0),
RESET_MP25(TIM20_R, RCC_TIM20CFGR, 0, 0),
RESET_MP25(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),
RESET_MP25(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),
RESET_MP25(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),
RESET_MP25(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),
RESET_MP25(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),
RESET_MP25(SPI1_R, RCC_SPI1CFGR, 0, 0),
RESET_MP25(SPI2_R, RCC_SPI2CFGR, 0, 0),
RESET_MP25(SPI3_R, RCC_SPI3CFGR, 0, 0),
RESET_MP25(SPI4_R, RCC_SPI4CFGR, 0, 0),
RESET_MP25(SPI5_R, RCC_SPI5CFGR, 0, 0),
RESET_MP25(SPI6_R, RCC_SPI6CFGR, 0, 0),
RESET_MP25(SPI7_R, RCC_SPI7CFGR, 0, 0),
RESET_MP25(SPI8_R, RCC_SPI8CFGR, 0, 0),
RESET_MP25(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),
RESET_MP25(USART1_R, RCC_USART1CFGR, 0, 0),
RESET_MP25(USART2_R, RCC_USART2CFGR, 0, 0),
RESET_MP25(USART3_R, RCC_USART3CFGR, 0, 0),
RESET_MP25(UART4_R, RCC_UART4CFGR, 0, 0),
RESET_MP25(UART5_R, RCC_UART5CFGR, 0, 0),
RESET_MP25(USART6_R, RCC_USART6CFGR, 0, 0),
RESET_MP25(UART7_R, RCC_UART7CFGR, 0, 0),
RESET_MP25(UART8_R, RCC_UART8CFGR, 0, 0),
RESET_MP25(UART9_R, RCC_UART9CFGR, 0, 0),
RESET_MP25(LPUART1_R, RCC_LPUART1CFGR, 0, 0),
RESET_MP25(IS2M_R, RCC_IS2MCFGR, 0, 0),
RESET_MP25(I2C1_R, RCC_I2C1CFGR, 0, 0),
RESET_MP25(I2C2_R, RCC_I2C2CFGR, 0, 0),
RESET_MP25(I2C3_R, RCC_I2C3CFGR, 0, 0),
RESET_MP25(I2C4_R, RCC_I2C4CFGR, 0, 0),
RESET_MP25(I2C5_R, RCC_I2C5CFGR, 0, 0),
RESET_MP25(I2C6_R, RCC_I2C6CFGR, 0, 0),
RESET_MP25(I2C7_R, RCC_I2C7CFGR, 0, 0),
RESET_MP25(I2C8_R, RCC_I2C8CFGR, 0, 0),
RESET_MP25(SAI1_R, RCC_SAI1CFGR, 0, 0),
RESET_MP25(SAI2_R, RCC_SAI2CFGR, 0, 0),
RESET_MP25(SAI3_R, RCC_SAI3CFGR, 0, 0),
RESET_MP25(SAI4_R, RCC_SAI4CFGR, 0, 0),
RESET_MP25(MDF1_R, RCC_MDF1CFGR, 0, 0),
RESET_MP25(MDF2_R, RCC_ADF1CFGR, 0, 0),
RESET_MP25(FDCAN_R, RCC_FDCANCFGR, 0, 0),
RESET_MP25(HDP_R, RCC_HDPCFGR, 0, 0),
RESET_MP25(ADC12_R, RCC_ADC12CFGR, 0, 0),
RESET_MP25(ADC3_R, RCC_ADC3CFGR, 0, 0),
RESET_MP25(ETH1_R, RCC_ETH1CFGR, 0, 0),
RESET_MP25(ETH2_R, RCC_ETH2CFGR, 0, 0),
RESET_MP25(USBH_R, RCC_USBHCFGR, 0, 0),
RESET_MP25(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),
RESET_MP25(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),
RESET_MP25(USB3DR_R, RCC_USB3DRCFGR, 0, 0),
RESET_MP25(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0, 0),
RESET_MP25(USBTC_R, RCC_USBTCCFGR, 0, 0),
RESET_MP25(ETHSW_R, RCC_ETHSWCFGR, 0, 0),
RESET_MP25(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),
RESET_MP25(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),
RESET_MP25(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),
RESET_MP25(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),
RESET_MP25(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),
RESET_MP25(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),
RESET_MP25(GPU_R, RCC_GPUCFGR, 0, 0),
RESET_MP25(LTDC_R, RCC_LTDCCFGR, 0, 0),
RESET_MP25(DSI_R, RCC_DSICFGR, 0, 0),
RESET_MP25(LVDS_R, RCC_LVDSCFGR, 0, 0),
RESET_MP25(CSI_R, RCC_CSICFGR, 0, 0),
RESET_MP25(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),
RESET_MP25(CCI_R, RCC_CCICFGR, 0, 0),
RESET_MP25(VDEC_R, RCC_VDECCFGR, 0, 0),
RESET_MP25(VENC_R, RCC_VENCCFGR, 0, 0),
RESET_MP25(WWDG1_R, RCC_WWDG1CFGR, 0, 0),
RESET_MP25(WWDG2_R, RCC_WWDG2CFGR, 0, 0),
RESET_MP25(VREF_R, RCC_VREFCFGR, 0, 0),
RESET_MP25(DTS_R, RCC_DTSCFGR, 0, 0),
RESET_MP25(CRC_R, RCC_CRCCFGR, 0, 0),
RESET_MP25(SERC_R, RCC_SERCCFGR, 0, 0),
RESET_MP25(OSPIIOM_R, RCC_OSPIIOMCFGR, 0, 0),
RESET_MP25(I3C1_R, RCC_I3C1CFGR, 0, 0),
RESET_MP25(I3C2_R, RCC_I3C2CFGR, 0, 0),
RESET_MP25(I3C3_R, RCC_I3C3CFGR, 0, 0),
RESET_MP25(I3C4_R, RCC_I3C4CFGR, 0, 0),
RESET_MP25(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),
RESET_MP25(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),
RESET_MP25(RNG_R, RCC_RNGCFGR, 0, 0),
RESET_MP25(PKA_R, RCC_PKACFGR, 0, 0),
RESET_MP25(SAES_R, RCC_SAESCFGR, 0, 0),
RESET_MP25(HASH_R, RCC_HASHCFGR, 0, 0),
RESET_MP25(CRYP1_R, RCC_CRYP1CFGR, 0, 0),
RESET_MP25(CRYP2_R, RCC_CRYP2CFGR, 0, 0),
RESET_MP25(PCIE_R, RCC_PCIECFGR, 0, 0),
};
static u16 stm32mp25_cpt_gate[GATE_NB];
static struct clk_stm32_clock_data stm32mp25_clock_data = {
.gate_cpt = stm32mp25_cpt_gate,
.gates = stm32mp25_gates,
.muxes = stm32mp25_muxes,
};
static struct clk_stm32_reset_data stm32mp25_reset_data = {
.reset_lines = stm32mp25_reset_cfg,
.nr_lines = ARRAY_SIZE(stm32mp25_reset_cfg),
};
static const struct stm32_rcc_match_data stm32mp25_data = {
.tab_clocks = stm32mp25_clock_cfg,
.num_clocks = ARRAY_SIZE(stm32mp25_clock_cfg),
.maxbinding = STM32MP25_LAST_CLK,
.clock_data = &stm32mp25_clock_data,
.reset_data = &stm32mp25_reset_data,
};
static const struct of_device_id stm32mp25_match_data[] = {
{ .compatible = "st,stm32mp25-rcc", .data = &stm32mp25_data, },
{ }
};
MODULE_DEVICE_TABLE(of, stm32mp25_match_data);
static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
return stm32_rcc_init(dev, stm32mp25_match_data, base);
}
static struct platform_driver stm32mp25_rcc_clocks_driver = {
.driver = {
.name = "stm32mp25_rcc",
.of_match_table = stm32mp25_match_data,
},
.probe = stm32mp25_rcc_clocks_probe,
};
static int __init stm32mp25_clocks_init(void)
{
return platform_driver_register(&stm32mp25_rcc_clocks_driver);
}
core_initcall(stm32mp25_clocks_init);
drivers/clk/stm32/reset-stm32.c
View file @ 7552d1b9
......@@ -19,6 +19,7 @@ struct stm32_reset_data {
struct reset_controller_dev rcdev;
void __iomem *membase;
u32 clear_offset;
const struct stm32_reset_cfg **reset_lines;
};
static inline struct stm32_reset_data *
......@@ -27,22 +28,46 @@ to_stm32_reset_data(struct reset_controller_dev *rcdev)
return container_of(rcdev, struct stm32_reset_data, rcdev);
}
static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_controller_dev *rcdev,
unsigned long id,
struct stm32_reset_cfg *line)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
if (!data->reset_lines) {
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
line->offset = bank * reg_width;
line->bit_idx = offset;
line->set_clr = (data->clear_offset ? true : false);
return line;
}
return data->reset_lines[id];
}
static int stm32_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
struct stm32_reset_cfg line_reset;
const struct stm32_reset_cfg *ptr_line;
if (data->clear_offset) {
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
if (!ptr_line)
return -EPERM;
if (ptr_line->set_clr) {
void __iomem *addr;
addr = data->membase + (bank * reg_width);
addr = data->membase + ptr_line->offset;
if (!assert)
addr += data->clear_offset;
writel(BIT(offset), addr);
writel(BIT(ptr_line->bit_idx), addr);
} else {
unsigned long flags;
......@@ -50,14 +75,14 @@ static int stm32_reset_update(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
reg = readl(data->membase + (bank * reg_width));
reg = readl(data->membase + ptr_line->offset);
if (assert)
reg |= BIT(offset);
reg |= BIT(ptr_line->bit_idx);
else
reg &= ~BIT(offset);
reg &= ~BIT(ptr_line->bit_idx);
writel(reg, data->membase + (bank * reg_width));
writel(reg, data->membase + ptr_line->offset);
spin_unlock_irqrestore(&data->lock, flags);
}
......@@ -81,14 +106,17 @@ static int stm32_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
struct stm32_reset_cfg line_reset;
const struct stm32_reset_cfg *ptr_line;
u32 reg;
reg = readl(data->membase + (bank * reg_width));
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
if (!ptr_line)
return -EPERM;
reg = readl(data->membase + ptr_line->offset);
return !!(reg & BIT(offset));
return !!(reg & BIT(ptr_line->bit_idx));
}
static const struct reset_control_ops stm32_reset_ops = {
......@@ -113,6 +141,7 @@ int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,
reset_data->rcdev.ops = &stm32_reset_ops;
reset_data->rcdev.of_node = dev_of_node(dev);
reset_data->rcdev.nr_resets = data->nr_lines;
reset_data->reset_lines = data->reset_lines;
reset_data->clear_offset = data->clear_offset;
return reset_controller_register(&reset_data->rcdev);
......
drivers/clk/stm32/reset-stm32.h
View file @ 7552d1b9
......@@ -4,8 +4,15 @@
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
struct stm32_reset_cfg {
u16 offset;
u8 bit_idx;
bool set_clr;
};
struct clk_stm32_reset_data {
const struct reset_control_ops *ops;
const struct stm32_reset_cfg **reset_lines;
unsigned int nr_lines;
u32 clear_offset;
};
......
drivers/clk/stm32/stm32mp25_rcc.h 0 → 100644
View file @ 7552d1b9
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#ifndef STM32MP25_RCC_H
#define STM32MP25_RCC_H
#define RCC_SECCFGR0 0x0
#define RCC_SECCFGR1 0x4
#define RCC_SECCFGR2 0x8
#define RCC_SECCFGR3 0xC
#define RCC_PRIVCFGR0 0x10
#define RCC_PRIVCFGR1 0x14
#define RCC_PRIVCFGR2 0x18
#define RCC_PRIVCFGR3 0x1C
#define RCC_RCFGLOCKR0 0x20
#define RCC_RCFGLOCKR1 0x24
#define RCC_RCFGLOCKR2 0x28
#define RCC_RCFGLOCKR3 0x2C
#define RCC_R0CIDCFGR 0x30
#define RCC_R0SEMCR 0x34
#define RCC_R1CIDCFGR 0x38
#define RCC_R1SEMCR 0x3C
#define RCC_R2CIDCFGR 0x40
#define RCC_R2SEMCR 0x44
#define RCC_R3CIDCFGR 0x48
#define RCC_R3SEMCR 0x4C
#define RCC_R4CIDCFGR 0x50
#define RCC_R4SEMCR 0x54
#define RCC_R5CIDCFGR 0x58
#define RCC_R5SEMCR 0x5C
#define RCC_R6CIDCFGR 0x60
#define RCC_R6SEMCR 0x64
#define RCC_R7CIDCFGR 0x68
#define RCC_R7SEMCR 0x6C
#define RCC_R8CIDCFGR 0x70
#define RCC_R8SEMCR 0x74
#define RCC_R9CIDCFGR 0x78
#define RCC_R9SEMCR 0x7C
#define RCC_R10CIDCFGR 0x80
#define RCC_R10SEMCR 0x84
#define RCC_R11CIDCFGR 0x88
#define RCC_R11SEMCR 0x8C
#define RCC_R12CIDCFGR 0x90
#define RCC_R12SEMCR 0x94
#define RCC_R13CIDCFGR 0x98
#define RCC_R13SEMCR 0x9C
#define RCC_R14CIDCFGR 0xA0
#define RCC_R14SEMCR 0xA4
#define RCC_R15CIDCFGR 0xA8
#define RCC_R15SEMCR 0xAC
#define RCC_R16CIDCFGR 0xB0
#define RCC_R16SEMCR 0xB4
#define RCC_R17CIDCFGR 0xB8
#define RCC_R17SEMCR 0xBC
#define RCC_R18CIDCFGR 0xC0
#define RCC_R18SEMCR 0xC4
#define RCC_R19CIDCFGR 0xC8
#define RCC_R19SEMCR 0xCC
#define RCC_R20CIDCFGR 0xD0
#define RCC_R20SEMCR 0xD4
#define RCC_R21CIDCFGR 0xD8
#define RCC_R21SEMCR 0xDC
#define RCC_R22CIDCFGR 0xE0
#define RCC_R22SEMCR 0xE4
#define RCC_R23CIDCFGR 0xE8
#define RCC_R23SEMCR 0xEC
#define RCC_R24CIDCFGR 0xF0
#define RCC_R24SEMCR 0xF4
#define RCC_R25CIDCFGR 0xF8
#define RCC_R25SEMCR 0xFC
#define RCC_R26CIDCFGR 0x100
#define RCC_R26SEMCR 0x104
#define RCC_R27CIDCFGR 0x108
#define RCC_R27SEMCR 0x10C
#define RCC_R28CIDCFGR 0x110
#define RCC_R28SEMCR 0x114
#define RCC_R29CIDCFGR 0x118
#define RCC_R29SEMCR 0x11C
#define RCC_R30CIDCFGR 0x120
#define RCC_R30SEMCR 0x124
#define RCC_R31CIDCFGR 0x128
#define RCC_R31SEMCR 0x12C
#define RCC_R32CIDCFGR 0x130
#define RCC_R32SEMCR 0x134
#define RCC_R33CIDCFGR 0x138
#define RCC_R33SEMCR 0x13C
#define RCC_R34CIDCFGR 0x140
#define RCC_R34SEMCR 0x144
#define RCC_R35CIDCFGR 0x148
#define RCC_R35SEMCR 0x14C
#define RCC_R36CIDCFGR 0x150
#define RCC_R36SEMCR 0x154
#define RCC_R37CIDCFGR 0x158
#define RCC_R37SEMCR 0x15C
#define RCC_R38CIDCFGR 0x160
#define RCC_R38SEMCR 0x164
#define RCC_R39CIDCFGR 0x168
#define RCC_R39SEMCR 0x16C
#define RCC_R40CIDCFGR 0x170
#define RCC_R40SEMCR 0x174
#define RCC_R41CIDCFGR 0x178
#define RCC_R41SEMCR 0x17C
#define RCC_R42CIDCFGR 0x180
#define RCC_R42SEMCR 0x184
#define RCC_R43CIDCFGR 0x188
#define RCC_R43SEMCR 0x18C
#define RCC_R44CIDCFGR 0x190
#define RCC_R44SEMCR 0x194
#define RCC_R45CIDCFGR 0x198
#define RCC_R45SEMCR 0x19C
#define RCC_R46CIDCFGR 0x1A0
#define RCC_R46SEMCR 0x1A4
#define RCC_R47CIDCFGR 0x1A8
#define RCC_R47SEMCR 0x1AC
#define RCC_R48CIDCFGR 0x1B0
#define RCC_R48SEMCR 0x1B4
#define RCC_R49CIDCFGR 0x1B8
#define RCC_R49SEMCR 0x1BC
#define RCC_R50CIDCFGR 0x1C0
#define RCC_R50SEMCR 0x1C4
#define RCC_R51CIDCFGR 0x1C8
#define RCC_R51SEMCR 0x1CC
#define RCC_R52CIDCFGR 0x1D0
#define RCC_R52SEMCR 0x1D4
#define RCC_R53CIDCFGR 0x1D8
#define RCC_R53SEMCR 0x1DC
#define RCC_R54CIDCFGR 0x1E0
#define RCC_R54SEMCR 0x1E4
#define RCC_R55CIDCFGR 0x1E8
#define RCC_R55SEMCR 0x1EC
#define RCC_R56CIDCFGR 0x1F0
#define RCC_R56SEMCR 0x1F4
#define RCC_R57CIDCFGR 0x1F8
#define RCC_R57SEMCR 0x1FC
#define RCC_R58CIDCFGR 0x200
#define RCC_R58SEMCR 0x204
#define RCC_R59CIDCFGR 0x208
#define RCC_R59SEMCR 0x20C
#define RCC_R60CIDCFGR 0x210
#define RCC_R60SEMCR 0x214
#define RCC_R61CIDCFGR 0x218
#define RCC_R61SEMCR 0x21C
#define RCC_R62CIDCFGR 0x220
#define RCC_R62SEMCR 0x224
#define RCC_R63CIDCFGR 0x228
#define RCC_R63SEMCR 0x22C
#define RCC_R64CIDCFGR 0x230
#define RCC_R64SEMCR 0x234
#define RCC_R65CIDCFGR 0x238
#define RCC_R65SEMCR 0x23C
#define RCC_R66CIDCFGR 0x240
#define RCC_R66SEMCR 0x244
#define RCC_R67CIDCFGR 0x248
#define RCC_R67SEMCR 0x24C
#define RCC_R68CIDCFGR 0x250
#define RCC_R68SEMCR 0x254
#define RCC_R69CIDCFGR 0x258
#define RCC_R69SEMCR 0x25C
#define RCC_R70CIDCFGR 0x260
#define RCC_R70SEMCR 0x264
#define RCC_R71CIDCFGR 0x268
#define RCC_R71SEMCR 0x26C
#define RCC_R72CIDCFGR 0x270
#define RCC_R72SEMCR 0x274
#define RCC_R73CIDCFGR 0x278
#define RCC_R73SEMCR 0x27C
#define RCC_R74CIDCFGR 0x280
#define RCC_R74SEMCR 0x284
#define RCC_R75CIDCFGR 0x288
#define RCC_R75SEMCR 0x28C
#define RCC_R76CIDCFGR 0x290
#define RCC_R76SEMCR 0x294
#define RCC_R77CIDCFGR 0x298
#define RCC_R77SEMCR 0x29C
#define RCC_R78CIDCFGR 0x2A0
#define RCC_R78SEMCR 0x2A4
#define RCC_R79CIDCFGR 0x2A8
#define RCC_R79SEMCR 0x2AC
#define RCC_R80CIDCFGR 0x2B0
#define RCC_R80SEMCR 0x2B4
#define RCC_R81CIDCFGR 0x2B8
#define RCC_R81SEMCR 0x2BC
#define RCC_R82CIDCFGR 0x2C0
#define RCC_R82SEMCR 0x2C4
#define RCC_R83CIDCFGR 0x2C8
#define RCC_R83SEMCR 0x2CC
#define RCC_R84CIDCFGR 0x2D0
#define RCC_R84SEMCR 0x2D4
#define RCC_R85CIDCFGR 0x2D8
#define RCC_R85SEMCR 0x2DC
#define RCC_R86CIDCFGR 0x2E0
#define RCC_R86SEMCR 0x2E4
#define RCC_R87CIDCFGR 0x2E8
#define RCC_R87SEMCR 0x2EC
#define RCC_R88CIDCFGR 0x2F0
#define RCC_R88SEMCR 0x2F4
#define RCC_R89CIDCFGR 0x2F8
#define RCC_R89SEMCR 0x2FC
#define RCC_R90CIDCFGR 0x300
#define RCC_R90SEMCR 0x304
#define RCC_R91CIDCFGR 0x308
#define RCC_R91SEMCR 0x30C
#define RCC_R92CIDCFGR 0x310
#define RCC_R92SEMCR 0x314
#define RCC_R93CIDCFGR 0x318
#define RCC_R93SEMCR 0x31C
#define RCC_R94CIDCFGR 0x320
#define RCC_R94SEMCR 0x324
#define RCC_R95CIDCFGR 0x328
#define RCC_R95SEMCR 0x32C
#define RCC_R96CIDCFGR 0x330
#define RCC_R96SEMCR 0x334
#define RCC_R97CIDCFGR 0x338
#define RCC_R97SEMCR 0x33C
#define RCC_R98CIDCFGR 0x340
#define RCC_R98SEMCR 0x344
#define RCC_R99CIDCFGR 0x348
#define RCC_R99SEMCR 0x34C
#define RCC_R100CIDCFGR 0x350
#define RCC_R100SEMCR 0x354
#define RCC_R101CIDCFGR 0x358
#define RCC_R101SEMCR 0x35C
#define RCC_R102CIDCFGR 0x360
#define RCC_R102SEMCR 0x364
#define RCC_R103CIDCFGR 0x368
#define RCC_R103SEMCR 0x36C
#define RCC_R104CIDCFGR 0x370
#define RCC_R104SEMCR 0x374
#define RCC_R105CIDCFGR 0x378
#define RCC_R105SEMCR 0x37C
#define RCC_R106CIDCFGR 0x380
#define RCC_R106SEMCR 0x384
#define RCC_R107CIDCFGR 0x388
#define RCC_R107SEMCR 0x38C
#define RCC_R108CIDCFGR 0x390
#define RCC_R108SEMCR 0x394
#define RCC_R109CIDCFGR 0x398
#define RCC_R109SEMCR 0x39C
#define RCC_R110CIDCFGR 0x3A0
#define RCC_R110SEMCR 0x3A4
#define RCC_R111CIDCFGR 0x3A8
#define RCC_R111SEMCR 0x3AC
#define RCC_R112CIDCFGR 0x3B0
#define RCC_R112SEMCR 0x3B4
#define RCC_R113CIDCFGR 0x3B8
#define RCC_R113SEMCR 0x3BC
#define RCC_GRSTCSETR 0x400
#define RCC_C1RSTCSETR 0x404
#define RCC_C1P1RSTCSETR 0x408
#define RCC_C2RSTCSETR 0x40C
#define RCC_HWRSTSCLRR 0x410
#define RCC_C1HWRSTSCLRR 0x414
#define RCC_C2HWRSTSCLRR 0x418
#define RCC_C1BOOTRSTSSETR 0x41C
#define RCC_C1BOOTRSTSCLRR 0x420
#define RCC_C2BOOTRSTSSETR 0x424
#define RCC_C2BOOTRSTSCLRR 0x428
#define RCC_C1SREQSETR 0x42C
#define RCC_C1SREQCLRR 0x430
#define RCC_CPUBOOTCR 0x434
#define RCC_STBYBOOTCR 0x438
#define RCC_LEGBOOTCR 0x43C
#define RCC_BDCR 0x440
#define RCC_D3DCR 0x444
#define RCC_D3DSR 0x448
#define RCC_RDCR 0x44C
#define RCC_C1MSRDCR 0x450
#define RCC_PWRLPDLYCR 0x454
#define RCC_C1CIESETR 0x458
#define RCC_C1CIFCLRR 0x45C
#define RCC_C2CIESETR 0x460
#define RCC_C2CIFCLRR 0x464
#define RCC_IWDGC1FZSETR 0x468
#define RCC_IWDGC1FZCLRR 0x46C
#define RCC_IWDGC1CFGSETR 0x470
#define RCC_IWDGC1CFGCLRR 0x474
#define RCC_IWDGC2FZSETR 0x478
#define RCC_IWDGC2FZCLRR 0x47C
#define RCC_IWDGC2CFGSETR 0x480
#define RCC_IWDGC2CFGCLRR 0x484
#define RCC_IWDGC3CFGSETR 0x488
#define RCC_IWDGC3CFGCLRR 0x48C
#define RCC_C3CFGR 0x490
#define RCC_MCO1CFGR 0x494
#define RCC_MCO2CFGR 0x498
#define RCC_OCENSETR 0x49C
#define RCC_OCENCLRR 0x4A0
#define RCC_OCRDYR 0x4A4
#define RCC_HSICFGR 0x4A8
#define RCC_MSICFGR 0x4AC
#define RCC_RTCDIVR 0x4B0
#define RCC_APB1DIVR 0x4B4
#define RCC_APB2DIVR 0x4B8
#define RCC_APB3DIVR 0x4BC
#define RCC_APB4DIVR 0x4C0
#define RCC_APBDBGDIVR 0x4C4
#define RCC_TIMG1PRER 0x4C8
#define RCC_TIMG2PRER 0x4CC
#define RCC_LSMCUDIVR 0x4D0
#define RCC_DDRCPCFGR 0x4D4
#define RCC_DDRCAPBCFGR 0x4D8
#define RCC_DDRPHYCAPBCFGR 0x4DC
#define RCC_DDRPHYCCFGR 0x4E0
#define RCC_DDRCFGR 0x4E4
#define RCC_DDRITFCFGR 0x4E8
#define RCC_SYSRAMCFGR 0x4F0
#define RCC_VDERAMCFGR 0x4F4
#define RCC_SRAM1CFGR 0x4F8
#define RCC_SRAM2CFGR 0x4FC
#define RCC_RETRAMCFGR 0x500
#define RCC_BKPSRAMCFGR 0x504
#define RCC_LPSRAM1CFGR 0x508
#define RCC_LPSRAM2CFGR 0x50C
#define RCC_LPSRAM3CFGR 0x510
#define RCC_OSPI1CFGR 0x514
#define RCC_OSPI2CFGR 0x518
#define RCC_FMCCFGR 0x51C
#define RCC_DBGCFGR 0x520
#define RCC_STM500CFGR 0x524
#define RCC_ETRCFGR 0x528
#define RCC_GPIOACFGR 0x52C
#define RCC_GPIOBCFGR 0x530
#define RCC_GPIOCCFGR 0x534
#define RCC_GPIODCFGR 0x538
#define RCC_GPIOECFGR 0x53C
#define RCC_GPIOFCFGR 0x540
#define RCC_GPIOGCFGR 0x544
#define RCC_GPIOHCFGR 0x548
#define RCC_GPIOICFGR 0x54C
#define RCC_GPIOJCFGR 0x550
#define RCC_GPIOKCFGR 0x554
#define RCC_GPIOZCFGR 0x558
#define RCC_HPDMA1CFGR 0x55C
#define RCC_HPDMA2CFGR 0x560
#define RCC_HPDMA3CFGR 0x564
#define RCC_LPDMACFGR 0x568
#define RCC_HSEMCFGR 0x56C
#define RCC_IPCC1CFGR 0x570
#define RCC_IPCC2CFGR 0x574
#define RCC_RTCCFGR 0x578
#define RCC_SYSCPU1CFGR 0x580
#define RCC_BSECCFGR 0x584
#define RCC_IS2MCFGR 0x58C
#define RCC_PLL2CFGR1 0x590
#define RCC_PLL2CFGR2 0x594
#define RCC_PLL2CFGR3 0x598
#define RCC_PLL2CFGR4 0x59C
#define RCC_PLL2CFGR5 0x5A0
#define RCC_PLL2CFGR6 0x5A8
#define RCC_PLL2CFGR7 0x5AC
#define RCC_PLL3CFGR1 0x5B8
#define RCC_PLL3CFGR2 0x5BC
#define RCC_PLL3CFGR3 0x5C0
#define RCC_PLL3CFGR4 0x5C4
#define RCC_PLL3CFGR5 0x5C8
#define RCC_PLL3CFGR6 0x5D0
#define RCC_PLL3CFGR7 0x5D4
#define RCC_HSIFMONCR 0x5E0
#define RCC_HSIFVALR 0x5E4
#define RCC_TIM1CFGR 0x700
#define RCC_TIM2CFGR 0x704
#define RCC_TIM3CFGR 0x708
#define RCC_TIM4CFGR 0x70C
#define RCC_TIM5CFGR 0x710
#define RCC_TIM6CFGR 0x714
#define RCC_TIM7CFGR 0x718
#define RCC_TIM8CFGR 0x71C
#define RCC_TIM10CFGR 0x720
#define RCC_TIM11CFGR 0x724
#define RCC_TIM12CFGR 0x728
#define RCC_TIM13CFGR 0x72C
#define RCC_TIM14CFGR 0x730
#define RCC_TIM15CFGR 0x734
#define RCC_TIM16CFGR 0x738
#define RCC_TIM17CFGR 0x73C
#define RCC_TIM20CFGR 0x740
#define RCC_LPTIM1CFGR 0x744
#define RCC_LPTIM2CFGR 0x748
#define RCC_LPTIM3CFGR 0x74C
#define RCC_LPTIM4CFGR 0x750
#define RCC_LPTIM5CFGR 0x754
#define RCC_SPI1CFGR 0x758
#define RCC_SPI2CFGR 0x75C
#define RCC_SPI3CFGR 0x760
#define RCC_SPI4CFGR 0x764
#define RCC_SPI5CFGR 0x768
#define RCC_SPI6CFGR 0x76C
#define RCC_SPI7CFGR 0x770
#define RCC_SPI8CFGR 0x774
#define RCC_SPDIFRXCFGR 0x778
#define RCC_USART1CFGR 0x77C
#define RCC_USART2CFGR 0x780
#define RCC_USART3CFGR 0x784
#define RCC_UART4CFGR 0x788
#define RCC_UART5CFGR 0x78C
#define RCC_USART6CFGR 0x790
#define RCC_UART7CFGR 0x794
#define RCC_UART8CFGR 0x798
#define RCC_UART9CFGR 0x79C
#define RCC_LPUART1CFGR 0x7A0
#define RCC_I2C1CFGR 0x7A4
#define RCC_I2C2CFGR 0x7A8
#define RCC_I2C3CFGR 0x7AC
#define RCC_I2C4CFGR 0x7B0
#define RCC_I2C5CFGR 0x7B4
#define RCC_I2C6CFGR 0x7B8
#define RCC_I2C7CFGR 0x7BC
#define RCC_I2C8CFGR 0x7C0
#define RCC_SAI1CFGR 0x7C4
#define RCC_SAI2CFGR 0x7C8
#define RCC_SAI3CFGR 0x7CC
#define RCC_SAI4CFGR 0x7D0
#define RCC_MDF1CFGR 0x7D8
#define RCC_ADF1CFGR 0x7DC
#define RCC_FDCANCFGR 0x7E0
#define RCC_HDPCFGR 0x7E4
#define RCC_ADC12CFGR 0x7E8
#define RCC_ADC3CFGR 0x7EC
#define RCC_ETH1CFGR 0x7F0
#define RCC_ETH2CFGR 0x7F4
#define RCC_USBHCFGR 0x7FC
#define RCC_USB2PHY1CFGR 0x800
#define RCC_USB2PHY2CFGR 0x804
#define RCC_USB3DRCFGR 0x808
#define RCC_USB3PCIEPHYCFGR 0x80C
#define RCC_PCIECFGR 0x810
#define RCC_USBTCCFGR 0x814
#define RCC_ETHSWCFGR 0x818
#define RCC_ETHSWACMCFGR 0x81C
#define RCC_ETHSWACMMSGCFGR 0x820
#define RCC_STGENCFGR 0x824
#define RCC_SDMMC1CFGR 0x830
#define RCC_SDMMC2CFGR 0x834
#define RCC_SDMMC3CFGR 0x838
#define RCC_GPUCFGR 0x83C
#define RCC_LTDCCFGR 0x840
#define RCC_DSICFGR 0x844
#define RCC_LVDSCFGR 0x850
#define RCC_CSICFGR 0x858
#define RCC_DCMIPPCFGR 0x85C
#define RCC_CCICFGR 0x860
#define RCC_VDECCFGR 0x864
#define RCC_VENCCFGR 0x868
#define RCC_RNGCFGR 0x870
#define RCC_PKACFGR 0x874
#define RCC_SAESCFGR 0x878
#define RCC_HASHCFGR 0x87C
#define RCC_CRYP1CFGR 0x880
#define RCC_CRYP2CFGR 0x884
#define RCC_IWDG1CFGR 0x888
#define RCC_IWDG2CFGR 0x88C
#define RCC_IWDG3CFGR 0x890
#define RCC_IWDG4CFGR 0x894
#define RCC_IWDG5CFGR 0x898
#define RCC_WWDG1CFGR 0x89C
#define RCC_WWDG2CFGR 0x8A0
#define RCC_VREFCFGR 0x8A8
#define RCC_DTSCFGR 0x8AC
#define RCC_CRCCFGR 0x8B4
#define RCC_SERCCFGR 0x8B8
#define RCC_OSPIIOMCFGR 0x8BC
#define RCC_GICV2MCFGR 0x8C0
#define RCC_I3C1CFGR 0x8C8
#define RCC_I3C2CFGR 0x8CC
#define RCC_I3C3CFGR 0x8D0
#define RCC_I3C4CFGR 0x8D4
#define RCC_MUXSELCFGR 0x1000
#define RCC_XBAR0CFGR 0x1018
#define RCC_XBAR1CFGR 0x101C
#define RCC_XBAR2CFGR 0x1020
#define RCC_XBAR3CFGR 0x1024
#define RCC_XBAR4CFGR 0x1028
#define RCC_XBAR5CFGR 0x102C
#define RCC_XBAR6CFGR 0x1030
#define RCC_XBAR7CFGR 0x1034
#define RCC_XBAR8CFGR 0x1038
#define RCC_XBAR9CFGR 0x103C
#define RCC_XBAR10CFGR 0x1040
#define RCC_XBAR11CFGR 0x1044
#define RCC_XBAR12CFGR 0x1048
#define RCC_XBAR13CFGR 0x104C
#define RCC_XBAR14CFGR 0x1050
#define RCC_XBAR15CFGR 0x1054
#define RCC_XBAR16CFGR 0x1058
#define RCC_XBAR17CFGR 0x105C
#define RCC_XBAR18CFGR 0x1060
#define RCC_XBAR19CFGR 0x1064
#define RCC_XBAR20CFGR 0x1068
#define RCC_XBAR21CFGR 0x106C
#define RCC_XBAR22CFGR 0x1070
#define RCC_XBAR23CFGR 0x1074
#define RCC_XBAR24CFGR 0x1078
#define RCC_XBAR25CFGR 0x107C
#define RCC_XBAR26CFGR 0x1080
#define RCC_XBAR27CFGR 0x1084
#define RCC_XBAR28CFGR 0x1088
#define RCC_XBAR29CFGR 0x108C
#define RCC_XBAR30CFGR 0x1090
#define RCC_XBAR31CFGR 0x1094
#define RCC_XBAR32CFGR 0x1098
#define RCC_XBAR33CFGR 0x109C
#define RCC_XBAR34CFGR 0x10A0
#define RCC_XBAR35CFGR 0x10A4
#define RCC_XBAR36CFGR 0x10A8
#define RCC_XBAR37CFGR 0x10AC
#define RCC_XBAR38CFGR 0x10B0
#define RCC_XBAR39CFGR 0x10B4
#define RCC_XBAR40CFGR 0x10B8
#define RCC_XBAR41CFGR 0x10BC
#define RCC_XBAR42CFGR 0x10C0
#define RCC_XBAR43CFGR 0x10C4
#define RCC_XBAR44CFGR 0x10C8
#define RCC_XBAR45CFGR 0x10CC
#define RCC_XBAR46CFGR 0x10D0
#define RCC_XBAR47CFGR 0x10D4
#define RCC_XBAR48CFGR 0x10D8
#define RCC_XBAR49CFGR 0x10DC
#define RCC_XBAR50CFGR 0x10E0
#define RCC_XBAR51CFGR 0x10E4
#define RCC_XBAR52CFGR 0x10E8
#define RCC_XBAR53CFGR 0x10EC
#define RCC_XBAR54CFGR 0x10F0
#define RCC_XBAR55CFGR 0x10F4
#define RCC_XBAR56CFGR 0x10F8
#define RCC_XBAR57CFGR 0x10FC
#define RCC_XBAR58CFGR 0x1100
#define RCC_XBAR59CFGR 0x1104
#define RCC_XBAR60CFGR 0x1108
#define RCC_XBAR61CFGR 0x110C
#define RCC_XBAR62CFGR 0x1110
#define RCC_XBAR63CFGR 0x1114
#define RCC_PREDIV0CFGR 0x1118
#define RCC_PREDIV1CFGR 0x111C
#define RCC_PREDIV2CFGR 0x1120
#define RCC_PREDIV3CFGR 0x1124
#define RCC_PREDIV4CFGR 0x1128
#define RCC_PREDIV5CFGR 0x112C
#define RCC_PREDIV6CFGR 0x1130
#define RCC_PREDIV7CFGR 0x1134
#define RCC_PREDIV8CFGR 0x1138
#define RCC_PREDIV9CFGR 0x113C
#define RCC_PREDIV10CFGR 0x1140
#define RCC_PREDIV11CFGR 0x1144
#define RCC_PREDIV12CFGR 0x1148
#define RCC_PREDIV13CFGR 0x114C
#define RCC_PREDIV14CFGR 0x1150
#define RCC_PREDIV15CFGR 0x1154
#define RCC_PREDIV16CFGR 0x1158
#define RCC_PREDIV17CFGR 0x115C
#define RCC_PREDIV18CFGR 0x1160
#define RCC_PREDIV19CFGR 0x1164
#define RCC_PREDIV20CFGR 0x1168
#define RCC_PREDIV21CFGR 0x116C
#define RCC_PREDIV22CFGR 0x1170
#define RCC_PREDIV23CFGR 0x1174
#define RCC_PREDIV24CFGR 0x1178
#define RCC_PREDIV25CFGR 0x117C
#define RCC_PREDIV26CFGR 0x1180
#define RCC_PREDIV27CFGR 0x1184
#define RCC_PREDIV28CFGR 0x1188
#define RCC_PREDIV29CFGR 0x118C
#define RCC_PREDIV30CFGR 0x1190
#define RCC_PREDIV31CFGR 0x1194
#define RCC_PREDIV32CFGR 0x1198
#define RCC_PREDIV33CFGR 0x119C
#define RCC_PREDIV34CFGR 0x11A0
#define RCC_PREDIV35CFGR 0x11A4
#define RCC_PREDIV36CFGR 0x11A8
#define RCC_PREDIV37CFGR 0x11AC
#define RCC_PREDIV38CFGR 0x11B0
#define RCC_PREDIV39CFGR 0x11B4
#define RCC_PREDIV40CFGR 0x11B8
#define RCC_PREDIV41CFGR 0x11BC
#define RCC_PREDIV42CFGR 0x11C0
#define RCC_PREDIV43CFGR 0x11C4
#define RCC_PREDIV44CFGR 0x11C8
#define RCC_PREDIV45CFGR 0x11CC
#define RCC_PREDIV46CFGR 0x11D0
#define RCC_PREDIV47CFGR 0x11D4
#define RCC_PREDIV48CFGR 0x11D8
#define RCC_PREDIV49CFGR 0x11DC
#define RCC_PREDIV50CFGR 0x11E0
#define RCC_PREDIV51CFGR 0x11E4
#define RCC_PREDIV52CFGR 0x11E8
#define RCC_PREDIV53CFGR 0x11EC
#define RCC_PREDIV54CFGR 0x11F0
#define RCC_PREDIV55CFGR 0x11F4
#define RCC_PREDIV56CFGR 0x11F8
#define RCC_PREDIV57CFGR 0x11FC
#define RCC_PREDIV58CFGR 0x1200
#define RCC_PREDIV59CFGR 0x1204
#define RCC_PREDIV60CFGR 0x1208
#define RCC_PREDIV61CFGR 0x120C
#define RCC_PREDIV62CFGR 0x1210
#define RCC_PREDIV63CFGR 0x1214
#define RCC_PREDIVSR1 0x1218
#define RCC_PREDIVSR2 0x121C
#define RCC_FINDIV0CFGR 0x1224
#define RCC_FINDIV1CFGR 0x1228
#define RCC_FINDIV2CFGR 0x122C
#define RCC_FINDIV3CFGR 0x1230
#define RCC_FINDIV4CFGR 0x1234
#define RCC_FINDIV5CFGR 0x1238
#define RCC_FINDIV6CFGR 0x123C
#define RCC_FINDIV7CFGR 0x1240
#define RCC_FINDIV8CFGR 0x1244
#define RCC_FINDIV9CFGR 0x1248
#define RCC_FINDIV10CFGR 0x124C
#define RCC_FINDIV11CFGR 0x1250
#define RCC_FINDIV12CFGR 0x1254
#define RCC_FINDIV13CFGR 0x1258
#define RCC_FINDIV14CFGR 0x125C
#define RCC_FINDIV15CFGR 0x1260
#define RCC_FINDIV16CFGR 0x1264
#define RCC_FINDIV17CFGR 0x1268
#define RCC_FINDIV18CFGR 0x126C
#define RCC_FINDIV19CFGR 0x1270
#define RCC_FINDIV20CFGR 0x1274
#define RCC_FINDIV21CFGR 0x1278
#define RCC_FINDIV22CFGR 0x127C
#define RCC_FINDIV23CFGR 0x1280
#define RCC_FINDIV24CFGR 0x1284
#define RCC_FINDIV25CFGR 0x1288
#define RCC_FINDIV26CFGR 0x128C
#define RCC_FINDIV27CFGR 0x1290
#define RCC_FINDIV28CFGR 0x1294
#define RCC_FINDIV29CFGR 0x1298
#define RCC_FINDIV30CFGR 0x129C
#define RCC_FINDIV31CFGR 0x12A0
#define RCC_FINDIV32CFGR 0x12A4
#define RCC_FINDIV33CFGR 0x12A8
#define RCC_FINDIV34CFGR 0x12AC
#define RCC_FINDIV35CFGR 0x12B0
#define RCC_FINDIV36CFGR 0x12B4
#define RCC_FINDIV37CFGR 0x12B8
#define RCC_FINDIV38CFGR 0x12BC
#define RCC_FINDIV39CFGR 0x12C0
#define RCC_FINDIV40CFGR 0x12C4
#define RCC_FINDIV41CFGR 0x12C8
#define RCC_FINDIV42CFGR 0x12CC
#define RCC_FINDIV43CFGR 0x12D0
#define RCC_FINDIV44CFGR 0x12D4
#define RCC_FINDIV45CFGR 0x12D8
#define RCC_FINDIV46CFGR 0x12DC
#define RCC_FINDIV47CFGR 0x12E0
#define RCC_FINDIV48CFGR 0x12E4
#define RCC_FINDIV49CFGR 0x12E8
#define RCC_FINDIV50CFGR 0x12EC
#define RCC_FINDIV51CFGR 0x12F0
#define RCC_FINDIV52CFGR 0x12F4
#define RCC_FINDIV53CFGR 0x12F8
#define RCC_FINDIV54CFGR 0x12FC
#define RCC_FINDIV55CFGR 0x1300
#define RCC_FINDIV56CFGR 0x1304
#define RCC_FINDIV57CFGR 0x1308
#define RCC_FINDIV58CFGR 0x130C
#define RCC_FINDIV59CFGR 0x1310
#define RCC_FINDIV60CFGR 0x1314
#define RCC_FINDIV61CFGR 0x1318
#define RCC_FINDIV62CFGR 0x131C
#define RCC_FINDIV63CFGR 0x1320
#define RCC_FINDIVSR1 0x1324
#define RCC_FINDIVSR2 0x1328
#define RCC_FCALCOBS0CFGR 0x1340
#define RCC_FCALCOBS1CFGR 0x1344
#define RCC_FCALCREFCFGR 0x1348
#define RCC_FCALCCR1 0x134C
#define RCC_FCALCCR2 0x1354
#define RCC_FCALCSR 0x1358
#define RCC_PLL4CFGR1 0x1360
#define RCC_PLL4CFGR2 0x1364
#define RCC_PLL4CFGR3 0x1368
#define RCC_PLL4CFGR4 0x136C
#define RCC_PLL4CFGR5 0x1370
#define RCC_PLL4CFGR6 0x1378
#define RCC_PLL4CFGR7 0x137C
#define RCC_PLL5CFGR1 0x1388
#define RCC_PLL5CFGR2 0x138C
#define RCC_PLL5CFGR3 0x1390
#define RCC_PLL5CFGR4 0x1394
#define RCC_PLL5CFGR5 0x1398
#define RCC_PLL5CFGR6 0x13A0
#define RCC_PLL5CFGR7 0x13A4
#define RCC_PLL6CFGR1 0x13B0
#define RCC_PLL6CFGR2 0x13B4
#define RCC_PLL6CFGR3 0x13B8
#define RCC_PLL6CFGR4 0x13BC
#define RCC_PLL6CFGR5 0x13C0
#define RCC_PLL6CFGR6 0x13C8
#define RCC_PLL6CFGR7 0x13CC
#define RCC_PLL7CFGR1 0x13D8
#define RCC_PLL7CFGR2 0x13DC
#define RCC_PLL7CFGR3 0x13E0
#define RCC_PLL7CFGR4 0x13E4
#define RCC_PLL7CFGR5 0x13E8
#define RCC_PLL7CFGR6 0x13F0
#define RCC_PLL7CFGR7 0x13F4
#define RCC_PLL8CFGR1 0x1400
#define RCC_PLL8CFGR2 0x1404
#define RCC_PLL8CFGR3 0x1408
#define RCC_PLL8CFGR4 0x140C
#define RCC_PLL8CFGR5 0x1410
#define RCC_PLL8CFGR6 0x1418
#define RCC_PLL8CFGR7 0x141C
#define RCC_VERR 0xFFF4
#define RCC_IDR 0xFFF8
#define RCC_SIDR 0xFFFC
#endif /* STM32MP25_RCC_H */
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
View file @ 7552d1b9
......@@ -125,6 +125,7 @@ static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun20i_d1_r_ccu_ids);
static struct platform_driver sun20i_d1_r_ccu_driver = {
.probe = sun20i_d1_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View file @ 7552d1b9
......@@ -1394,6 +1394,7 @@ static const struct of_device_id sun20i_d1_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun20i_d1_ccu_ids);
static struct platform_driver sun20i_d1_ccu_driver = {
.probe = sun20i_d1_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
View file @ 7552d1b9
......@@ -1481,6 +1481,7 @@ static const struct of_device_id sun4i_a10_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_a10_ccu_ids);
static struct platform_driver sun4i_a10_ccu_driver = {
.probe = sun4i_a10_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
View file @ 7552d1b9
......@@ -202,6 +202,7 @@ static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a100_r_ccu_ids);
static struct platform_driver sun50i_a100_r_ccu_driver = {
.probe = sun50i_a100_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
View file @ 7552d1b9
......@@ -1264,6 +1264,7 @@ static const struct of_device_id sun50i_a100_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a100_ccu_ids);
static struct platform_driver sun50i_a100_ccu_driver = {
.probe = sun50i_a100_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View file @ 7552d1b9
......@@ -171,11 +171,13 @@ static struct ccu_nkm pll_mipi_clk = {
* user manual, and by experiments the PLL doesn't work without
* these bits toggled.
*/
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.max_m_n_ratio = 3,
.min_parent_m_ratio = 24000000,
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
......@@ -978,6 +980,7 @@ static const struct of_device_id sun50i_a64_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a64-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a64_ccu_ids);
static struct platform_driver sun50i_a64_ccu_driver = {
.probe = sun50i_a64_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View file @ 7552d1b9
......@@ -244,6 +244,7 @@ static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h6_r_ccu_ids);
static struct platform_driver sun50i_h6_r_ccu_driver = {
.probe = sun50i_h6_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
View file @ 7552d1b9
......@@ -1259,6 +1259,7 @@ static const struct of_device_id sun50i_h6_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h6-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h6_ccu_ids);
static struct platform_driver sun50i_h6_ccu_driver = {
.probe = sun50i_h6_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View file @ 7552d1b9
......@@ -1154,6 +1154,7 @@ static const struct of_device_id sun50i_h616_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h616-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h616_ccu_ids);
static struct platform_driver sun50i_h616_ccu_driver = {
.probe = sun50i_h616_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
View file @ 7552d1b9
......@@ -1271,6 +1271,7 @@ static const struct of_device_id sun6i_a31_ccu_ids[] = {
{ .compatible = "allwinner,sun6i-a31-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun6i_a31_ccu_ids);
static struct platform_driver sun6i_a31_ccu_driver = {
.probe = sun6i_a31_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
View file @ 7552d1b9
......@@ -336,6 +336,7 @@ static const struct of_device_id sun6i_rtc_ccu_match[] = {
},
{},
};
MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
{
......
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
View file @ 7552d1b9
......@@ -751,6 +751,7 @@ static const struct of_device_id sun8i_a23_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a23-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a23_ccu_ids);
static struct platform_driver sun8i_a23_ccu_driver = {
.probe = sun8i_a23_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
View file @ 7552d1b9
......@@ -823,6 +823,7 @@ static const struct of_device_id sun8i_a33_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a33-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a33_ccu_ids);
static struct platform_driver sun8i_a33_ccu_driver = {
.probe = sun8i_a33_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
View file @ 7552d1b9
......@@ -911,6 +911,7 @@ static const struct of_device_id sun8i_a83t_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a83t_ccu_ids);
static struct platform_driver sun8i_a83t_ccu_driver = {
.probe = sun8i_a83t_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View file @ 7552d1b9
......@@ -337,6 +337,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids);
static struct platform_driver sunxi_de2_clk_driver = {
.probe = sunxi_de2_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View file @ 7552d1b9
......@@ -1082,6 +1082,7 @@ static const struct of_device_id sun8i_h3_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_h3_ccu_ids);
static struct platform_driver sun8i_h3_ccu_driver = {
.probe = sun8i_h3_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View file @ 7552d1b9
......@@ -262,6 +262,7 @@ static const struct of_device_id sun8i_r_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_r_ccu_ids);
static struct platform_driver sun8i_r_ccu_driver = {
.probe = sun8i_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View file @ 7552d1b9
......@@ -1363,6 +1363,7 @@ static const struct of_device_id sun8i_r40_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-r40-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_r40_ccu_ids);
static struct platform_driver sun8i_r40_ccu_driver = {
.probe = sun8i_r40_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View file @ 7552d1b9
......@@ -768,6 +768,7 @@ static const struct of_device_id sun8i_v3s_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_v3s_ccu_ids);
static struct platform_driver sun8i_v3s_ccu_driver = {
.probe = sun8i_v3s_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View file @ 7552d1b9
......@@ -254,6 +254,7 @@ static const struct of_device_id sun9i_a80_de_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-de-clks" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_de_clk_ids);
static struct platform_driver sun9i_a80_de_clk_driver = {
.probe = sun9i_a80_de_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View file @ 7552d1b9
......@@ -127,6 +127,7 @@ static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-usb-clks" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_usb_clk_ids);
static struct platform_driver sun9i_a80_usb_clk_driver = {
.probe = sun9i_a80_usb_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
View file @ 7552d1b9
......@@ -1236,6 +1236,7 @@ static const struct of_device_id sun9i_a80_ccu_ids[] = {
{ .compatible = "allwinner,sun9i-a80-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_ccu_ids);
static struct platform_driver sun9i_a80_ccu_driver = {
.probe = sun9i_a80_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View file @ 7552d1b9
......@@ -565,6 +565,7 @@ static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
{ .compatible = "allwinner,suniv-f1c100s-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, suniv_f1c100s_ccu_ids);
static struct platform_driver suniv_f1c100s_ccu_driver = {
.probe = suniv_f1c100s_ccu_probe,
......
drivers/clk/sunxi-ng/ccu_nkm.c
View file @ 7552d1b9
......@@ -16,6 +16,20 @@ struct _ccu_nkm {
unsigned long m, min_m, max_m;
};
static bool ccu_nkm_is_valid_rate(struct ccu_common *common, unsigned long parent,
unsigned long n, unsigned long m)
{
struct ccu_nkm *nkm = container_of(common, struct ccu_nkm, common);
if (nkm->max_m_n_ratio && (m > nkm->max_m_n_ratio * n))
return false;
if (nkm->min_parent_m_ratio && (parent < nkm->min_parent_m_ratio * m))
return false;
return true;
}
static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
struct clk_hw *parent_hw,
unsigned long *parent, unsigned long rate,
......@@ -31,6 +45,10 @@ static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common
unsigned long tmp_rate, tmp_parent;
tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
if (!ccu_nkm_is_valid_rate(common, tmp_parent, _n, _m))
continue;
tmp_rate = tmp_parent * _n * _k / _m;
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
......@@ -64,6 +82,9 @@ static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
if (!ccu_nkm_is_valid_rate(common, parent, _n, _m))
continue;
unsigned long tmp_rate;
tmp_rate = parent * _n * _k / _m;
......
drivers/clk/sunxi-ng/ccu_nkm.h
View file @ 7552d1b9
......@@ -27,6 +27,8 @@ struct ccu_nkm {
struct ccu_mux_internal mux;
unsigned int fixed_post_div;
unsigned long max_m_n_ratio;
unsigned long min_parent_m_ratio;
struct ccu_common common;
};
......
include/dt-bindings/clock/r9a07g043-cpg.h
View file @ 7552d1b9
......@@ -16,15 +16,15 @@
#define R9A07G043_CLK_SD0 5
#define R9A07G043_CLK_SD1 6
#define R9A07G043_CLK_M0 7
#define R9A07G043_CLK_M2 8
#define R9A07G043_CLK_M3 9
#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */
#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */
#define R9A07G043_CLK_HP 10
#define R9A07G043_CLK_TSU 11
#define R9A07G043_CLK_ZT 12
#define R9A07G043_CLK_P0 13
#define R9A07G043_CLK_P1 14
#define R9A07G043_CLK_P2 15
#define R9A07G043_CLK_AT 16
#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */
#define R9A07G043_OSCCLK 17
#define R9A07G043_CLK_P0_DIV2 18
......@@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
/* Power domain IDs. */
#define R9A07G043_PD_ALWAYS_ON 0
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
#define R9A07G043_PD_DMAC 6
#define R9A07G043_PD_GTM0 7
#define R9A07G043_PD_GTM1 8
#define R9A07G043_PD_GTM2 9
#define R9A07G043_PD_MTU 10
#define R9A07G043_PD_POE3 11
#define R9A07G043_PD_WDT0 12
#define R9A07G043_PD_SPI 13
#define R9A07G043_PD_SDHI0 14
#define R9A07G043_PD_SDHI1 15
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
#define R9A07G043_PD_SSI0 19
#define R9A07G043_PD_SSI1 20
#define R9A07G043_PD_SSI2 21
#define R9A07G043_PD_SSI3 22
#define R9A07G043_PD_SRC 23
#define R9A07G043_PD_USB0 24
#define R9A07G043_PD_USB1 25
#define R9A07G043_PD_USB_PHY 26
#define R9A07G043_PD_ETHER0 27
#define R9A07G043_PD_ETHER1 28
#define R9A07G043_PD_I2C0 29
#define R9A07G043_PD_I2C1 30
#define R9A07G043_PD_I2C2 31
#define R9A07G043_PD_I2C3 32
#define R9A07G043_PD_SCIF0 33
#define R9A07G043_PD_SCIF1 34
#define R9A07G043_PD_SCIF2 35
#define R9A07G043_PD_SCIF3 36
#define R9A07G043_PD_SCIF4 37
#define R9A07G043_PD_SCI0 38
#define R9A07G043_PD_SCI1 39
#define R9A07G043_PD_IRDA 40
#define R9A07G043_PD_RSPI0 41
#define R9A07G043_PD_RSPI1 42
#define R9A07G043_PD_RSPI2 43
#define R9A07G043_PD_CANFD 44
#define R9A07G043_PD_ADC 45
#define R9A07G043_PD_TSU 46
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
include/dt-bindings/clock/r9a07g044-cpg.h
View file @ 7552d1b9
......@@ -217,4 +217,62 @@
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
/* Power domain IDs. */
#define R9A07G044_PD_ALWAYS_ON 0
#define R9A07G044_PD_GIC 1
#define R9A07G044_PD_IA55 2
#define R9A07G044_PD_MHU 3
#define R9A07G044_PD_CORESIGHT 4
#define R9A07G044_PD_SYC 5
#define R9A07G044_PD_DMAC 6
#define R9A07G044_PD_GTM0 7
#define R9A07G044_PD_GTM1 8
#define R9A07G044_PD_GTM2 9
#define R9A07G044_PD_MTU 10
#define R9A07G044_PD_POE3 11
#define R9A07G044_PD_GPT 12
#define R9A07G044_PD_POEGA 13
#define R9A07G044_PD_POEGB 14
#define R9A07G044_PD_POEGC 15
#define R9A07G044_PD_POEGD 16
#define R9A07G044_PD_WDT0 17
#define R9A07G044_PD_WDT1 18
#define R9A07G044_PD_SPI 19
#define R9A07G044_PD_SDHI0 20
#define R9A07G044_PD_SDHI1 21
#define R9A07G044_PD_3DGE 22
#define R9A07G044_PD_ISU 23
#define R9A07G044_PD_VCPL4 24
#define R9A07G044_PD_CRU 25
#define R9A07G044_PD_MIPI_DSI 26
#define R9A07G044_PD_LCDC 27
#define R9A07G044_PD_SSI0 28
#define R9A07G044_PD_SSI1 29
#define R9A07G044_PD_SSI2 30
#define R9A07G044_PD_SSI3 31
#define R9A07G044_PD_SRC 32
#define R9A07G044_PD_USB0 33
#define R9A07G044_PD_USB1 34
#define R9A07G044_PD_USB_PHY 35
#define R9A07G044_PD_ETHER0 36
#define R9A07G044_PD_ETHER1 37
#define R9A07G044_PD_I2C0 38
#define R9A07G044_PD_I2C1 39
#define R9A07G044_PD_I2C2 40
#define R9A07G044_PD_I2C3 41
#define R9A07G044_PD_SCIF0 42
#define R9A07G044_PD_SCIF1 43
#define R9A07G044_PD_SCIF2 44
#define R9A07G044_PD_SCIF3 45
#define R9A07G044_PD_SCIF4 46
#define R9A07G044_PD_SCI0 47
#define R9A07G044_PD_SCI1 48
#define R9A07G044_PD_IRDA 49
#define R9A07G044_PD_RSPI0 50
#define R9A07G044_PD_RSPI1 51
#define R9A07G044_PD_RSPI2 52
#define R9A07G044_PD_CANFD 53
#define R9A07G044_PD_ADC 54
#define R9A07G044_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
include/dt-bindings/clock/r9a07g054-cpg.h
View file @ 7552d1b9
......@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
/* Power domain IDs. */
#define R9A07G054_PD_ALWAYS_ON 0
#define R9A07G054_PD_GIC 1
#define R9A07G054_PD_IA55 2
#define R9A07G054_PD_MHU 3
#define R9A07G054_PD_CORESIGHT 4
#define R9A07G054_PD_SYC 5
#define R9A07G054_PD_DMAC 6
#define R9A07G054_PD_GTM0 7
#define R9A07G054_PD_GTM1 8
#define R9A07G054_PD_GTM2 9
#define R9A07G054_PD_MTU 10
#define R9A07G054_PD_POE3 11
#define R9A07G054_PD_GPT 12
#define R9A07G054_PD_POEGA 13
#define R9A07G054_PD_POEGB 14
#define R9A07G054_PD_POEGC 15
#define R9A07G054_PD_POEGD 16
#define R9A07G054_PD_WDT0 17
#define R9A07G054_PD_WDT1 18
#define R9A07G054_PD_SPI 19
#define R9A07G054_PD_SDHI0 20
#define R9A07G054_PD_SDHI1 21
#define R9A07G054_PD_3DGE 22
#define R9A07G054_PD_ISU 23
#define R9A07G054_PD_VCPL4 24
#define R9A07G054_PD_CRU 25
#define R9A07G054_PD_MIPI_DSI 26
#define R9A07G054_PD_LCDC 27
#define R9A07G054_PD_SSI0 28
#define R9A07G054_PD_SSI1 29
#define R9A07G054_PD_SSI2 30
#define R9A07G054_PD_SSI3 31
#define R9A07G054_PD_SRC 32
#define R9A07G054_PD_USB0 33
#define R9A07G054_PD_USB1 34
#define R9A07G054_PD_USB_PHY 35
#define R9A07G054_PD_ETHER0 36
#define R9A07G054_PD_ETHER1 37
#define R9A07G054_PD_I2C0 38
#define R9A07G054_PD_I2C1 39
#define R9A07G054_PD_I2C2 40
#define R9A07G054_PD_I2C3 41
#define R9A07G054_PD_SCIF0 42
#define R9A07G054_PD_SCIF1 43
#define R9A07G054_PD_SCIF2 44
#define R9A07G054_PD_SCIF3 45
#define R9A07G054_PD_SCIF4 46
#define R9A07G054_PD_SCI0 47
#define R9A07G054_PD_SCI1 48
#define R9A07G054_PD_IRDA 49
#define R9A07G054_PD_RSPI0 50
#define R9A07G054_PD_RSPI1 51
#define R9A07G054_PD_RSPI2 52
#define R9A07G054_PD_CANFD 53
#define R9A07G054_PD_ADC 54
#define R9A07G054_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
include/dt-bindings/clock/r9a08g045-cpg.h
View file @ 7552d1b9
......@@ -239,4 +239,74 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
/* Power domain IDs. */
#define R9A08G045_PD_ALWAYS_ON 0
#define R9A08G045_PD_GIC 1
#define R9A08G045_PD_IA55 2
#define R9A08G045_PD_MHU 3
#define R9A08G045_PD_CORESIGHT 4
#define R9A08G045_PD_SYC 5
#define R9A08G045_PD_DMAC 6
#define R9A08G045_PD_GTM0 7
#define R9A08G045_PD_GTM1 8
#define R9A08G045_PD_GTM2 9
#define R9A08G045_PD_GTM3 10
#define R9A08G045_PD_GTM4 11
#define R9A08G045_PD_GTM5 12
#define R9A08G045_PD_GTM6 13
#define R9A08G045_PD_GTM7 14
#define R9A08G045_PD_MTU 15
#define R9A08G045_PD_POE3 16
#define R9A08G045_PD_GPT 17
#define R9A08G045_PD_POEGA 18
#define R9A08G045_PD_POEGB 19
#define R9A08G045_PD_POEGC 20
#define R9A08G045_PD_POEGD 21
#define R9A08G045_PD_WDT0 22
#define R9A08G045_PD_XSPI 23
#define R9A08G045_PD_SDHI0 24
#define R9A08G045_PD_SDHI1 25
#define R9A08G045_PD_SDHI2 26
#define R9A08G045_PD_SSI0 27
#define R9A08G045_PD_SSI1 28
#define R9A08G045_PD_SSI2 29
#define R9A08G045_PD_SSI3 30
#define R9A08G045_PD_SRC 31
#define R9A08G045_PD_USB0 32
#define R9A08G045_PD_USB1 33
#define R9A08G045_PD_USB_PHY 34
#define R9A08G045_PD_ETHER0 35
#define R9A08G045_PD_ETHER1 36
#define R9A08G045_PD_I2C0 37
#define R9A08G045_PD_I2C1 38
#define R9A08G045_PD_I2C2 39
#define R9A08G045_PD_I2C3 40
#define R9A08G045_PD_SCIF0 41
#define R9A08G045_PD_SCIF1 42
#define R9A08G045_PD_SCIF2 43
#define R9A08G045_PD_SCIF3 44
#define R9A08G045_PD_SCIF4 45
#define R9A08G045_PD_SCIF5 46
#define R9A08G045_PD_SCI0 47
#define R9A08G045_PD_SCI1 48
#define R9A08G045_PD_IRDA 49
#define R9A08G045_PD_RSPI0 50
#define R9A08G045_PD_RSPI1 51
#define R9A08G045_PD_RSPI2 52
#define R9A08G045_PD_RSPI3 53
#define R9A08G045_PD_RSPI4 54
#define R9A08G045_PD_CANFD 55
#define R9A08G045_PD_ADC 56
#define R9A08G045_PD_TSU 57
#define R9A08G045_PD_OCTA 58
#define R9A08G045_PD_PDM 59
#define R9A08G045_PD_PCI 60
#define R9A08G045_PD_SPDIF 61
#define R9A08G045_PD_I3C 62
#define R9A08G045_PD_VBAT 63
#define R9A08G045_PD_DDR 64
#define R9A08G045_PD_TZCDDR 65
#define R9A08G045_PD_OTFDE_DDR 66
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
include/dt-bindings/reset/st,stm32mp25-rcc.h
View file @ 7552d1b9
......@@ -69,7 +69,7 @@
#define ADC3_R 59
#define ETH1_R 60
#define ETH2_R 61
#define USB2_R 62
#define USBH_R 62
#define USB2PHY1_R 63
#define USB2PHY2_R 64
#define USB3DR_R 65
......
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