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Commit 7552d1b9 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-stm', 'clk-renesas', 'clk-scmi' and 'clk-allwinner' into clk-next 

 - STM32MP257 SoC clk driver
 - Allocate clk_ops dynamically for SCMI clk driver

* clk-stm:
  dt-bindings: clocks: stm32mp25: add access-controllers description
  clk: stm32: introduce clocks for STM32MP257 platform
  dt-bindings: clocks: stm32mp25: add description of all parents
  clk: stm32mp13: use platform device APIs

* clk-renesas:
  clk: renesas: r9a08g045: Add support for power domains
  clk: renesas: rzg2l: Extend power domain support
  dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
  dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
  dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
  clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
  clk: renesas: r8a7740: Remove unused div4_clk.flags field
  clk: renesas: r9a07g043: Add clock and reset entry for PLIC
  clk: renesas: r8a779h0: Add INTC-EX clock
  clk: renesas: r8a779h0: Add MSIOF clocks
  clk: renesas: r8a779a0: Fix CANFD parent clock
  clk: rs9: fix wrong default value for clock amplitude
  clk: renesas: r8a779h0: Add timer clocks
  clk: renesas: r8a779h0: Add SCIF clocks
  clk: renesas: r9a07g044: Mark resets array as const
  clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
  clk: renesas: r8a779h0: Add thermal clock
  dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks

* clk-scmi:
  clk: scmi: Add support for get/set duty_cycle operations
  clk: scmi: Add support for re-parenting restricted clocks
  clk: scmi: Add support for rate change restricted clocks
  clk: scmi: Add support for state control restricted clocks
  clk: scmi: Allocate CLK operations dynamically

* clk-allwinner:
  clk: sunxi-ng: fix module autoloading
  clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
  clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
parents 5aabfd91 12b52b83 8beff788 87af9481 19149b31
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Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View file @ 7552d1b9
......@@ -57,7 +57,8 @@ properties:
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
const: 0
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
be used to reference individual CPG power domains.
'#reset-cells':
description:
......@@ -76,6 +77,21 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-cpg
then:
properties:
'#power-domain-cells':
const: 1
else:
properties:
'#power-domain-cells':
const: 0
examples:
- |
cpg: clock-controller@11010000 {
......
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
View file @ 7552d1b9
......@@ -38,14 +38,85 @@ properties:
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
- description: CK_SCMI_ICN_VID Video interconnect bus clock
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
- description: CK_SCMI_FLEXGEN_15 flexgen clock 15
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
- description: CK_SCMI_FLEXGEN_28 flexgen clock 28
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
- description: CK_SCMI_FLEXGEN_32 flexgen clock 32
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
- description: CK_SCMI_FLEXGEN_34 flexgen clock 34
- description: CK_SCMI_FLEXGEN_35 flexgen clock 35
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
- description: CK_SCMI_FLEXGEN_49 flexgen clock 49
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
- description: CK_SCMI_FLEXGEN_59 flexgen clock 59
- description: CK_SCMI_FLEXGEN_60 flexgen clock 60
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
- description: CK_SCMI_PLL3 PLL3 clock
- description: clk_dsi_txbyte DSI byte clock
clock-names:
items:
- const: hse
- const: hsi
- const: msi
- const: lse
- const: lsi
access-controllers:
minItems: 1
maxItems: 2
required:
- compatible
......@@ -53,7 +124,6 @@ required:
- '#clock-cells'
- '#reset-cells'
- clocks
- clock-names
additionalProperties: false
......@@ -66,11 +136,85 @@ examples:
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "msi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_ICN_VID>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_15>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_28>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_32>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_34>,
<&scmi_clk CK_SCMI_FLEXGEN_35>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_49>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_59>,
<&scmi_clk CK_SCMI_FLEXGEN_60>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
};
...
drivers/clk/clk-renesas-pcie.c
View file @ 7552d1b9
......@@ -25,10 +25,12 @@
#define RS9_REG_SS_AMP_0V7 0x1
#define RS9_REG_SS_AMP_0V8 0x2
#define RS9_REG_SS_AMP_0V9 0x3
#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
#define RS9_REG_SS_AMP_MASK 0x3
#define RS9_REG_SS_SSC_100 0
#define RS9_REG_SS_SSC_M025 (1 << 3)
#define RS9_REG_SS_SSC_M050 (3 << 3)
#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
#define RS9_REG_SS_SSC_MASK (3 << 3)
#define RS9_REG_SS_SSC_LOCK BIT(5)
#define RS9_REG_SR 0x2
......@@ -205,8 +207,8 @@ static int rs9_get_common_config(struct rs9_driver_data *rs9)
int ret;
/* Set defaults */
rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
rs9->pll_ssc = RS9_REG_SS_SSC_100;
rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
/* Output clock amplitude */
ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
......@@ -247,13 +249,13 @@ static void rs9_update_config(struct rs9_driver_data *rs9)
int i;
/* If amplitude is non-default, update it. */
if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
rs9->pll_amplitude);
}
/* If SSC is non-default, update it. */
if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
rs9->pll_ssc);
}
......
drivers/clk/clk-scmi.c
View file @ 7552d1b9
......@@ -2,9 +2,10 @@
/*
* System Control and Power Interface (SCMI) Protocol based clock driver
*
* Copyright (C) 2018-2022 ARM Ltd.
* Copyright (C) 2018-2024 ARM Ltd.
*/
#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
......@@ -16,6 +17,17 @@
#define NOT_ATOMIC false
#define ATOMIC true
enum scmi_clk_feats {
SCMI_CLK_ATOMIC_SUPPORTED,
SCMI_CLK_STATE_CTRL_SUPPORTED,
SCMI_CLK_RATE_CTRL_SUPPORTED,
SCMI_CLK_PARENT_CTRL_SUPPORTED,
SCMI_CLK_DUTY_CYCLE_SUPPORTED,
SCMI_CLK_FEATS_COUNT
};
#define SCMI_MAX_CLK_OPS BIT(SCMI_CLK_FEATS_COUNT)
static const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
struct scmi_clk {
......@@ -158,41 +170,44 @@ static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)
return !!enabled;
}
/*
* We can provide enable/disable/is_enabled atomic callbacks only if the
* underlying SCMI transport for an SCMI instance is configured to handle
* SCMI commands in an atomic manner.
*
* When no SCMI atomic transport support is available we instead provide only
* the prepare/unprepare API, as allowed by the clock framework when atomic
* calls are not available.
*
* Two distinct sets of clk_ops are provided since we could have multiple SCMI
* instances with different underlying transport quality, so they cannot be
* shared.
*/
static const struct clk_ops scmi_clk_ops = {
.recalc_rate = scmi_clk_recalc_rate,
.round_rate = scmi_clk_round_rate,
.set_rate = scmi_clk_set_rate,
.prepare = scmi_clk_enable,
.unprepare = scmi_clk_disable,
.set_parent = scmi_clk_set_parent,
.get_parent = scmi_clk_get_parent,
.determine_rate = scmi_clk_determine_rate,
};
static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
int ret;
u32 val;
struct scmi_clk *clk = to_scmi_clk(hw);
static const struct clk_ops scmi_atomic_clk_ops = {
.recalc_rate = scmi_clk_recalc_rate,
.round_rate = scmi_clk_round_rate,
.set_rate = scmi_clk_set_rate,
.enable = scmi_clk_atomic_enable,
.disable = scmi_clk_atomic_disable,
.is_enabled = scmi_clk_atomic_is_enabled,
.set_parent = scmi_clk_set_parent,
.get_parent = scmi_clk_get_parent,
.determine_rate = scmi_clk_determine_rate,
};
ret = scmi_proto_clk_ops->config_oem_get(clk->ph, clk->id,
SCMI_CLOCK_CFG_DUTY_CYCLE,
&val, NULL, false);
if (!ret) {
duty->num = val;
duty->den = 100;
} else {
dev_warn(clk->dev,
"Failed to get duty cycle for clock ID %d\n", clk->id);
}
return ret;
}
static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
int ret;
u32 val;
struct scmi_clk *clk = to_scmi_clk(hw);
/* SCMI OEM Duty Cycle is expressed as a percentage */
val = (duty->num * 100) / duty->den;
ret = scmi_proto_clk_ops->config_oem_set(clk->ph, clk->id,
SCMI_CLOCK_CFG_DUTY_CYCLE,
val, false);
if (ret)
dev_warn(clk->dev,
"Failed to set duty cycle(%u/%u) for clock ID %d\n",
duty->num, duty->den, clk->id);
return ret;
}
static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
const struct clk_ops *scmi_ops)
......@@ -230,17 +245,153 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
return ret;
}
/**
* scmi_clk_ops_alloc() - Alloc and configure clock operations
* @dev: A device reference for devres
* @feats_key: A bitmap representing the desired clk_ops capabilities
*
* Allocate and configure a proper set of clock operations depending on the
* specifically required SCMI clock features.
*
* Return: A pointer to the allocated and configured clk_ops on success,
* or NULL on allocation failure.
*/
static const struct clk_ops *
scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
{
struct clk_ops *ops;
ops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);
if (!ops)
return NULL;
/*
* We can provide enable/disable/is_enabled atomic callbacks only if the
* underlying SCMI transport for an SCMI instance is configured to
* handle SCMI commands in an atomic manner.
*
* When no SCMI atomic transport support is available we instead provide
* only the prepare/unprepare API, as allowed by the clock framework
* when atomic calls are not available.
*/
if (feats_key & BIT(SCMI_CLK_STATE_CTRL_SUPPORTED)) {
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
ops->enable = scmi_clk_atomic_enable;
ops->disable = scmi_clk_atomic_disable;
} else {
ops->prepare = scmi_clk_enable;
ops->unprepare = scmi_clk_disable;
}
}
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))
ops->is_enabled = scmi_clk_atomic_is_enabled;
/* Rate ops */
ops->recalc_rate = scmi_clk_recalc_rate;
ops->round_rate = scmi_clk_round_rate;
ops->determine_rate = scmi_clk_determine_rate;
if (feats_key & BIT(SCMI_CLK_RATE_CTRL_SUPPORTED))
ops->set_rate = scmi_clk_set_rate;
/* Parent ops */
ops->get_parent = scmi_clk_get_parent;
if (feats_key & BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED))
ops->set_parent = scmi_clk_set_parent;
/* Duty cycle */
if (feats_key & BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED)) {
ops->get_duty_cycle = scmi_clk_get_duty_cycle;
ops->set_duty_cycle = scmi_clk_set_duty_cycle;
}
return ops;
}
/**
* scmi_clk_ops_select() - Select a proper set of clock operations
* @sclk: A reference to an SCMI clock descriptor
* @atomic_capable: A flag to indicate if atomic mode is supported by the
* transport
* @atomic_threshold_us: Platform atomic threshold value in microseconds:
* clk_ops are atomic when clock enable latency is less
* than this threshold
* @clk_ops_db: A reference to the array used as a database to store all the
* created clock operations combinations.
* @db_size: Maximum number of entries held by @clk_ops_db
*
* After having built a bitmap descriptor to represent the set of features
* needed by this SCMI clock, at first use it to lookup into the set of
* previously allocated clk_ops to check if a suitable combination of clock
* operations was already created; when no match is found allocate a brand new
* set of clk_ops satisfying the required combination of features and save it
* for future references.
*
* In this way only one set of clk_ops is ever created for each different
* combination that is effectively needed by a driver instance.
*
* Return: A pointer to the allocated and configured clk_ops on success, or
* NULL otherwise.
*/
static const struct clk_ops *
scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
unsigned int atomic_threshold_us,
const struct clk_ops **clk_ops_db, size_t db_size)
{
const struct scmi_clock_info *ci = sclk->info;
unsigned int feats_key = 0;
const struct clk_ops *ops;
/*
* Note that when transport is atomic but SCMI protocol did not
* specify (or support) an enable_latency associated with a
* clock, we default to use atomic operations mode.
*/
if (atomic_capable && ci->enable_latency <= atomic_threshold_us)
feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
if (!ci->state_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_STATE_CTRL_SUPPORTED);
if (!ci->rate_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_RATE_CTRL_SUPPORTED);
if (!ci->parent_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED);
if (ci->extended_config)
feats_key |= BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED);
if (WARN_ON(feats_key >= db_size))
return NULL;
/* Lookup previously allocated ops */
ops = clk_ops_db[feats_key];
if (ops)
return ops;
/* Did not find a pre-allocated clock_ops */
ops = scmi_clk_ops_alloc(sclk->dev, feats_key);
if (!ops)
return NULL;
/* Store new ops combinations */
clk_ops_db[feats_key] = ops;
return ops;
}
static int scmi_clocks_probe(struct scmi_device *sdev)
{
int idx, count, err;
unsigned int atomic_threshold;
bool is_atomic;
unsigned int atomic_threshold_us;
bool transport_is_atomic;
struct clk_hw **hws;
struct clk_hw_onecell_data *clk_data;
struct device *dev = &sdev->dev;
struct device_node *np = dev->of_node;
const struct scmi_handle *handle = sdev->handle;
struct scmi_protocol_handle *ph;
const struct clk_ops *scmi_clk_ops_db[SCMI_MAX_CLK_OPS] = {};
if (!handle)
return -ENODEV;
......@@ -264,7 +415,8 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
clk_data->num = count;
hws = clk_data->hws;
is_atomic = handle->is_transport_atomic(handle, &atomic_threshold);
transport_is_atomic = handle->is_transport_atomic(handle,
&atomic_threshold_us);
for (idx = 0; idx < count; idx++) {
struct scmi_clk *sclk;
......@@ -286,15 +438,17 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
sclk->dev = dev;
/*
* Note that when transport is atomic but SCMI protocol did not
* specify (or support) an enable_latency associated with a
* clock, we default to use atomic operations mode.
* Note that the scmi_clk_ops_db is on the stack, not global,
* because it cannot be shared between mulitple probe-sequences
* to avoid sharing the devm_ allocated clk_ops between multiple
* SCMI clk driver instances.
*/
if (is_atomic &&
sclk->info->enable_latency <= atomic_threshold)
scmi_ops = &scmi_atomic_clk_ops;
else
scmi_ops = &scmi_clk_ops;
scmi_ops = scmi_clk_ops_select(sclk, transport_is_atomic,
atomic_threshold_us,
scmi_clk_ops_db,
ARRAY_SIZE(scmi_clk_ops_db));
if (!scmi_ops)
return -ENOMEM;
/* Initialize clock parent data. */
if (sclk->info->num_parents > 0) {
......@@ -318,8 +472,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
} else {
dev_dbg(dev, "Registered clock:%s%s\n",
sclk->info->name,
scmi_ops == &scmi_atomic_clk_ops ?
" (atomic ops)" : "");
scmi_ops->enable ? " (atomic ops)" : "");
hws[idx] = &sclk->hw;
}
}
......
drivers/clk/renesas/clk-r8a73a4.c
View file @ 7552d1b9
......@@ -30,8 +30,6 @@ struct r8a73a4_cpg {
#define CPG_PLL2HCR 0xe4
#define CPG_PLL2SCR 0xf4
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
unsigned int reg;
......
drivers/clk/renesas/clk-r8a7740.c
View file @ 7552d1b9
......@@ -26,28 +26,25 @@ struct r8a7740_cpg {
#define CPG_USBCKCR 0x8c
#define CPG_FRQCRC 0xe0
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
unsigned int reg;
unsigned int shift;
int flags;
};
static struct div4_clk div4_clks[] = {
{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
{ "hp", CPG_FRQCRB, 4, 0 },
{ "hpp", CPG_FRQCRC, 20, 0 },
{ "usbp", CPG_FRQCRC, 16, 0 },
{ "s", CPG_FRQCRC, 12, 0 },
{ "zb", CPG_FRQCRC, 8, 0 },
{ "m3", CPG_FRQCRC, 4, 0 },
{ "cp", CPG_FRQCRC, 0, 0 },
{ NULL, 0, 0, 0 },
{ "i", CPG_FRQCRA, 20 },
{ "zg", CPG_FRQCRA, 16 },
{ "b", CPG_FRQCRA, 8 },
{ "m1", CPG_FRQCRA, 4 },
{ "hp", CPG_FRQCRB, 4 },
{ "hpp", CPG_FRQCRC, 20 },
{ "usbp", CPG_FRQCRC, 16 },
{ "s", CPG_FRQCRC, 12 },
{ "zb", CPG_FRQCRC, 8 },
{ "m3", CPG_FRQCRC, 4 },
{ "cp", CPG_FRQCRC, 0 },
{ NULL, 0, 0 },
};
static const struct clk_div_table div4_div_table[] = {
......
drivers/clk/renesas/clk-sh73a0.c
View file @ 7552d1b9
......@@ -34,8 +34,6 @@ struct sh73a0_cpg {
#define CPG_DSI0PHYCR 0x6c
#define CPG_DSI1PHYCR 0x70
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
const char *parent;
......
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View file @ 7552d1b9
......@@ -139,7 +139,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
......
drivers/clk/renesas/r8a779h0-cpg-mssr.c
View file @ 7552d1b9
......@@ -184,14 +184,35 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
};
/*
......
drivers/clk/renesas/r9a07g043-cpg.c
View file @ 7552d1b9
......@@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
#endif
};
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
#ifdef CONFIG_ARM64
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0x514, 0),
......@@ -280,9 +280,13 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x5a8, 1),
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0x5ac, 0),
#ifdef CONFIG_RISCV
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
0x608, 0),
#endif
};
static struct rzg2l_reset r9a07g043_resets[] = {
static const struct rzg2l_reset r9a07g043_resets[] = {
#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
......@@ -338,6 +342,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
#ifdef CONFIG_RISCV
DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
#endif
};
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
......@@ -347,6 +355,7 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
#endif
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
};
......
drivers/clk/renesas/r9a07g044-cpg.c
View file @ 7552d1b9
......@@ -368,7 +368,7 @@ static const struct {
#endif
};
static struct rzg2l_reset r9a07g044_resets[] = {
static const struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
......
drivers/clk/renesas/r9a08g045-cpg.c
View file @ 7552d1b9
......@@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
/* Keep always-on domain on the first position for proper domains registration. */
DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
DEF_REG_CONF(0, 0),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("gic", R9A08G045_PD_GIC,
DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("ia55", R9A08G045_PD_IA55,
DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("dmac", R9A08G045_PD_DMAC,
DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
RZG2L_PD_F_ALWAYS_ON),
DEF_PD("wdt0", R9A08G045_PD_WDT0,
DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
RZG2L_PD_F_NONE),
DEF_PD("eth0", R9A08G045_PD_ETHER0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
RZG2L_PD_F_NONE),
DEF_PD("eth1", R9A08G045_PD_ETHER1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
RZG2L_PD_F_NONE),
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
};
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
......@@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
/* Power domains */
.pm_domains = r9a08g045_pm_domains,
.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
.has_clk_mon_regs = true,
};
drivers/clk/renesas/rzg2l-cpg.c
View file @ 7552d1b9
......@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
* @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
......@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
struct generic_pm_domain genpd;
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
......@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
return true;
}
/**
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
* @onecell_data: cell data
* @domains: generic PM domains
*/
struct rzg2l_cpg_pm_domains {
struct genpd_onecell_data onecell_data;
struct generic_pm_domain *domains[];
};
/**
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
* @genpd: generic PM domain
* @priv: pointer to CPG private data structure
* @conf: CPG PM domain configuration info
* @id: RZ/G2L power domain ID
*/
struct rzg2l_cpg_pd {
struct generic_pm_domain genpd;
struct rzg2l_cpg_priv *priv;
struct rzg2l_cpg_pm_domain_conf conf;
u16 id;
};
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_priv *priv = pd->priv;
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
......@@ -1617,31 +1639,180 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
}
static void rzg2l_cpg_genpd_remove(void *data)
{
struct genpd_onecell_data *celldata = data;
for (unsigned int i = 0; i < celldata->num_domains; i++)
pm_genpd_remove(celldata->domains[i]);
}
static void rzg2l_cpg_genpd_remove_simple(void *data)
{
pm_genpd_remove(data);
}
static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask << 16, priv->base + mstop.off);
return 0;
}
static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
return 0;
}
static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
{
struct dev_power_governor *governor;
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
if (always_on) {
pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
governor = &pm_domain_always_on_gov;
} else {
pd->genpd.power_on = rzg2l_cpg_power_on;
pd->genpd.power_off = rzg2l_cpg_power_off;
governor = &simple_qos_governor;
}
return pm_genpd_init(&pd->genpd, governor, !always_on);
}
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd = &priv->genpd;
struct rzg2l_cpg_pd *pd;
int ret;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = np->name;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd, true);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, &pd->genpd);
}
static struct generic_pm_domain *
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
{
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
struct genpd_onecell_data *genpd = data;
if (spec->args_count != 1)
return ERR_PTR(-EINVAL);
for (unsigned int i = 0; i < genpd->num_domains; i++) {
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
genpd);
if (pd->id == spec->args[0]) {
domain = &pd->genpd;
break;
}
}
return domain;
}
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
{
const struct rzg2l_cpg_info *info = priv->info;
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct rzg2l_cpg_pm_domains *domains;
struct generic_pm_domain *parent;
u32 ncells;
int ret;
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
if (ret)
return ret;
/* For backward compatibility. */
if (!ncells)
return rzg2l_cpg_add_clk_domain(priv);
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
GFP_KERNEL);
if (!domains)
return -ENOMEM;
domains->onecell_data.domains = domains->domains;
domains->onecell_data.num_domains = info->num_pm_domains;
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
struct rzg2l_cpg_pd *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = info->pm_domains[i].name;
pd->conf = info->pm_domains[i].conf;
pd->id = info->pm_domains[i].id;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd, always_on);
if (ret)
return ret;
if (always_on) {
ret = rzg2l_cpg_power_on(&pd->genpd);
if (ret)
return ret;
}
domains->domains[i] = &pd->genpd;
/* Parent should be on the very first entry of info->pm_domains[]. */
if (!i) {
parent = &pd->genpd;
continue;
}
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
if (ret)
return ret;
}
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, genpd);
return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
......@@ -1697,7 +1868,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
error = rzg2l_cpg_add_clk_domain(priv);
error = rzg2l_cpg_add_pm_domains(priv);
if (error)
return error;
......
drivers/clk/renesas/rzg2l-cpg.h
View file @ 7552d1b9
......@@ -27,6 +27,18 @@
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
#define CPG_BUS_ACPU_MSTOP (0xB60)
#define CPG_BUS_MCPU1_MSTOP (0xB64)
#define CPG_BUS_MCPU2_MSTOP (0xB68)
#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
#define CPG_BUS_REG0_MSTOP (0xB7C)
#define CPG_BUS_REG1_MSTOP (0xB80)
#define CPG_BUS_TZCDDR_MSTOP (0xB84)
#define CPG_MHU_MSTOP (0xB88)
#define CPG_BUS_MCPU3_MSTOP (0xB90)
#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
......@@ -234,6 +246,55 @@ struct rzg2l_reset {
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
/**
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
* @off: register offset
* @mask: register mask
*/
struct rzg2l_cpg_reg_conf {
u16 off;
u16 mask;
};
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
/**
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
* @mstop: MSTOP register configuration
*/
struct rzg2l_cpg_pm_domain_conf {
struct rzg2l_cpg_reg_conf mstop;
};
/**
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
* @name: PM domain name
* @conf: PM domain configuration
* @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
* @id: PM domain ID (similar to the ones defined in
* include/dt-bindings/clock/<soc-id>-cpg.h)
*/
struct rzg2l_cpg_pm_domain_init_data {
const char * const name;
struct rzg2l_cpg_pm_domain_conf conf;
u32 flags;
u16 id;
};
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
{ \
.name = (_name), \
.id = (_id), \
.conf = { \
.mstop = (_mstop_conf), \
}, \
.flags = (_flags), \
}
/* Power domain flags. */
#define RZG2L_PD_F_ALWAYS_ON BIT(0)
#define RZG2L_PD_F_NONE (0)
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
......@@ -252,6 +313,8 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
* @pm_domains: PM domains init data array
* @num_pm_domains: Number of PM domains
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
......@@ -278,6 +341,10 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
/* Power domain. */
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
unsigned int num_pm_domains;
bool has_clk_mon_regs;
};
......
drivers/clk/stm32/Kconfig
View file @ 7552d1b9
......@@ -25,5 +25,12 @@ config COMMON_CLK_STM32MP157
help
Support for stm32mp15x SoC family clocks.
config COMMON_CLK_STM32MP257
bool "Clock driver for stm32mp25x clocks"
depends on ARM64 || COMPILE_TEST
default y
help
Support for stm32mp25x SoC family clocks.
endif
drivers/clk/stm32/Makefile
View file @ 7552d1b9
obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
drivers/clk/stm32/clk-stm32-core.c
View file @ 7552d1b9
......@@ -25,7 +25,6 @@ static int stm32_rcc_clock_init(struct device *dev,
{
const struct stm32_rcc_match_data *data = match->data;
struct clk_hw_onecell_data *clk_data = data->hw_clks;
struct device_node *np = dev_of_node(dev);
struct clk_hw **hws;
int n, max_binding;
......@@ -64,7 +63,7 @@ static int stm32_rcc_clock_init(struct device *dev,
hws[cfg_clock->id] = hw;
}
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
}
int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
......@@ -638,7 +637,7 @@ struct clk_hw *clk_stm32_mux_register(struct device *dev,
mux->lock = lock;
mux->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -659,7 +658,7 @@ struct clk_hw *clk_stm32_gate_register(struct device *dev,
gate->lock = lock;
gate->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -680,7 +679,7 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
div->lock = lock;
div->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......@@ -701,7 +700,7 @@ struct clk_hw *clk_stm32_composite_register(struct device *dev,
composite->lock = lock;
composite->clock_data = data->clock_data;
err = clk_hw_register(dev, hw);
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
......
drivers/clk/stm32/clk-stm32mp13.c
View file @ 7552d1b9
......@@ -1536,77 +1536,16 @@ static const struct of_device_id stm32mp13_match_data[] = {
};
MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
static int stm32mp1_rcc_init(struct device *dev)
{
void __iomem *rcc_base;
int ret = -ENOMEM;
rcc_base = of_iomap(dev_of_node(dev), 0);
if (!rcc_base) {
dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
goto out;
}
ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
out:
if (ret) {
if (rcc_base)
iounmap(rcc_base);
of_node_put(dev_of_node(dev));
}
return ret;
}
static int get_clock_deps(struct device *dev)
{
static const char * const clock_deps_name[] = {
"hsi", "hse", "csi", "lsi", "lse",
};
size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
struct clk **clk_deps;
int i;
clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
if (!clk_deps)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
clock_deps_name[i]);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
return PTR_ERR(clk);
} else {
/* Device gets a reference count on the clock */
clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
clk_put(clk);
}
}
return 0;
}
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret = get_clock_deps(dev);
void __iomem *base;
if (!ret)
ret = stm32mp1_rcc_init(dev);
return ret;
}
static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev_of_node(dev);
base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base)))
return PTR_ERR(base);
for_each_available_child_of_node(np, child)
of_clk_del_provider(child);
return stm32_rcc_init(dev, stm32mp13_match_data, base);
}
static struct platform_driver stm32mp13_rcc_clocks_driver = {
......@@ -1615,7 +1554,6 @@ static struct platform_driver stm32mp13_rcc_clocks_driver = {
.of_match_table = stm32mp13_match_data,
},
.probe = stm32mp1_rcc_clocks_probe,
.remove_new = stm32mp1_rcc_clocks_remove,
};
static int __init stm32mp13_clocks_init(void)
......
drivers/clk/stm32/clk-stm32mp25.c 0 → 100644
View file @ 7552d1b9
This diff is collapsed.
drivers/clk/stm32/reset-stm32.c
View file @ 7552d1b9
......@@ -19,6 +19,7 @@ struct stm32_reset_data {
struct reset_controller_dev rcdev;
void __iomem *membase;
u32 clear_offset;
const struct stm32_reset_cfg **reset_lines;
};
static inline struct stm32_reset_data *
......@@ -27,22 +28,46 @@ to_stm32_reset_data(struct reset_controller_dev *rcdev)
return container_of(rcdev, struct stm32_reset_data, rcdev);
}
static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_controller_dev *rcdev,
unsigned long id,
struct stm32_reset_cfg *line)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
if (!data->reset_lines) {
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
line->offset = bank * reg_width;
line->bit_idx = offset;
line->set_clr = (data->clear_offset ? true : false);
return line;
}
return data->reset_lines[id];
}
static int stm32_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
struct stm32_reset_cfg line_reset;
const struct stm32_reset_cfg *ptr_line;
if (data->clear_offset) {
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
if (!ptr_line)
return -EPERM;
if (ptr_line->set_clr) {
void __iomem *addr;
addr = data->membase + (bank * reg_width);
addr = data->membase + ptr_line->offset;
if (!assert)
addr += data->clear_offset;
writel(BIT(offset), addr);
writel(BIT(ptr_line->bit_idx), addr);
} else {
unsigned long flags;
......@@ -50,14 +75,14 @@ static int stm32_reset_update(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
reg = readl(data->membase + (bank * reg_width));
reg = readl(data->membase + ptr_line->offset);
if (assert)
reg |= BIT(offset);
reg |= BIT(ptr_line->bit_idx);
else
reg &= ~BIT(offset);
reg &= ~BIT(ptr_line->bit_idx);
writel(reg, data->membase + (bank * reg_width));
writel(reg, data->membase + ptr_line->offset);
spin_unlock_irqrestore(&data->lock, flags);
}
......@@ -81,14 +106,17 @@ static int stm32_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
int reg_width = sizeof(u32);
int bank = id / (reg_width * BITS_PER_BYTE);
int offset = id % (reg_width * BITS_PER_BYTE);
struct stm32_reset_cfg line_reset;
const struct stm32_reset_cfg *ptr_line;
u32 reg;
reg = readl(data->membase + (bank * reg_width));
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
if (!ptr_line)
return -EPERM;
reg = readl(data->membase + ptr_line->offset);
return !!(reg & BIT(offset));
return !!(reg & BIT(ptr_line->bit_idx));
}
static const struct reset_control_ops stm32_reset_ops = {
......@@ -113,6 +141,7 @@ int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,
reset_data->rcdev.ops = &stm32_reset_ops;
reset_data->rcdev.of_node = dev_of_node(dev);
reset_data->rcdev.nr_resets = data->nr_lines;
reset_data->reset_lines = data->reset_lines;
reset_data->clear_offset = data->clear_offset;
return reset_controller_register(&reset_data->rcdev);
......
drivers/clk/stm32/reset-stm32.h
View file @ 7552d1b9
......@@ -4,8 +4,15 @@
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
struct stm32_reset_cfg {
u16 offset;
u8 bit_idx;
bool set_clr;
};
struct clk_stm32_reset_data {
const struct reset_control_ops *ops;
const struct stm32_reset_cfg **reset_lines;
unsigned int nr_lines;
u32 clear_offset;
};
......
drivers/clk/stm32/stm32mp25_rcc.h 0 → 100644
View file @ 7552d1b9
This diff is collapsed.
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
View file @ 7552d1b9
......@@ -125,6 +125,7 @@ static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun20i_d1_r_ccu_ids);
static struct platform_driver sun20i_d1_r_ccu_driver = {
.probe = sun20i_d1_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View file @ 7552d1b9
......@@ -1394,6 +1394,7 @@ static const struct of_device_id sun20i_d1_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun20i_d1_ccu_ids);
static struct platform_driver sun20i_d1_ccu_driver = {
.probe = sun20i_d1_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
View file @ 7552d1b9
......@@ -1481,6 +1481,7 @@ static const struct of_device_id sun4i_a10_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_a10_ccu_ids);
static struct platform_driver sun4i_a10_ccu_driver = {
.probe = sun4i_a10_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
View file @ 7552d1b9
......@@ -202,6 +202,7 @@ static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a100_r_ccu_ids);
static struct platform_driver sun50i_a100_r_ccu_driver = {
.probe = sun50i_a100_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
View file @ 7552d1b9
......@@ -1264,6 +1264,7 @@ static const struct of_device_id sun50i_a100_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a100_ccu_ids);
static struct platform_driver sun50i_a100_ccu_driver = {
.probe = sun50i_a100_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View file @ 7552d1b9
......@@ -171,11 +171,13 @@ static struct ccu_nkm pll_mipi_clk = {
* user manual, and by experiments the PLL doesn't work without
* these bits toggled.
*/
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.max_m_n_ratio = 3,
.min_parent_m_ratio = 24000000,
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
......@@ -978,6 +980,7 @@ static const struct of_device_id sun50i_a64_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a64-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_a64_ccu_ids);
static struct platform_driver sun50i_a64_ccu_driver = {
.probe = sun50i_a64_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View file @ 7552d1b9
......@@ -244,6 +244,7 @@ static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h6_r_ccu_ids);
static struct platform_driver sun50i_h6_r_ccu_driver = {
.probe = sun50i_h6_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
View file @ 7552d1b9
......@@ -1259,6 +1259,7 @@ static const struct of_device_id sun50i_h6_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h6-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h6_ccu_ids);
static struct platform_driver sun50i_h6_ccu_driver = {
.probe = sun50i_h6_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View file @ 7552d1b9
......@@ -1154,6 +1154,7 @@ static const struct of_device_id sun50i_h616_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h616-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun50i_h616_ccu_ids);
static struct platform_driver sun50i_h616_ccu_driver = {
.probe = sun50i_h616_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
View file @ 7552d1b9
......@@ -1271,6 +1271,7 @@ static const struct of_device_id sun6i_a31_ccu_ids[] = {
{ .compatible = "allwinner,sun6i-a31-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun6i_a31_ccu_ids);
static struct platform_driver sun6i_a31_ccu_driver = {
.probe = sun6i_a31_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
View file @ 7552d1b9
......@@ -336,6 +336,7 @@ static const struct of_device_id sun6i_rtc_ccu_match[] = {
},
{},
};
MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
{
......
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
View file @ 7552d1b9
......@@ -751,6 +751,7 @@ static const struct of_device_id sun8i_a23_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a23-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a23_ccu_ids);
static struct platform_driver sun8i_a23_ccu_driver = {
.probe = sun8i_a23_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
View file @ 7552d1b9
......@@ -823,6 +823,7 @@ static const struct of_device_id sun8i_a33_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a33-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a33_ccu_ids);
static struct platform_driver sun8i_a33_ccu_driver = {
.probe = sun8i_a33_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
View file @ 7552d1b9
......@@ -911,6 +911,7 @@ static const struct of_device_id sun8i_a83t_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_a83t_ccu_ids);
static struct platform_driver sun8i_a83t_ccu_driver = {
.probe = sun8i_a83t_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View file @ 7552d1b9
......@@ -337,6 +337,7 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids);
static struct platform_driver sunxi_de2_clk_driver = {
.probe = sunxi_de2_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View file @ 7552d1b9
......@@ -1082,6 +1082,7 @@ static const struct of_device_id sun8i_h3_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_h3_ccu_ids);
static struct platform_driver sun8i_h3_ccu_driver = {
.probe = sun8i_h3_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View file @ 7552d1b9
......@@ -262,6 +262,7 @@ static const struct of_device_id sun8i_r_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_r_ccu_ids);
static struct platform_driver sun8i_r_ccu_driver = {
.probe = sun8i_r_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View file @ 7552d1b9
......@@ -1363,6 +1363,7 @@ static const struct of_device_id sun8i_r40_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-r40-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_r40_ccu_ids);
static struct platform_driver sun8i_r40_ccu_driver = {
.probe = sun8i_r40_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View file @ 7552d1b9
......@@ -768,6 +768,7 @@ static const struct of_device_id sun8i_v3s_ccu_ids[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_v3s_ccu_ids);
static struct platform_driver sun8i_v3s_ccu_driver = {
.probe = sun8i_v3s_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View file @ 7552d1b9
......@@ -254,6 +254,7 @@ static const struct of_device_id sun9i_a80_de_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-de-clks" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_de_clk_ids);
static struct platform_driver sun9i_a80_de_clk_driver = {
.probe = sun9i_a80_de_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View file @ 7552d1b9
......@@ -127,6 +127,7 @@ static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-usb-clks" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_usb_clk_ids);
static struct platform_driver sun9i_a80_usb_clk_driver = {
.probe = sun9i_a80_usb_clk_probe,
......
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
View file @ 7552d1b9
......@@ -1236,6 +1236,7 @@ static const struct of_device_id sun9i_a80_ccu_ids[] = {
{ .compatible = "allwinner,sun9i-a80-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, sun9i_a80_ccu_ids);
static struct platform_driver sun9i_a80_ccu_driver = {
.probe = sun9i_a80_ccu_probe,
......
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View file @ 7552d1b9
......@@ -565,6 +565,7 @@ static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
{ .compatible = "allwinner,suniv-f1c100s-ccu" },
{ }
};
MODULE_DEVICE_TABLE(of, suniv_f1c100s_ccu_ids);
static struct platform_driver suniv_f1c100s_ccu_driver = {
.probe = suniv_f1c100s_ccu_probe,
......
drivers/clk/sunxi-ng/ccu_nkm.c
View file @ 7552d1b9
......@@ -16,6 +16,20 @@ struct _ccu_nkm {
unsigned long m, min_m, max_m;
};
static bool ccu_nkm_is_valid_rate(struct ccu_common *common, unsigned long parent,
unsigned long n, unsigned long m)
{
struct ccu_nkm *nkm = container_of(common, struct ccu_nkm, common);
if (nkm->max_m_n_ratio && (m > nkm->max_m_n_ratio * n))
return false;
if (nkm->min_parent_m_ratio && (parent < nkm->min_parent_m_ratio * m))
return false;
return true;
}
static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
struct clk_hw *parent_hw,
unsigned long *parent, unsigned long rate,
......@@ -31,6 +45,10 @@ static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common
unsigned long tmp_rate, tmp_parent;
tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
if (!ccu_nkm_is_valid_rate(common, tmp_parent, _n, _m))
continue;
tmp_rate = tmp_parent * _n * _k / _m;
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
......@@ -64,6 +82,9 @@ static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
if (!ccu_nkm_is_valid_rate(common, parent, _n, _m))
continue;
unsigned long tmp_rate;
tmp_rate = parent * _n * _k / _m;
......
drivers/clk/sunxi-ng/ccu_nkm.h
View file @ 7552d1b9
......@@ -27,6 +27,8 @@ struct ccu_nkm {
struct ccu_mux_internal mux;
unsigned int fixed_post_div;
unsigned long max_m_n_ratio;
unsigned long min_parent_m_ratio;
struct ccu_common common;
};
......
include/dt-bindings/clock/r9a07g043-cpg.h
View file @ 7552d1b9
......@@ -16,15 +16,15 @@
#define R9A07G043_CLK_SD0 5
#define R9A07G043_CLK_SD1 6
#define R9A07G043_CLK_M0 7
#define R9A07G043_CLK_M2 8
#define R9A07G043_CLK_M3 9
#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */
#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */
#define R9A07G043_CLK_HP 10
#define R9A07G043_CLK_TSU 11
#define R9A07G043_CLK_ZT 12
#define R9A07G043_CLK_P0 13
#define R9A07G043_CLK_P1 14
#define R9A07G043_CLK_P2 15
#define R9A07G043_CLK_AT 16
#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */
#define R9A07G043_OSCCLK 17
#define R9A07G043_CLK_P0_DIV2 18
......@@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
/* Power domain IDs. */
#define R9A07G043_PD_ALWAYS_ON 0
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
#define R9A07G043_PD_DMAC 6
#define R9A07G043_PD_GTM0 7
#define R9A07G043_PD_GTM1 8
#define R9A07G043_PD_GTM2 9
#define R9A07G043_PD_MTU 10
#define R9A07G043_PD_POE3 11
#define R9A07G043_PD_WDT0 12
#define R9A07G043_PD_SPI 13
#define R9A07G043_PD_SDHI0 14
#define R9A07G043_PD_SDHI1 15
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
#define R9A07G043_PD_SSI0 19
#define R9A07G043_PD_SSI1 20
#define R9A07G043_PD_SSI2 21
#define R9A07G043_PD_SSI3 22
#define R9A07G043_PD_SRC 23
#define R9A07G043_PD_USB0 24
#define R9A07G043_PD_USB1 25
#define R9A07G043_PD_USB_PHY 26
#define R9A07G043_PD_ETHER0 27
#define R9A07G043_PD_ETHER1 28
#define R9A07G043_PD_I2C0 29
#define R9A07G043_PD_I2C1 30
#define R9A07G043_PD_I2C2 31
#define R9A07G043_PD_I2C3 32
#define R9A07G043_PD_SCIF0 33
#define R9A07G043_PD_SCIF1 34
#define R9A07G043_PD_SCIF2 35
#define R9A07G043_PD_SCIF3 36
#define R9A07G043_PD_SCIF4 37
#define R9A07G043_PD_SCI0 38
#define R9A07G043_PD_SCI1 39
#define R9A07G043_PD_IRDA 40
#define R9A07G043_PD_RSPI0 41
#define R9A07G043_PD_RSPI1 42
#define R9A07G043_PD_RSPI2 43
#define R9A07G043_PD_CANFD 44
#define R9A07G043_PD_ADC 45
#define R9A07G043_PD_TSU 46
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
include/dt-bindings/clock/r9a07g044-cpg.h
View file @ 7552d1b9
......@@ -217,4 +217,62 @@
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
/* Power domain IDs. */
#define R9A07G044_PD_ALWAYS_ON 0
#define R9A07G044_PD_GIC 1
#define R9A07G044_PD_IA55 2
#define R9A07G044_PD_MHU 3
#define R9A07G044_PD_CORESIGHT 4
#define R9A07G044_PD_SYC 5
#define R9A07G044_PD_DMAC 6
#define R9A07G044_PD_GTM0 7
#define R9A07G044_PD_GTM1 8
#define R9A07G044_PD_GTM2 9
#define R9A07G044_PD_MTU 10
#define R9A07G044_PD_POE3 11
#define R9A07G044_PD_GPT 12
#define R9A07G044_PD_POEGA 13
#define R9A07G044_PD_POEGB 14
#define R9A07G044_PD_POEGC 15
#define R9A07G044_PD_POEGD 16
#define R9A07G044_PD_WDT0 17
#define R9A07G044_PD_WDT1 18
#define R9A07G044_PD_SPI 19
#define R9A07G044_PD_SDHI0 20
#define R9A07G044_PD_SDHI1 21
#define R9A07G044_PD_3DGE 22
#define R9A07G044_PD_ISU 23
#define R9A07G044_PD_VCPL4 24
#define R9A07G044_PD_CRU 25
#define R9A07G044_PD_MIPI_DSI 26
#define R9A07G044_PD_LCDC 27
#define R9A07G044_PD_SSI0 28
#define R9A07G044_PD_SSI1 29
#define R9A07G044_PD_SSI2 30
#define R9A07G044_PD_SSI3 31
#define R9A07G044_PD_SRC 32
#define R9A07G044_PD_USB0 33
#define R9A07G044_PD_USB1 34
#define R9A07G044_PD_USB_PHY 35
#define R9A07G044_PD_ETHER0 36
#define R9A07G044_PD_ETHER1 37
#define R9A07G044_PD_I2C0 38
#define R9A07G044_PD_I2C1 39
#define R9A07G044_PD_I2C2 40
#define R9A07G044_PD_I2C3 41
#define R9A07G044_PD_SCIF0 42
#define R9A07G044_PD_SCIF1 43
#define R9A07G044_PD_SCIF2 44
#define R9A07G044_PD_SCIF3 45
#define R9A07G044_PD_SCIF4 46
#define R9A07G044_PD_SCI0 47
#define R9A07G044_PD_SCI1 48
#define R9A07G044_PD_IRDA 49
#define R9A07G044_PD_RSPI0 50
#define R9A07G044_PD_RSPI1 51
#define R9A07G044_PD_RSPI2 52
#define R9A07G044_PD_CANFD 53
#define R9A07G044_PD_ADC 54
#define R9A07G044_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
include/dt-bindings/clock/r9a07g054-cpg.h
View file @ 7552d1b9
......@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
/* Power domain IDs. */
#define R9A07G054_PD_ALWAYS_ON 0
#define R9A07G054_PD_GIC 1
#define R9A07G054_PD_IA55 2
#define R9A07G054_PD_MHU 3
#define R9A07G054_PD_CORESIGHT 4
#define R9A07G054_PD_SYC 5
#define R9A07G054_PD_DMAC 6
#define R9A07G054_PD_GTM0 7
#define R9A07G054_PD_GTM1 8
#define R9A07G054_PD_GTM2 9
#define R9A07G054_PD_MTU 10
#define R9A07G054_PD_POE3 11
#define R9A07G054_PD_GPT 12
#define R9A07G054_PD_POEGA 13
#define R9A07G054_PD_POEGB 14
#define R9A07G054_PD_POEGC 15
#define R9A07G054_PD_POEGD 16
#define R9A07G054_PD_WDT0 17
#define R9A07G054_PD_WDT1 18
#define R9A07G054_PD_SPI 19
#define R9A07G054_PD_SDHI0 20
#define R9A07G054_PD_SDHI1 21
#define R9A07G054_PD_3DGE 22
#define R9A07G054_PD_ISU 23
#define R9A07G054_PD_VCPL4 24
#define R9A07G054_PD_CRU 25
#define R9A07G054_PD_MIPI_DSI 26
#define R9A07G054_PD_LCDC 27
#define R9A07G054_PD_SSI0 28
#define R9A07G054_PD_SSI1 29
#define R9A07G054_PD_SSI2 30
#define R9A07G054_PD_SSI3 31
#define R9A07G054_PD_SRC 32
#define R9A07G054_PD_USB0 33
#define R9A07G054_PD_USB1 34
#define R9A07G054_PD_USB_PHY 35
#define R9A07G054_PD_ETHER0 36
#define R9A07G054_PD_ETHER1 37
#define R9A07G054_PD_I2C0 38
#define R9A07G054_PD_I2C1 39
#define R9A07G054_PD_I2C2 40
#define R9A07G054_PD_I2C3 41
#define R9A07G054_PD_SCIF0 42
#define R9A07G054_PD_SCIF1 43
#define R9A07G054_PD_SCIF2 44
#define R9A07G054_PD_SCIF3 45
#define R9A07G054_PD_SCIF4 46
#define R9A07G054_PD_SCI0 47
#define R9A07G054_PD_SCI1 48
#define R9A07G054_PD_IRDA 49
#define R9A07G054_PD_RSPI0 50
#define R9A07G054_PD_RSPI1 51
#define R9A07G054_PD_RSPI2 52
#define R9A07G054_PD_CANFD 53
#define R9A07G054_PD_ADC 54
#define R9A07G054_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
include/dt-bindings/clock/r9a08g045-cpg.h
View file @ 7552d1b9
......@@ -239,4 +239,74 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
/* Power domain IDs. */
#define R9A08G045_PD_ALWAYS_ON 0
#define R9A08G045_PD_GIC 1
#define R9A08G045_PD_IA55 2
#define R9A08G045_PD_MHU 3
#define R9A08G045_PD_CORESIGHT 4
#define R9A08G045_PD_SYC 5
#define R9A08G045_PD_DMAC 6
#define R9A08G045_PD_GTM0 7
#define R9A08G045_PD_GTM1 8
#define R9A08G045_PD_GTM2 9
#define R9A08G045_PD_GTM3 10
#define R9A08G045_PD_GTM4 11
#define R9A08G045_PD_GTM5 12
#define R9A08G045_PD_GTM6 13
#define R9A08G045_PD_GTM7 14
#define R9A08G045_PD_MTU 15
#define R9A08G045_PD_POE3 16
#define R9A08G045_PD_GPT 17
#define R9A08G045_PD_POEGA 18
#define R9A08G045_PD_POEGB 19
#define R9A08G045_PD_POEGC 20
#define R9A08G045_PD_POEGD 21
#define R9A08G045_PD_WDT0 22
#define R9A08G045_PD_XSPI 23
#define R9A08G045_PD_SDHI0 24
#define R9A08G045_PD_SDHI1 25
#define R9A08G045_PD_SDHI2 26
#define R9A08G045_PD_SSI0 27
#define R9A08G045_PD_SSI1 28
#define R9A08G045_PD_SSI2 29
#define R9A08G045_PD_SSI3 30
#define R9A08G045_PD_SRC 31
#define R9A08G045_PD_USB0 32
#define R9A08G045_PD_USB1 33
#define R9A08G045_PD_USB_PHY 34
#define R9A08G045_PD_ETHER0 35
#define R9A08G045_PD_ETHER1 36
#define R9A08G045_PD_I2C0 37
#define R9A08G045_PD_I2C1 38
#define R9A08G045_PD_I2C2 39
#define R9A08G045_PD_I2C3 40
#define R9A08G045_PD_SCIF0 41
#define R9A08G045_PD_SCIF1 42
#define R9A08G045_PD_SCIF2 43
#define R9A08G045_PD_SCIF3 44
#define R9A08G045_PD_SCIF4 45
#define R9A08G045_PD_SCIF5 46
#define R9A08G045_PD_SCI0 47
#define R9A08G045_PD_SCI1 48
#define R9A08G045_PD_IRDA 49
#define R9A08G045_PD_RSPI0 50
#define R9A08G045_PD_RSPI1 51
#define R9A08G045_PD_RSPI2 52
#define R9A08G045_PD_RSPI3 53
#define R9A08G045_PD_RSPI4 54
#define R9A08G045_PD_CANFD 55
#define R9A08G045_PD_ADC 56
#define R9A08G045_PD_TSU 57
#define R9A08G045_PD_OCTA 58
#define R9A08G045_PD_PDM 59
#define R9A08G045_PD_PCI 60
#define R9A08G045_PD_SPDIF 61
#define R9A08G045_PD_I3C 62
#define R9A08G045_PD_VBAT 63
#define R9A08G045_PD_DDR 64
#define R9A08G045_PD_TZCDDR 65
#define R9A08G045_PD_OTFDE_DDR 66
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
include/dt-bindings/reset/st,stm32mp25-rcc.h
View file @ 7552d1b9
......@@ -69,7 +69,7 @@
#define ADC3_R 59
#define ETH1_R 60
#define ETH2_R 61
#define USB2_R 62
#define USBH_R 62
#define USB2PHY1_R 63
#define USB2PHY2_R 64
#define USB3DR_R 65
......
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