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Commit 7b70c427 authored by Russell King's avatar Russell King
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Merge branch 'devel-stable' into devel 

Conflicts:
	arch/arm/kernel/entry-armv.S
	arch/arm/kernel/setup.c
	arch/arm/mm/init.c
parents ceb0885d a20df564
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Showing with 13840 additions and 3553 deletions
arch/arm/Kconfig
View file @ 7b70c427
......@@ -303,6 +303,7 @@ config ARCH_CNS3XXX
select CPU_V6
select GENERIC_CLOCKEVENTS
select ARM_GIC
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
......@@ -469,6 +470,19 @@ config ARCH_LOKI
help
Support for the Marvell Loki (88RC8480) SoC.
config ARCH_LPC32XX
bool "NXP LPC32XX"
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
select HAVE_IDE
select ARM_AMBA
select USB_ARCH_HAS_OHCI
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
Support for the NXP LPC32XX family of processors
config ARCH_MV78XX0
bool "Marvell MV78xx0"
select CPU_FEROCEON
......@@ -573,6 +587,7 @@ config ARCH_MSM
bool "Qualcomm MSM"
select HAVE_CLK
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
help
Support for Qualcomm MSM/QSD based systems. This runs on the
apps processor of the MSM/QSD and depends on a shared memory
......@@ -831,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-loki/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
......@@ -1041,7 +1058,7 @@ config ISA_DMA_API
bool
config PCI
bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
......@@ -1372,6 +1389,24 @@ config UACCESS_WITH_MEMCPY
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
config CC_STACKPROTECTOR
bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
help
This option turns on the -fstack-protector GCC feature. This
feature puts, at the beginning of functions, a canary value on
the stack just before the return address, and validates
the value just before actually returning. Stack based buffer
overflows (that need to overwrite this return address) now also
overwrite the canary, which gets detected and the attack is then
neutralized via a kernel panic.
This feature requires gcc version 4.2 or above.
config DEPRECATED_PARAM_STRUCT
bool "Provide old way to pass kernel parameters"
help
This was deprecated in 2001 and announced to live on for 5 years.
Some old boot loaders still use this way.
endmenu
menu "Boot options"
......@@ -1482,6 +1517,105 @@ config ATAGS_PROC
Should the atags used to boot the kernel be exported in an "atags"
file in procfs. Useful with kexec.
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address"
depends on !ZBOOT_ROM && !ARCH_U300
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
will be determined at run-time by masking the current IP with
0xf8000000. This assumes the zImage being placed in the first 128MB
from start of memory.
config ZRELADDR
hex "Physical address of the decompressed kernel image"
depends on !AUTO_ZRELADDR
default 0x00008000 if ARCH_BCMRING ||\
ARCH_CNS3XXX ||\
ARCH_DOVE ||\
ARCH_EBSA110 ||\
ARCH_FOOTBRIDGE ||\
ARCH_INTEGRATOR ||\
ARCH_IOP13XX ||\
ARCH_IOP33X ||\
ARCH_IXP2000 ||\
ARCH_IXP23XX ||\
ARCH_IXP4XX ||\
ARCH_KIRKWOOD ||\
ARCH_KS8695 ||\
ARCH_LOKI ||\
ARCH_MMP ||\
ARCH_MV78XX0 ||\
ARCH_NOMADIK ||\
ARCH_NUC93X ||\
ARCH_NS9XXX ||\
ARCH_ORION5X ||\
ARCH_SPEAR3XX ||\
ARCH_SPEAR6XX ||\
ARCH_U8500 ||\
ARCH_VERSATILE ||\
ARCH_W90X900
default 0x08008000 if ARCH_MX1 ||\
ARCH_SHARK
default 0x10008000 if ARCH_MSM ||\
ARCH_OMAP1 ||\
ARCH_RPC
default 0x20008000 if ARCH_S5P6440 ||\
ARCH_S5P6442 ||\
ARCH_S5PC100 ||\
ARCH_S5PV210
default 0x30008000 if ARCH_S3C2410 ||\
ARCH_S3C2400 ||\
ARCH_S3C2412 ||\
ARCH_S3C2416 ||\
ARCH_S3C2440 ||\
ARCH_S3C2443
default 0x40008000 if ARCH_STMP378X ||\
ARCH_STMP37XX ||\
ARCH_SH7372 ||\
ARCH_SH7377
default 0x50008000 if ARCH_S3C64XX ||\
ARCH_SH7367
default 0x60008000 if ARCH_VEXPRESS
default 0x80008000 if ARCH_MX25 ||\
ARCH_MX3 ||\
ARCH_NETX ||\
ARCH_OMAP2PLUS ||\
ARCH_PNX4008
default 0x90008000 if ARCH_MX5 ||\
ARCH_MX91231
default 0xa0008000 if ARCH_IOP32X ||\
ARCH_PXA ||\
MACH_MX27
default 0xc0008000 if ARCH_LH7A40X ||\
MACH_MX21
default 0xf0008000 if ARCH_AAEC2000 ||\
ARCH_L7200
default 0xc0028000 if ARCH_CLPS711X
default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
default 0xc0208000 if ARCH_SA1100 && SA1111
default 0xc0008000 if ARCH_SA1100 && !SA1111
default 0x30108000 if ARCH_S3C2410 && PM_H1940
default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. ZRELADDR has to be specified when the
assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
selected.
endmenu
menu "CPU Power Management"
......
arch/arm/Makefile
View file @ 7b70c427
......@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
endif
ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
KBUILD_CFLAGS +=-fstack-protector
endif
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
KBUILD_CPPFLAGS += -mbig-endian
AS += -EB
......@@ -141,11 +145,12 @@ machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
machine-$(CONFIG_ARCH_KS8695) := ks8695
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_LOKI) := loki
machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
machine-$(CONFIG_ARCH_MMP) := mmp
machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := mx1
machine-$(CONFIG_ARCH_MX2) := mx2
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
......
arch/arm/boot/Makefile
View file @ 7b70c427
......@@ -14,18 +14,16 @@
MKIMAGE := $(srctree)/scripts/mkuboot.sh
ifneq ($(MACHINE),)
include $(srctree)/$(MACHINE)/Makefile.boot
-include $(srctree)/$(MACHINE)/Makefile.boot
endif
# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
ZRELADDR := $(zreladdr-y)
PARAMS_PHYS := $(params_phys-y)
INITRD_PHYS := $(initrd_phys-y)
export ZRELADDR INITRD_PHYS PARAMS_PHYS
export INITRD_PHYS PARAMS_PHYS
targets := Image zImage xipImage bootpImage uImage
......@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE $@
ifeq ($(CONFIG_ZBOOT_ROM),y)
$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
else
$(obj)/uImage: LOADADDR=$(ZRELADDR)
$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
endif
ifeq ($(CONFIG_THUMB2_KERNEL),y)
......
arch/arm/boot/compressed/Makefile
View file @ 7b70c427
......@@ -4,6 +4,7 @@
# create a compressed vmlinuz image from the original vmlinux
#
AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
HEAD = head.o
OBJS = misc.o decompress.o
FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
......@@ -75,19 +76,9 @@ endif
EXTRA_CFLAGS := -fpic -fno-builtin
EXTRA_AFLAGS := -Wa,-march=all
# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
# linker symbols. We only define initrd_phys and params_phys if the
# machine class defined the corresponding makefile variable.
LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
LDFLAGS_vmlinux += --be8
endif
ifneq ($(INITRD_PHYS),)
LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
endif
ifneq ($(PARAMS_PHYS),)
LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
endif
# ?
LDFLAGS_vmlinux += -p
# Report unresolved symbol references
......
arch/arm/boot/compressed/Makefile.debug deleted 100644 → 0
View file @ ceb0885d
#
# linux/arch/arm/boot/compressed/Makefile
#
# create a compressed vmlinux image from the original vmlinux
#
COMPRESSED_EXTRA=../../lib/ll_char_wr.o
OBJECTS=misc-debug.o ll_char_wr.aout.o
CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
test-gzip: piggy.aout.o $(OBJECTS)
$(CC) -o $@ $(OBJECTS) piggy.aout.o
misc-debug.o: misc.c
$(CC) $(CFLAGS) -o $@ misc.c
piggy.aout.o: piggy.o
arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
arch/arm/boot/compressed/head.S
View file @ 7b70c427
......@@ -170,9 +170,16 @@ not_angel:
.text
adr r0, LC0
ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
ARM( ldmia r0, {r1, r2, r3, r5, r6, r11, ip, sp})
THUMB( ldmia r0, {r1, r2, r3, r5, r6, r11, ip} )
THUMB( ldr sp, [r0, #32] )
#ifdef CONFIG_AUTO_ZRELADDR
@ determine final kernel image address
and r4, pc, #0xf8000000
add r4, r4, #TEXT_OFFSET
#else
ldr r4, =CONFIG_ZRELADDR
#endif
subs r0, r0, r1 @ calculate the delta offset
@ if delta is zero, we are
......@@ -310,18 +317,17 @@ wont_overwrite: mov r0, r4
LC0: .word LC0 @ r1
.word __bss_start @ r2
.word _end @ r3
.word zreladdr @ r4
.word _start @ r5
.word _image_size @ r6
.word _got_start @ r11
.word _got_end @ ip
.word user_stack+4096 @ sp
.word user_stack_end @ sp
LC1: .word reloc_end - reloc_start
.size LC0, . - LC0
#ifdef CONFIG_ARCH_RPC
.globl params
params: ldr r0, =params_phys
params: ldr r0, =0x10000100 @ params_phys for RPC
mov pc, lr
.ltorg
.align
......@@ -339,9 +345,8 @@ params: ldr r0, =params_phys
* r4 = kernel execution address
* r7 = architecture number
* r8 = atags pointer
* r9 = run-time address of "start" (???)
* On exit,
* r1, r2, r3, r9, r10, r12 corrupted
* r0, r1, r2, r3, r9, r10, r12 corrupted
* This routine must preserve:
* r4, r5, r6, r7, r8
*/
......@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
mov r0, #0
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
/*
* ?? ARMv3 MMU does not allow reading the control register,
* does this really work on ARMv3 MPU?
*/
mrc p15, 0, r0, c1, c0, 0 @ read control reg
@ .... .... .... WC.M
orr r0, r0, #0x000d @ .... .... .... 11.1
/* ?? this overwrites the value constructed above? */
mov r0, #0
mcr p15, 0, r0, c1, c0, 0 @ write control reg
/* ?? invalidate for the second time? */
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
......@@ -771,8 +782,10 @@ proc_types:
* Turn off the Cache and MMU. ARMv3 does not support
* reading the control register, but ARMv4 does.
*
* On exit, r0, r1, r2, r3, r9, r12 corrupted
* This routine must preserve: r4, r6, r7
* On exit,
* r0, r1, r2, r3, r9, r12 corrupted
* This routine must preserve:
* r4, r6, r7
*/
.align 5
cache_off: mov r3, #12 @ cache_off function
......@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
* Clean and flush the cache to maintain consistency.
*
* On exit,
* r1, r2, r3, r9, r11, r12 corrupted
* r1, r2, r3, r9, r10, r11, r12 corrupted
* This routine must preserve:
* r0, r4, r5, r6, r7
*/
......@@ -988,7 +1001,7 @@ no_cache_id:
__armv3_mmu_cache_flush:
__armv3_mpu_cache_flush:
mov r1, #0
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
/*
......@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
phexbuf: .space 12
.size phexbuf, . - phexbuf
@ phex corrupts {r0, r1, r2, r3}
phex: adr r3, phexbuf
mov r2, #0
strb r2, [r3, r1]
......@@ -1015,6 +1029,7 @@ phex: adr r3, phexbuf
strb r2, [r3, r1]
b 1b
@ puts corrupts {r0, r1, r2, r3}
puts: loadsp r3, r1
1: ldrb r2, [r0], #1
teq r2, #0
......@@ -1029,12 +1044,14 @@ puts: loadsp r3, r1
teq r0, #0
bne 1b
mov pc, lr
@ putc corrupts {r0, r1, r2, r3}
putc:
mov r2, r0
mov r0, #0
loadsp r3, r1
b 2b
@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
memdump: mov r12, r0
mov r10, lr
mov r11, #0
......@@ -1070,3 +1087,4 @@ reloc_end:
.align
.section ".stack", "w"
user_stack: .space 4096
user_stack_end:
arch/arm/boot/compressed/misc.c
View file @ 7b70c427
......@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
#include <asm/unaligned.h>
#ifdef STANDALONE_DEBUG
#define putstr printf
#else
static void putstr(const char *ptr);
extern void error(char *x);
......@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
flush();
}
#endif
void *memcpy(void *__dest, __const void *__src, size_t __n)
{
......@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
#ifndef STANDALONE_DEBUG
unsigned long
decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
......@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
putstr(" done, booting the kernel.\n");
return output_ptr;
}
#else
char output_buffer[1500*1024];
int main()
{
output_data = output_buffer;
putstr("Uncompressing Linux...");
decompress(input_data, input_data_end - input_data,
NULL, NULL, output_data, NULL, error);
putstr("done.\n");
return 0;
}
#endif
arch/arm/configs/kirkwood_defconfig
View file @ 7b70c427
......@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
CONFIG_MACH_RD88F6281=y
CONFIG_MACH_MV88F6281GTW_GE=y
CONFIG_MACH_SHEEVAPLUG=y
CONFIG_MACH_ESATA_SHEEVAPLUG=y
CONFIG_MACH_GURUPLUG=y
CONFIG_MACH_TS219=y
CONFIG_MACH_TS41X=y
CONFIG_MACH_OPENRD_BASE=y
CONFIG_MACH_OPENRD_CLIENT=y
CONFIG_MACH_OPENRD_ULTIMATE=y
CONFIG_MACH_NETSPACE_V2=y
CONFIG_MACH_INETSPACE_V2=y
CONFIG_MACH_NETSPACE_MAX_V2=y
CONFIG_MACH_NET2BIG_V2=y
CONFIG_MACH_NET5BIG_V2=y
CONFIG_MACH_T5325=y
# CONFIG_CPU_FEROCEON_OLD_ID is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
......
arch/arm/include/asm/elf.h
View file @ 7b70c427
......@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
extern void elf_set_personality(const struct elf32_hdr *);
#define SET_PERSONALITY(ex) elf_set_personality(&(ex))
struct mm_struct;
extern unsigned long arch_randomize_brk(struct mm_struct *mm);
#define arch_randomize_brk arch_randomize_brk
#endif
arch/arm/include/asm/mach/pci.h
View file @ 7b70c427
......@@ -46,6 +46,7 @@ struct pci_sys_data {
/* IRQ mapping */
int (*map_irq)(struct pci_dev *, u8, u8);
struct hw_pci *hw;
void *private_data; /* platform controller private data */
};
/*
......
arch/arm/include/asm/stackprotector.h 0 → 100644
View file @ 7b70c427
/*
* GCC stack protector support.
*
* Stack protector works by putting predefined pattern at the start of
* the stack frame and verifying that it hasn't been overwritten when
* returning from the function. The pattern is called stack canary
* and gcc expects it to be defined by a global variable called
* "__stack_chk_guard" on ARM. This unfortunately means that on SMP
* we cannot have a different canary value per task.
*/
#ifndef _ASM_STACKPROTECTOR_H
#define _ASM_STACKPROTECTOR_H 1
#include <linux/random.h>
#include <linux/version.h>
extern unsigned long __stack_chk_guard;
/*
* Initialize the stackprotector canary value.
*
* NOTE: this must only be called from functions that never return,
* and it must always be inlined.
*/
static __always_inline void boot_init_stack_canary(void)
{
unsigned long canary;
/* Try to get a semi random initial value. */
get_random_bytes(&canary, sizeof(canary));
canary ^= LINUX_VERSION_CODE;
current->stack_canary = canary;
__stack_chk_guard = current->stack_canary;
}
#endif /* _ASM_STACKPROTECTOR_H */
arch/arm/kernel/Makefile
View file @ 7b70c427
......@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
# Object file lists.
obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \
obj-y := elf.o entry-armv.o entry-common.o irq.o \
process.o ptrace.o return_address.o setup.o signal.o \
sys_arm.o stacktrace.o time.o traps.o
obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
obj-$(CONFIG_LEDS) += leds.o
obj-$(CONFIG_OC_ETM) += etm.o
......
arch/arm/kernel/asm-offsets.c
View file @ 7b70c427
......@@ -40,6 +40,9 @@
int main(void)
{
DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
#ifdef CONFIG_CC_STACKPROTECTOR
DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
#endif
BLANK();
DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
......
arch/arm/kernel/compat.c
View file @ 7b70c427
......@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
struct param_struct *params = (struct param_struct *)tags;
build_tag_list(params, &params->u2);
}
void __init squash_mem_tags(struct tag *tag)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM)
tag->hdr.tag = ATAG_NONE;
}
arch/arm/kernel/compat.h
View file @ 7b70c427
......@@ -9,5 +9,3 @@
*/
extern void convert_to_tag_list(struct tag *tags);
extern void squash_mem_tags(struct tag *tag);
arch/arm/kernel/entry-armv.S
View file @ 7b70c427
......@@ -737,6 +737,11 @@ ENTRY(__switch_to)
ldr r6, [r2, #TI_CPU_DOMAIN]
#endif
set_tls r3, r4, r5
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
ldr r7, [r2, #TI_TASK]
ldr r8, =__stack_chk_guard
ldr r7, [r7, #TSK_STACK_CANARY]
#endif
#ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
#endif
......@@ -745,6 +750,9 @@ ENTRY(__switch_to)
ldr r0, =thread_notify_head
mov r1, #THREAD_NOTIFY_SWITCH
bl atomic_notifier_call_chain
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
str r7, [r8]
#endif
THUMB( mov ip, r4 )
mov r0, r5
ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
......
arch/arm/kernel/process.c
View file @ 7b70c427
......@@ -28,6 +28,7 @@
#include <linux/tick.h>
#include <linux/utsname.h>
#include <linux/uaccess.h>
#include <linux/random.h>
#include <asm/cacheflush.h>
#include <asm/leds.h>
......@@ -37,6 +38,12 @@
#include <asm/stacktrace.h>
#include <asm/mach/time.h>
#ifdef CONFIG_CC_STACKPROTECTOR
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
EXPORT_SYMBOL(__stack_chk_guard);
#endif
static const char *processor_modes[] = {
"USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
"UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
......@@ -445,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
} while (count ++ < 16);
return 0;
}
unsigned long arch_randomize_brk(struct mm_struct *mm)
{
unsigned long range_end = mm->brk + 0x02000000;
return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
arch/arm/kernel/setup.c
View file @ 7b70c427
......@@ -47,7 +47,9 @@
#include <asm/traps.h>
#include <asm/unwind.h>
#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
#include "compat.h"
#endif
#include "atags.h"
#include "tcm.h"
......@@ -755,6 +757,13 @@ static int __init setup_elfcorehdr(char *arg)
early_param("elfcorehdr", setup_elfcorehdr);
#endif /* CONFIG_CRASH_DUMP */
static void __init squash_mem_tags(struct tag *tag)
{
for (; tag->hdr.size; tag = tag_next(tag))
if (tag->hdr.tag == ATAG_MEM)
tag->hdr.tag = ATAG_NONE;
}
void __init setup_arch(char **cmdline_p)
{
struct tag *tags = (struct tag *)&init_tags;
......@@ -775,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
else if (mdesc->boot_params)
tags = phys_to_virt(mdesc->boot_params);
#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
/*
* If we have the old style parameters, convert them to
* a tag list.
*/
if (tags->hdr.tag != ATAG_CORE)
convert_to_tag_list(tags);
#endif
if (tags->hdr.tag != ATAG_CORE)
tags = (struct tag *)&init_tags;
......
arch/arm/mach-cns3xxx/Makefile
View file @ 7b70c427
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
arch/arm/mach-cns3xxx/cns3420vb.c
View file @ 7b70c427
......@@ -32,6 +32,7 @@
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include "core.h"
#include "devices.h"
/*
* NOR Flash
......@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
{
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
cns3xxx_ahci_init();
cns3xxx_sdhci_init();
pm_power_off = cns3xxx_power_off;
}
......
arch/arm/mach-cns3xxx/devices.c 0 → 100644
View file @ 7b70c427
/*
* CNS3xxx common devices
*
* Copyright 2008 Cavium Networks
* Scott Shu
* Copyright 2010 MontaVista Software, LLC.
* Anton Vorontsov <avorontsov@mvista.com>
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/compiler.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include "core.h"
#include "devices.h"
/*
* AHCI
*/
static struct resource cns3xxx_ahci_resource[] = {
[0] = {
.start = CNS3XXX_SATA2_BASE,
.end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CNS3XXX_SATA,
.end = IRQ_CNS3XXX_SATA,
.flags = IORESOURCE_IRQ,
},
};
static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
static struct platform_device cns3xxx_ahci_pdev = {
.name = "ahci",
.id = 0,
.resource = cns3xxx_ahci_resource,
.num_resources = ARRAY_SIZE(cns3xxx_ahci_resource),
.dev = {
.dma_mask = &cns3xxx_ahci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init cns3xxx_ahci_init(void)
{
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
platform_device_register(&cns3xxx_ahci_pdev);
}
/*
* SDHCI
*/
static struct resource cns3xxx_sdhci_resources[] = {
[0] = {
.start = CNS3XXX_SDIO_BASE,
.end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CNS3XXX_SDIO,
.end = IRQ_CNS3XXX_SDIO,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cns3xxx_sdhci_pdev = {
.name = "sdhci-cns3xxx",
.id = 0,
.num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources),
.resource = cns3xxx_sdhci_resources,
};
void __init cns3xxx_sdhci_init(void)
{
u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
platform_device_register(&cns3xxx_sdhci_pdev);
}
arch/arm/mach-cns3xxx/devices.h 0 → 100644
View file @ 7b70c427
/*
* CNS3xxx common devices
*
* Copyright 2008 Cavium Networks
* Scott Shu
* Copyright 2010 MontaVista Software, LLC.
* Anton Vorontsov <avorontsov@mvista.com>
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __CNS3XXX_DEVICES_H_
#define __CNS3XXX_DEVICES_H_
void __init cns3xxx_ahci_init(void);
void __init cns3xxx_sdhci_init(void);
#endif /* __CNS3XXX_DEVICES_H_ */
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
View file @ 7b70c427
......@@ -247,37 +247,36 @@
* Misc block
*/
#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310)
#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
......@@ -300,21 +299,21 @@
/*
* Power management and clock control
*/
#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
#define PM_CSR_REG PMU_REG_VALUE(0x030)
#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
#define PM_CSR_REG PMU_MEM_MAP(0x030)
/* PM_CLK_GATE_REG */
#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
......
arch/arm/mach-cns3xxx/pcie.c 0 → 100644
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-cns3xxx/pm.c
View file @ 7b70c427
......@@ -6,18 +6,25 @@
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
void cns3xxx_pwr_clk_en(unsigned int block)
{
PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
u32 reg = __raw_readl(PM_CLK_GATE_REG);
reg |= (block & PM_CLK_GATE_REG_MASK);
__raw_writel(reg, PM_CLK_GATE_REG);
}
void cns3xxx_pwr_power_up(unsigned int block)
{
PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
/* Wait for 300us for the PLL output clock locked. */
udelay(300);
......@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
void cns3xxx_pwr_power_down(unsigned int block)
{
u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
/* write '1' to power down */
PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
reg |= (block & CNS3XXX_PWR_PLL_ALL);
__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
u32 reg = __raw_readl(PM_SOFT_RST_REG);
/*
* bit 0, 28, 29 => program low to reset,
* the other else program low and then high
*/
if (block & 0x30000001) {
PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
reg &= ~(block & PM_SOFT_RST_REG_MASK);
} else {
PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
reg &= ~(block & PM_SOFT_RST_REG_MASK);
reg |= (block & PM_SOFT_RST_REG_MASK);
}
__raw_writel(reg, PM_SOFT_RST_REG);
}
void cns3xxx_pwr_soft_rst(unsigned int block)
......@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
*/
int cns3xxx_cpu_clock(void)
{
u32 reg = __raw_readl(PM_CLK_CTRL_REG);
int cpu;
int cpu_sel;
int div_sel;
cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
......
arch/arm/mach-dove/common.c
View file @ 7b70c427
......@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
platform_device_register(&dove_xor11_channel);
}
/*****************************************************************************
* SDIO
****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);
static struct resource dove_sdio0_resources[] = {
{
.start = DOVE_SDIO0_PHYS_BASE,
.end = DOVE_SDIO0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SDIO0,
.end = IRQ_DOVE_SDIO0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_sdio0 = {
.name = "sdhci-mv",
.id = 0,
.dev = {
.dma_mask = &sdio_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = dove_sdio0_resources,
.num_resources = ARRAY_SIZE(dove_sdio0_resources),
};
void __init dove_sdio0_init(void)
{
platform_device_register(&dove_sdio0);
}
static struct resource dove_sdio1_resources[] = {
{
.start = DOVE_SDIO1_PHYS_BASE,
.end = DOVE_SDIO1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SDIO1,
.end = IRQ_DOVE_SDIO1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_sdio1 = {
.name = "sdhci-mv",
.id = 1,
.dev = {
.dma_mask = &sdio_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = dove_sdio1_resources,
.num_resources = ARRAY_SIZE(dove_sdio1_resources),
};
void __init dove_sdio1_init(void)
{
platform_device_register(&dove_sdio1);
}
void __init dove_init(void)
{
int tclk;
......
arch/arm/mach-dove/common.h
View file @ 7b70c427
......@@ -36,5 +36,7 @@ void dove_uart3_init(void);
void dove_spi0_init(void);
void dove_spi1_init(void);
void dove_i2c_init(void);
void dove_sdio0_init(void);
void dove_sdio1_init(void);
#endif
arch/arm/mach-dove/dove-db-setup.c
View file @ 7b70c427
......@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
dove_ehci0_init();
dove_ehci1_init();
dove_sata_init(&dove_db_sata_data);
dove_sdio0_init();
dove_sdio1_init();
dove_spi0_init();
dove_spi1_init();
dove_uart0_init();
......
arch/arm/mach-mx2/Kconfig → arch/arm/mach-imx/Kconfig
View file @ 7b70c427
config IMX_HAVE_DMA_V1
bool
if ARCH_MX1
config SOC_IMX1
select CPU_ARM920T
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
comment "MX1 platforms:"
config MACH_MXLADS
bool
config ARCH_MX1ADS
bool "MX1ADS platform"
select MACH_MXLADS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
Say Y here if you are using Motorola MX1ADS/MXLADS boards
config MACH_SCB9328
bool "Synertronixx scb9328"
select IMX_HAVE_PLATFORM_IMX_UART
help
Say Y here if you are using a Synertronixx scb9328 board
endif
if ARCH_MX2
config SOC_IMX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
choice
prompt "CPUs:"
default MACH_MX21
config MACH_MX21
bool "i.MX21 support"
select ARCH_MXC_AUDMUX_V1
select SOC_IMX21
help
This enables support for Freescale's MX2 based i.MX21 processor.
config MACH_MX27
bool "i.MX27 support"
select ARCH_MXC_AUDMUX_V1
select SOC_IMX27
help
This enables support for Freescale's MX2 based i.MX27 processor.
endchoice
comment "MX2 platforms:"
endif
if MACH_MX21
comment "MX21 platforms:"
config MACH_MX21ADS
bool "MX21ADS platform"
depends on MACH_MX21
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for MX21ADS platform. This includes specific
configurations for the board and its peripherals.
endif
if MACH_MX27
comment "MX27 platforms:"
config MACH_MX27ADS
bool "MX27ADS platform"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for MX27ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for phyCORE-i.MX27 (aka pcm038) platform. This
......@@ -58,7 +119,9 @@ endchoice
config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for Eukrea CPUIMX27 platform. This includes
specific configurations for the module and its peripherals.
......@@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_CPUIMX27
help
This adds support for the internal SDHC2 used on CPUIMX27 used
This adds support for the internal SDHC2 used on CPUIMX27
for wifi or eMMC.
config MACH_EUKREA_CPUIMX27_USEUART4
bool "CPUIMX27 integrates UART4 module"
depends on MACH_CPUIMX27
help
This adds support for the internal UART4 used on CPUIMX27
for bluetooth.
choice
prompt "Baseboard"
depends on MACH_CPUIMX27
......@@ -78,6 +148,8 @@ choice
config MACH_EUKREA_MBIMX27_BASEBOARD
prompt "Eukrea MBIMX27 development board"
bool
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SPI_IMX
help
This adds board specific devices that can be found on Eukrea's
MBIMX27 evaluation board.
......@@ -86,21 +158,24 @@ endchoice
config MACH_MX27_3DS
bool "MX27PDK platform"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX27 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for phyCARD-s (aka pca100) platform. This
......@@ -108,7 +183,9 @@ config MACH_PCA100
config MACH_MXT_TD60
bool "Maxtrack i-MXT TD60"
depends on MACH_MX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for i-MXT (aka td60) platform. This
includes specific configurations for the module and its peripherals.
......
arch/arm/mach-mx2/Makefile → arch/arm/mach-imx/Makefile
View file @ 7b70c427
......@@ -4,14 +4,24 @@
# Object file lists.
obj-y := devices.o serial.o
obj-y := devices.o
obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
......
arch/arm/mach-mx2/Makefile.boot → arch/arm/mach-imx/Makefile.boot
View file @ 7b70c427
zreladdr-$(CONFIG_ARCH_MX1) := 0x08008000
params_phys-$(CONFIG_ARCH_MX1) := 0x08000100
initrd_phys-$(CONFIG_ARCH_MX1) := 0x08800000
zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
......
arch/arm/mach-mx1/clock.c → arch/arm/mach-imx/clock-imx1.c
View file @ 7b70c427
......@@ -2,18 +2,17 @@
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
......@@ -29,7 +28,41 @@
#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include "crm_regs.h"
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
/* CCM register addresses */
#define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_PCDR IO_ADDR_CCM(0x20)
#define CCM_CSCR_CLKO_OFFSET 29
#define CCM_CSCR_CLKO_MASK (0x7 << 29)
#define CCM_CSCR_USB_OFFSET 26
#define CCM_CSCR_USB_MASK (0x7 << 26)
#define CCM_CSCR_OSC_EN_SHIFT 17
#define CCM_CSCR_SYSTEM_SEL (1 << 16)
#define CCM_CSCR_BCLK_OFFSET 10
#define CCM_CSCR_BCLK_MASK (0xf << 10)
#define CCM_CSCR_PRESC (1 << 15)
#define CCM_PCDR_PCLK3_OFFSET 16
#define CCM_PCDR_PCLK3_MASK (0x7f << 16)
#define CCM_PCDR_PCLK2_OFFSET 4
#define CCM_PCDR_PCLK2_MASK (0xf << 4)
#define CCM_PCDR_PCLK1_OFFSET 0
#define CCM_PCDR_PCLK1_MASK 0xf
#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
/* SCM register addresses */
#define SCM_GCCR IO_ADDR_SCM(0xc)
#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
static int _clk_enable(struct clk *clk)
{
......@@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref)
clk_enable(&hclk);
clk_enable(&fclk);
mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
MX1_TIM1_INT);
return 0;
}
arch/arm/mach-mx2/clock_imx27.c → arch/arm/mach-imx/clock-imx27.c
View file @ 7b70c427
......@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK(NULL, "csi", csi_clk)
_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
......
arch/arm/mach-imx/devices-imx1.h 0 → 100644
View file @ 7b70c427
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx1.h>
#include <mach/devices-common.h>
#define imx1_add_i2c_imx(pdata) \
imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
#define imx1_add_imx_uart0(pdata) \
imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
#define imx1_add_imx_uart1(pdata) \
imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
arch/arm/mach-imx/devices-imx21.h 0 → 100644
View file @ 7b70c427
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx21.h>
#include <mach/devices-common.h>
#define imx21_add_i2c_imx(pdata) \
imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
#define imx21_add_imx_uart0(pdata) \
imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
#define imx21_add_imx_uart1(pdata) \
imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
#define imx21_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
#define imx21_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
#define imx21_add_spi_imx0(pdata) \
imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
#define imx21_add_spi_imx1(pdata) \
imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
arch/arm/mach-imx/devices-imx27.h 0 → 100644
View file @ 7b70c427
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx27.h>
#include <mach/devices-common.h>
#define imx27_add_i2c_imx0(pdata) \
imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
#define imx27_add_i2c_imx1(pdata) \
imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
#define imx27_add_imx_uart0(pdata) \
imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
#define imx27_add_imx_uart1(pdata) \
imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
#define imx27_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
#define imx27_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
#define imx27_add_imx_uart4(pdata) \
imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
#define imx27_add_imx_uart5(pdata) \
imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
#define imx27_add_spi_imx0(pdata) \
imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
#define imx27_add_spi_imx1(pdata) \
imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
#define imx27_add_spi_imx2(pdata) \
imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
arch/arm/mach-mx2/devices.c → arch/arm/mach-imx/devices.c
View file @ 7b70c427
......@@ -11,6 +11,9 @@
*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
......@@ -32,6 +35,7 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
......@@ -40,38 +44,179 @@
#include "devices.h"
/*
* SPI master controller
*
* - i.MX1: 2 channel (slighly different register setting)
* - i.MX21: 2 channel
* - i.MX27: 3 channel
*/
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
static struct resource mxc_spi_resources ## n[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
}, \
}; \
\
struct platform_device mxc_spi_device ## n = { \
.name = "spi_imx", \
.id = n, \
.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
.resource = mxc_spi_resources ## n, \
#if defined(CONFIG_ARCH_MX1)
static struct resource imx1_camera_resources[] = {
{
.start = 0x00224000,
.end = 0x00224010,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CSI_INT,
.end = MX1_CSI_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
struct platform_device imx1_camera_device = {
.name = "mx1-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &imx1_camera_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = imx1_camera_resources,
.num_resources = ARRAY_SIZE(imx1_camera_resources),
};
static struct resource imx_rtc_resources[] = {
{
.start = 0x00204000,
.end = 0x00204024,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_RTC_INT,
.end = MX1_RTC_INT,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_RTC_SAMINT,
.end = MX1_RTC_SAMINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device = {
.name = "rtc-imx",
.id = 0,
.resource = imx_rtc_resources,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
};
static struct resource imx_wdt_resources[] = {
{
.start = 0x00201000,
.end = 0x00201008,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_WDT_INT,
.end = MX1_WDT_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_wdt_device = {
.name = "imx-wdt",
.id = 0,
.resource = imx_wdt_resources,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
};
static struct resource imx_usb_resources[] = {
{
.start = 0x00212000,
.end = 0x00212148,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_USBD_INT0,
.end = MX1_USBD_INT0,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT1,
.end = MX1_USBD_INT1,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT2,
.end = MX1_USBD_INT2,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT3,
.end = MX1_USBD_INT3,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT4,
.end = MX1_USBD_INT4,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT5,
.end = MX1_USBD_INT5,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT6,
.end = MX1_USBD_INT6,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_usb_device = {
.name = "imx_udc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_usb_resources),
.resource = imx_usb_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
.irq = MX1_GPIO_INT_PORTA,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
.irq = MX1_GPIO_INT_PORTB,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
.irq = MX1_GPIO_INT_PORTC,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
.irq = MX1_GPIO_INT_PORTD,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx1_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
#endif
DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
static struct resource mx27_camera_resources[] = {
{
.start = MX27_CSI_BASE_ADDR,
.end = MX27_CSI_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_EMMA_PRP_BASE_ADDR,
.end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_CSI,
.end = MX27_INT_CSI,
.flags = IORESOURCE_IRQ,
},{
.start = MX27_INT_EMMAPRP,
.end = MX27_INT_EMMAPRP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx27_camera_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx27_camera_resources),
.resource = mx27_camera_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
#endif
/*
......@@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = {
.resource = mxc_w1_master_resources,
};
#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
static struct resource pfx ## _nand_resources[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
}, \
}; \
\
struct platform_device pfx ## _nand_device = { \
.name = "mxc_nand", \
.id = 0, \
.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
.resource = pfx ## _nand_resources, \
}
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
#endif
/*
* lcdc:
* - i.MX1: the basic controller
......@@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = {
};
#endif
#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
static struct resource mxc_i2c_resources ## n[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
} \
}; \
\
struct platform_device mxc_i2c_device ## n = { \
.name = "imx-i2c", \
.id = n, \
.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
.resource = mxc_i2c_resources ## n, \
}
DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
#ifdef CONFIG_MACH_MX27
DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
#endif
static struct resource mxc_pwm_resources[] = {
{
.start = MX2x_PWM_BASE_ADDR,
......@@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
int __init imx21_register_gpios(void)
{
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
#endif
int __init mxc_register_gpios(void)
int __init imx27_register_gpios(void)
{
#ifdef CONFIG_MACH_MX21
if (cpu_is_mx21())
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
else
#endif
#ifdef CONFIG_MACH_MX27
if (cpu_is_mx27())
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
else
#endif
return 0;
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
......@@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = {
};
#endif
static struct resource imx_kpp_resources[] = {
{
.start = MX2x_KPP_BASE_ADDR,
.end = MX2x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX2x_INT_KPP,
.end = MX2x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
#endif
arch/arm/mach-mx2/devices.h → arch/arm/mach-imx/devices.h
View file @ 7b70c427
#ifdef CONFIG_ARCH_MX1
extern struct platform_device imx1_camera_device;
extern struct platform_device imx_rtc_device;
extern struct platform_device imx_wdt_device;
extern struct platform_device imx_usb_device;
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2;
#ifdef CONFIG_MACH_MX27
......@@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5;
#endif
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_uart_device3;
extern struct platform_device mxc_uart_device4;
extern struct platform_device mxc_uart_device5;
extern struct platform_device mxc_w1_master_device;
#ifdef CONFIG_MACH_MX21
extern struct platform_device imx21_nand_device;
#endif
#ifdef CONFIG_MACH_MX27
extern struct platform_device imx27_nand_device;
#endif
extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_fec_device;
extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_i2c_device0;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_i2c_device1;
#endif
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mx27_camera_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_spi_device2;
#endif
extern struct platform_device mx21_usbhc_device;
extern struct platform_device imx_ssi_device0;
extern struct platform_device imx_ssi_device1;
extern struct platform_device imx_kpp_device;
#endif
arch/arm/plat-mxc/dma-mx1-mx2.c → arch/arm/mach-imx/dma-v1.c
View file @ 7b70c427
/*
* linux/arch/arm/plat-mxc/dma-mx1-mx2.c
* linux/arch/arm/plat-mxc/dma-v1.c
*
* i.MX DMA registration and IRQ dispatching
*
......@@ -34,7 +34,7 @@
#include <asm/system.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/dma-mx1-mx2.h>
#include <mach/dma-v1.h>
#define DMA_DCR 0x00 /* Control Register */
#define DMA_DISR 0x04 /* Interrupt status Register */
......
arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c → arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View file @ 7b70c427
/*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
* Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
......@@ -24,6 +24,9 @@
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/backlight.h>
#include <video/platform_lcd.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach/arch.h>
......@@ -32,8 +35,11 @@
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/imx-uart.h>
#include <mach/spi.h>
#include <mach/ssi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices.h"
static int eukrea_mbimx27_pins[] = {
......@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* UART4 */
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
#endif
/* SDHC1*/
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
......@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* SPI1 */
PD28_PF_CSPI1_SS0,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* SSI4 */
#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
PC16_PF_SSI4_FS,
PC17_PF_SSI4_RXD | GPIO_PUEN,
PC18_PF_SSI4_TXD | GPIO_PUEN,
PC19_PF_SSI4_CLK,
#endif
};
static const uint32_t eukrea_mbimx27_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(0, 1, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_LEFT),
};
static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
.keymap = eukrea_mbimx27_keymap,
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
static struct gpio_led gpio_leds[] = {
......@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
.active_low = 1,
.gpio = GPIO_PORTF | 19,
},
{
.name = "backlight",
.default_trigger = "backlight",
.active_low = 0,
.gpio = GPIO_PORTE | 5,
},
};
static struct gpio_led_platform_data gpio_led_info = {
......@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
{
.mode = {
.name = "CMO-QGVA",
.name = "CMO-QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
......@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
},
.pcr = 0xFAD08B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 32000,
.hsync_len = 1,
.left_margin = 35,
.right_margin = 0,
.vsync_len = 1,
.upper_margin = 7,
.lower_margin = 0,
},
.pcr = 0xFA208B80,
.bpp = 16,
}, {
.mode = {
.name = "DVI-SVGA",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.hsync_len = 1,
.left_margin = 35,
.right_margin = 0,
.vsync_len = 1,
.upper_margin = 7,
.lower_margin = 0,
},
.pcr = 0xFA208B80,
.bpp = 16,
},
};
......@@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
.dmacr = 0x00040060,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
},
{
.flags = IMXUART_HAVE_RTSCTS,
static void eukrea_mbimx27_bl_set_intensity(int intensity)
{
if (intensity)
gpio_direction_output(GPIO_PORTE | 5, 1);
else
gpio_direction_output(GPIO_PORTE | 5, 0);
}
static struct generic_bl_info eukrea_mbimx27_bl_info = {
.name = "eukrea_mbimx27-bl",
.max_intensity = 0xff,
.default_intensity = 0xff,
.set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
};
static struct platform_device eukrea_mbimx27_bl_dev = {
.name = "generic-bl",
.id = 1,
.dev = {
.platform_data = &eukrea_mbimx27_bl_info,
},
};
#if defined(CONFIG_TOUCHSCREEN_ADS7846)
static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(GPIO_PORTA | 25, 1);
else
gpio_direction_output(GPIO_PORTA | 25, 0);
}
static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
.set_power = eukrea_mbimx27_lcd_power_set,
};
static struct platform_device eukrea_mbimx27_lcd_powerdev = {
.name = "platform-lcd",
.dev.platform_data = &eukrea_mbimx27_lcd_power_data,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
#define ADS7846_PENDOWN (GPIO_PORTD | 25)
......@@ -173,7 +262,6 @@ static void ads7846_dev_init(void)
printk(KERN_ERR "can't get ads746 pen down GPIO\n");
return;
}
gpio_direction_input(ADS7846_PENDOWN);
}
......@@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
.get_pendown_state = ads7846_get_pendown_state,
.keep_vref_on = 1,
};
#endif
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
[0] = {
.modalias = "ads7846",
......@@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
.chipselect = eukrea_mbimx27_spi_cs,
.num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
};
#endif
static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
static struct platform_device *platform_devices[] __initdata = {
&leds_gpio,
};
static struct imxmmc_platform_data sdhc_pdata = {
.dat3_card_detect = 1,
};
struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
.flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
};
/*
* system init for baseboard usage. Will be called by cpuimx27 init.
*
......@@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
/* SSI unit master I2S codec connected to SSI_PINS_4*/
mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
MXC_AUDMUX_V1_PCR_SYN |
MXC_AUDMUX_V1_PCR_TFSDIR |
MXC_AUDMUX_V1_PCR_TCLKDIR |
MXC_AUDMUX_V1_PCR_RFSDIR |
MXC_AUDMUX_V1_PCR_RCLKDIR |
MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
);
mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
MXC_AUDMUX_V1_PCR_SYN |
MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
);
#endif
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
imx27_add_imx_uart3(&uart_pdata);
#endif
mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
mxc_register_device(&mxc_sdhc_device0, NULL);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
#if defined(CONFIG_TOUCHSCREEN_ADS7846)
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* SPI and ADS7846 Touchscreen controler init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
/* ADS7846 Touchscreen controller init */
mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
ads7846_dev_init();
#endif
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
/* SPI_CS0 init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
spi_register_board_info(eukrea_mbimx27_spi_board_info,
ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
ads7846_dev_init();
#endif
/* Leds configuration */
......@@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
/* Backlight */
mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
gpio_request(GPIO_PORTE | 5, "backlight");
platform_device_register(&eukrea_mbimx27_bl_dev);
/* LCD Reset */
mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
gpio_request(GPIO_PORTA | 25, "lcd_enable");
platform_device_register(&eukrea_mbimx27_lcd_powerdev);
mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
arch/arm/mach-imx/include/mach/dma-mx1-mx2.h 0 → 100644
View file @ 7b70c427
#ifndef __MACH_DMA_MX1_MX2_H__
#define __MACH_DMA_MX1_MX2_H__
/*
* Don't use this header in new code, it will go away when all users are
* converted to mach/dma-v1.h
*/
#include <mach/dma-v1.h>
#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h → arch/arm/mach-imx/include/mach/dma-v1.h
View file @ 7b70c427
/*
* linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
* linux/arch/arm/mach-imx/include/mach/dma-v1.h
*
* i.MX DMA registration and IRQ dispatching
*
......@@ -22,8 +22,10 @@
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_DMA_H
#define __ASM_ARCH_MXC_DMA_H
#ifndef __MACH_DMA_V1_H__
#define __MACH_DMA_V1_H__
#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define IMX_DMA_CHANNELS 16
......@@ -102,4 +104,4 @@ enum imx_dma_prio {
int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
#endif /* _ASM_ARCH_MXC_DMA_H */
#endif /* __MACH_DMA_V1_H__ */
arch/arm/mach-mx2/mach-cpuimx27.c → arch/arm/mach-imx/mach-cpuimx27.c
View file @ 7b70c427
......@@ -26,20 +26,24 @@
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/board-eukrea_cpuimx27.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/iomux-mx27.h>
#include <mach/imx-uart.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static int eukrea_cpuimx27_pins[] = {
......@@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART4 */
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
#endif
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
......@@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* SDHC2 */
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* Quad UART's IRQ */
GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
#endif
/* OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* USBH2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
......@@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
.resource = &eukrea_cpuimx27_flash_resource,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
static const struct mxc_nand_platform_data
cpuimx27_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
......@@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_fec_device,
&mxc_wdt,
&mxc_w1_master_device,
};
static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -182,34 +215,83 @@ static struct platform_device serial_device = {
};
#endif
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static int otg_mode_host;
static int __init eukrea_cpuimx27_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = 1;
else if (!strcmp(options, "device"))
otg_mode_host = 0;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 0;
}
__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
static void __init eukrea_cpuimx27_init(void)
{
mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
imx27_add_imx_uart0(&uart_pdata);
mxc_register_device(&imx27_nand_device,
&eukrea_cpuimx27_nand_board_info);
imx27_add_mxc_nand(&cpuimx27_nand_board_info);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
mxc_register_device(&mxc_sdhc_device1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
imx27_add_imx_uart3(&uart_pdata);
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
platform_device_register(&serial_device);
#endif
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();
#endif
......
arch/arm/mach-mx2/mach-imx27lite.c → arch/arm/mach-imx/mach-imx27lite.c
View file @ 7b70c427
......@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/platform_device.h>
......@@ -26,10 +22,9 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx27.h>
#include <mach/board-mx27lite.h>
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mx27lite_pins[] = {
......@@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
PF23_AIN_FEC_TX_EN,
};
static struct imxuart_platform_data uart_pdata = {
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
......@@ -71,7 +66,7 @@ static void __init mx27lite_init(void)
{
mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
"imx27lite");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
imx27_add_imx_uart0(&uart_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
......
arch/arm/mach-mx1/mach-mx1ads.c → arch/arm/mach-imx/mach-mx1ads.c
View file @ 7b70c427
......@@ -26,10 +26,10 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx1.h>
#include <mach/irqs.h>
#include "devices-imx1.h"
#include "devices.h"
static int mx1ads_pins[] = {
......@@ -58,12 +58,12 @@ static int mx1ads_pins[] = {
* UARTs platform data
*/
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
static const struct imxuart_platform_data uart0_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/*
......@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
};
static struct resource flash_resource = {
.start = IMX_CS0_PHYS,
.end = IMX_CS0_PHYS + SZ_32M - 1,
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
......@@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
}
};
static struct imxi2c_platform_data mx1ads_i2c_data = {
static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
.bitrate = 100000,
};
......@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
ARRAY_SIZE(mx1ads_pins), "mx1ads");
/* UART */
mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
imx1_add_imx_uart0(&uart0_pdata);
imx1_add_imx_uart1(&uart1_pdata);
/* Physmap flash */
mxc_register_device(&flash_device, &mx1ads_flash_data);
......@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
i2c_register_board_info(0, mx1ads_i2c_devices,
ARRAY_SIZE(mx1ads_i2c_devices));
mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
imx1_add_i2c_imx(&mx1ads_i2c_data);
}
static void __init mx1ads_timer_init(void)
......@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
MACHINE_START(MX1ADS, "Freescale MX1ADS")
/* Maintainer: Sascha Hauer, Pengutronix */
.phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.phys_io = MX1_IO_BASE_ADDR,
.io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = MX1_PHYS_OFFSET + 0x100,
.map_io = mx1_map_io,
.init_irq = mx1_init_irq,
......@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
MACHINE_END
MACHINE_START(MXLADS, "Freescale MXLADS")
.phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.phys_io = MX1_IO_BASE_ADDR,
.io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
.boot_params = MX1_PHYS_OFFSET + 0x100,
.map_io = mx1_map_io,
.init_irq = mx1_init_irq,
......
arch/arm/mach-mx2/mach-mx21ads.c → arch/arm/mach-imx/mach-mx21ads.c
View file @ 7b70c427
......@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/platform_device.h>
......@@ -28,15 +24,49 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#include <mach/board-mx21ads.h>
#include "devices-imx21.h"
#include "devices.h"
/*
* Memory-mapped I/O on MX21ADS base board
*/
#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
#define MX21ADS_MMIO_SIZE SZ_16M
#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
(MX21ADS_MMIO_BASE_ADDR + (offset))
#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
/* MX21ADS_IO_REG bit definitions */
#define MX21ADS_IO_SD_WP 0x0001 /* read */
#define MX21ADS_IO_TP6 0x0001 /* write */
#define MX21ADS_IO_SW_SEL 0x0002 /* read */
#define MX21ADS_IO_TP7 0x0002 /* write */
#define MX21ADS_IO_RESET_E_UART 0x0004
#define MX21ADS_IO_RESET_BASE 0x0008
#define MX21ADS_IO_CSI_CTL2 0x0010
#define MX21ADS_IO_CSI_CTL1 0x0020
#define MX21ADS_IO_CSI_CTL0 0x0040
#define MX21ADS_IO_UART1_EN 0x0080
#define MX21ADS_IO_UART4_EN 0x0100
#define MX21ADS_IO_LCDON 0x0200
#define MX21ADS_IO_IRDA_EN 0x0400
#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
#define MX21ADS_IO_IRDA_MD0_B 0x1000
#define MX21ADS_IO_IRDA_MD1 0x2000
#define MX21ADS_IO_LED4_ON 0x4000
#define MX21ADS_IO_LED3_ON 0x8000
static unsigned int mx21ads_pins[] = {
/* CS8900A */
......@@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
.resource = &mx21ads_flash_resource,
};
static struct imxuart_platform_data uart_pdata = {
static const struct imxuart_platform_data uart_pdata_rts __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct imxuart_platform_data uart_norts_pdata = {
static const struct imxuart_platform_data uart_pdata_norts __initconst = {
};
static int mx21ads_fb_init(struct platform_device *pdev)
{
u16 tmp;
......@@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
.exit = mx21ads_sdhc_exit,
};
static struct mxc_nand_platform_data mx21ads_nand_board_info = {
static const struct mxc_nand_platform_data
mx21ads_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
......@@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void)
mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
"mx21ads");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
mxc_register_device(&mxc_uart_device3, &uart_pdata);
imx21_add_imx_uart0(&uart_pdata_rts);
imx21_add_imx_uart2(&uart_pdata_norts);
imx21_add_imx_uart3(&uart_pdata_rts);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
......
arch/arm/mach-mx2/mach-mx27_3ds.c → arch/arm/mach-imx/mach-mx27_3ds.c
View file @ 7b70c427
......@@ -12,23 +12,25 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* This machine is known as:
* - i.MX27 3-Stack Development System
* - i.MX27 Platform Development Kit (i.MX27 PDK)
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx27.h>
#include <mach/board-mx27pdk.h>
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mx27pdk_pins[] = {
......@@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = {
PF23_AIN_FEC_TX_EN,
};
static struct imxuart_platform_data uart_pdata = {
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
......@@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = {
&mxc_fec_device,
};
/*
* Matrix keyboard
*/
static const uint32_t mx27_3ds_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(0, 1, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_LEFT),
KEY(1, 2, KEY_ENTER),
KEY(2, 0, KEY_F6),
KEY(2, 1, KEY_F8),
KEY(2, 2, KEY_F9),
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx27_3ds_keymap_data = {
.keymap = mx27_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
static void __init mx27pdk_init(void)
{
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
mxc_register_device(&mxc_uart_device0, &uart_pdata);
imx27_add_imx_uart0(&uart_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
}
static void __init mx27pdk_timer_init(void)
......
arch/arm/mach-mx2/mach-mx27ads.c → arch/arm/mach-imx/mach-mx27ads.c
View file @ 7b70c427
......@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/platform_device.h>
......@@ -32,16 +28,44 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx27.h>
#include <mach/board-mx27ads.h>
#include <mach/mxc_nand.h>
#include <mach/i2c.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
/*
* Base address of PBC controller, CS4
*/
#define PBC_BASE_ADDRESS 0xf4300000
#define PBC_REG_ADDR(offset) (void __force __iomem *) \
(PBC_BASE_ADDRESS + (offset))
/* When the PBC address connection is fixed in h/w, defined as 1 */
#define PBC_ADDR_SH 0
/* Offsets for the PBC Controller register */
/*
* PBC Board version register offset
*/
#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
/*
* PBC Board control register 1 set address.
*/
#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
/*
* PBC Board control register 1 clear address.
*/
#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET (1 << 3)
static unsigned int mx27ads_pins[] = {
/* UART0 */
PE12_PF_UART1_TXD,
......@@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = {
PB9_PF_SD2_CLK,
};
static struct mxc_nand_platform_data mx27ads_nand_board_info = {
static const struct mxc_nand_platform_data
mx27ads_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
......@@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
.resource = &mx27ads_flash_resource,
};
static struct imxi2c_platform_data mx27ads_i2c_data = {
static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static void __init mx27ads_board_init(void)
......@@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void)
mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
"mx27ads");
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
imx27_add_imx_uart3(&uart_pdata);
imx27_add_imx_uart4(&uart_pdata);
imx27_add_imx_uart5(&uart_pdata);
imx27_add_mxc_nand(&mx27ads_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, mx27ads_i2c_devices,
ARRAY_SIZE(mx27ads_i2c_devices));
mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
imx27_add_i2c_imx1(&mx27ads_i2c1_data);
mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
......@@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
.init_machine = mx27ads_board_init,
.timer = &mx27ads_timer,
MACHINE_END
arch/arm/mach-mx2/mach-mxt_td60.c → arch/arm/mach-imx/mach-mxt_td60.c
View file @ 7b70c427
......@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/platform_device.h>
......@@ -32,14 +28,13 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/i2c.h>
#include <linux/i2c/pca953x.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mxt_td60_pins[] __initdata = {
......@@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = {
PB9_PF_SD2_CLK,
};
static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
static const struct mxc_nand_platform_data
mxt_td60_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
static struct imxi2c_platform_data mxt_td60_i2c_data = {
static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
.bitrate = 100000,
};
......@@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
},
};
static struct imxi2c_platform_data mxt_td60_i2c2_data = {
static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
&mxc_fec_device,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static void __init mxt_td60_board_init(void)
......@@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void)
mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
"MXT_TD60");
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
imx27_add_mxc_nand(&mxt_td60_nand_board_info);
i2c_register_board_info(0, mxt_td60_i2c_devices,
ARRAY_SIZE(mxt_td60_i2c_devices));
......@@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void)
i2c_register_board_info(1, mxt_td60_i2c2_devices,
ARRAY_SIZE(mxt_td60_i2c2_devices));
mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
......
arch/arm/mach-mx2/mach-pca100.c → arch/arm/mach-imx/mach-pca100.c
View file @ 7b70c427
......@@ -36,12 +36,7 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/i2c.h>
#include <asm/mach/time.h>
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
#include <mach/spi.h>
#endif
#include <mach/imx-uart.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include <mach/mxc_nand.h>
......@@ -49,11 +44,16 @@
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/imxfb.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
#define SPI1_SS0 (GPIO_PORTD + 28)
#define SPI1_SS1 (GPIO_PORTD + 27)
#define SD2_CD (GPIO_PORTC + 29)
static int pca100_pins[] = {
/* UART1 */
......@@ -68,6 +68,7 @@ static int pca100_pins[] = {
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
SD2_CD | GPIO_GPIO | GPIO_IN,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
......@@ -131,13 +132,42 @@ static int pca100_pins[] = {
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA26_PF_PS,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
/* free GPIO */
GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
};
static struct imxuart_platform_data uart_pdata = {
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct mxc_nand_platform_data pca100_nand_board_info = {
static const struct mxc_nand_platform_data
pca100_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
......@@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = {
&mxc_wdt,
};
static struct imxi2c_platform_data pca100_i2c_1_data = {
static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
},
};
static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
static struct spi_imx_master pca100_spi_0_data = {
static const struct spi_imx_master pca100_spi0_data __initconst = {
.chipselect = pca100_spi_cs,
.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
};
......@@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
.exit = pca100_sdhc2_exit,
};
#if defined(CONFIG_USB_ULPI)
static int otg_phy_init(struct platform_device *pdev)
{
gpio_set_value(OTG_PHY_CS_GPIO, 0);
......@@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
......@@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
}
__setup("otg_mode=", pca100_otg_mode);
/* framebuffer info */
static struct imx_fb_videomode pca100_fb_modes[] = {
{
.mode = {
.name = "EMERGING-ETV570G0DHU",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722, /* in ps (25.175 MHz) */
.hsync_len = 30,
.left_margin = 114,
.right_margin = 16,
.vsync_len = 3,
.upper_margin = 32,
.lower_margin = 0,
},
/*
* TFT
* Pixel pol active high
* HSYNC active low
* VSYNC active low
* use HSYNC for ACD count
* line clock disable while idle
* always enable line clock even if no data
*/
.pcr = 0xf0c08080,
.bpp = 16,
},
};
static struct imx_fb_platform_data pca100_fb_data = {
.mode = pca100_fb_modes,
.num_modes = ARRAY_SIZE(pca100_fb_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static void __init pca100_init(void)
{
int ret;
......@@ -320,33 +391,24 @@ static void __init pca100_init(void)
mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
imx27_add_imx_uart0(&uart_pdata);
mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
imx27_add_mxc_nand(&pca100_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pca100_i2c_devices,
ARRAY_SIZE(pca100_i2c_devices));
mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
/* GPIO0_IRQ */
mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
/* GPIO1_IRQ */
mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
/* GPIO2_IRQ */
mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
imx27_add_i2c_imx1(&pca100_i2c1_data);
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
spi_register_board_info(pca100_spi_board_info,
ARRAY_SIZE(pca100_spi_board_info));
mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
imx27_add_spi_imx0(&pca100_spi_0_data);
#endif
gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
......@@ -372,6 +434,8 @@ static void __init pca100_init(void)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
}
mxc_register_device(&mxc_fb_device, &pca100_fb_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
......
arch/arm/mach-mx2/mach-pcm038.c → arch/arm/mach-imx/mach-pcm038.c
View file @ 7b70c427
......@@ -35,14 +35,12 @@
#include <mach/board-pcm038.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/iomux-mx27.h>
#include <mach/imx-uart.h>
#include <mach/mxc_nand.h>
#include <mach/spi.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static int pcm038_pins[] = {
......@@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = {
.resource = &pcm038_flash_resource,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct mxc_nand_platform_data pcm038_nand_board_info = {
static const struct mxc_nand_platform_data
pcm038_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
};
......@@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void)
mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
}
static struct imxi2c_platform_data pcm038_i2c_1_data = {
static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
static struct spi_imx_master pcm038_spi_0_data = {
static const struct spi_imx_master pcm038_spi0_data __initconst = {
.chipselect = pcm038_spi_cs,
.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
};
......@@ -305,18 +298,18 @@ static void __init pcm038_init(void)
pcm038_init_sram();
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
imx27_add_imx_uart0(&uart_pdata);
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
mxc_gpio_mode(PE16_AF_OWIRE);
mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
imx27_add_mxc_nand(&pcm038_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pcm038_i2c_devices,
ARRAY_SIZE(pcm038_i2c_devices));
mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
imx27_add_i2c_imx1(&pcm038_i2c1_data);
/* PE18 for user-LED D40 */
mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
......@@ -326,7 +319,7 @@ static void __init pcm038_init(void)
/* MC13783 IRQ */
mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
imx27_add_spi_imx0(&pcm038_spi0_data);
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
......
arch/arm/mach-mx1/mach-scb9328.c → arch/arm/mach-imx/mach-scb9328.c
View file @ 7b70c427
......@@ -22,17 +22,17 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
#include "devices.h"
/*
* This scb9328 has a 32MiB flash
*/
static struct resource flash_resource = {
.start = IMX_CS0_PHYS,
.end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
.flags = IORESOURCE_MEM,
};
......@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
static struct resource dm9000x_resources[] = {
{
.name = "address area",
.start = IMX_CS5_PHYS,
.end = IMX_CS5_PHYS + 1,
.start = MX1_CS5_PHYS,
.end = MX1_CS5_PHYS + 1,
.flags = IORESOURCE_MEM, /* address access */
}, {
.name = "data area",
.start = IMX_CS5_PHYS + 4,
.end = IMX_CS5_PHYS + 5,
.start = MX1_CS5_PHYS + 4,
.end = MX1_CS5_PHYS + 5,
.flags = IORESOURCE_MEM, /* data access */
}, {
.start = IRQ_GPIOC(3),
......@@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev)
ARRAY_SIZE(mxc_uart1_pins), "UART1");
}
static int uart1_mxc_exit(struct platform_device *pdev)
static void uart1_mxc_exit(struct platform_device *pdev)
{
mxc_gpio_release_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins));
return 0;
}
static struct imxuart_platform_data uart_pdata = {
static const struct imxuart_platform_data uart_pdata __initconst = {
.init = uart1_mxc_init,
.exit = uart1_mxc_exit,
.flags = IMXUART_HAVE_RTSCTS,
......@@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
*/
static void __init scb9328_init(void)
{
mxc_register_device(&imx_uart1_device, &uart_pdata);
imx1_add_imx_uart0(&uart_pdata);
printk(KERN_INFO"Scb9328: Adding devices\n");
platform_add_devices(devices, ARRAY_SIZE(devices));
......
arch/arm/mach-mx1/generic.c → arch/arm/mach-imx/mm-imx1.c
View file @ 7b70c427
......@@ -3,7 +3,7 @@
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
* Common code for i.MX1 machines
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -14,11 +14,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
......@@ -31,23 +26,25 @@
static struct map_desc imx_io_desc[] __initdata = {
{
.virtual = IMX_IO_BASE,
.pfn = __phys_to_pfn(IMX_IO_PHYS),
.length = IMX_IO_SIZE,
.type = MT_DEVICE
.virtual = MX1_IO_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
.length = MX1_IO_SIZE,
.type = MT_DEVICE
}
};
void __init mx1_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX1);
mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
}
int imx1_register_gpios(void);
void __init mx1_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
imx1_register_gpios();
}
arch/arm/mach-mx2/mm-imx21.c → arch/arm/mach-imx/mm-imx21.c
View file @ 7b70c427
/*
* arch/arm/mach-mx2/mm-imx21.c
* arch/arm/mach-imx/mm-imx21.c
*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
......@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
}
int imx21_register_gpios(void);
void __init mx21_init_irq(void)
{
mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
imx21_register_gpios();
}
arch/arm/mach-mx2/mm-imx27.c → arch/arm/mach-imx/mm-imx27.c
View file @ 7b70c427
/*
* arch/arm/mach-mx2/mm-imx27.c
* arch/arm/mach-imx/mm-imx27.c
*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
......@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
}
int imx27_register_gpios(void);
void __init mx27_init_irq(void)
{
mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
imx27_register_gpios();
}
arch/arm/mach-imx/pm-imx27.c 0 → 100644
View file @ 7b70c427
/*
* i.MX27 Power Management Routines
*
* Based on Freescale's BSP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
#include <mach/system.h>
#include <mach/mx27.h>
static int mx27_suspend_enter(suspend_state_t state)
{
u32 cscr;
switch (state) {
case PM_SUSPEND_MEM:
/* Clear MPEN and SPEN to disable MPLL/SPLL */
cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
cscr &= 0xFFFFFFFC;
__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
/* Executes WFI */
arch_idle();
break;
default:
return -EINVAL;
}
return 0;
}
static struct platform_suspend_ops mx27_suspend_ops = {
.enter = mx27_suspend_enter,
.valid = suspend_valid_only_mem,
};
static int __init mx27_pm_init(void)
{
suspend_set_ops(&mx27_suspend_ops);
return 0;
}
device_initcall(mx27_pm_init);
arch/arm/mach-kirkwood/Kconfig
View file @ 7b70c427
......@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
Say 'Y' here if you want your kernel to support the
Marvell OpenRD Client Board.
config MACH_OPENRD_ULTIMATE
bool "Marvell OpenRD Ultimate Board"
select MACH_OPENRD
help
Say 'Y' here if you want your kernel to support the
Marvell OpenRD Ultimate Board.
config MACH_NETSPACE_V2
bool "LaCie Network Space v2 NAS Board"
help
......@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
Say 'Y' here if you want your kernel to support the
LaCie Internet Space v2 NAS.
config MACH_NETSPACE_MAX_V2
bool "LaCie Network Space Max v2 NAS Board"
help
Say 'Y' here if you want your kernel to support the
LaCie Network Space Max v2 NAS.
config MACH_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
help
......@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
Say 'Y' here if you want your kernel to support the
LaCie 5Big Network v2 NAS.
config MACH_T5325
bool "HP t5325 Thin Client"
help
Say 'Y' here if you want your kernel to support the
HP t5325 Thin Client.
endmenu
endif
arch/arm/mach-kirkwood/Makefile
View file @ 7b70c427
......@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
obj-$(CONFIG_MACH_T5325) += t5325-setup.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
arch/arm/mach-kirkwood/addr-map.c
View file @ 7b70c427
......@@ -31,6 +31,8 @@
#define ATTR_DEV_CS0 0x3e
#define ATTR_PCIE_IO 0xe0
#define ATTR_PCIE_MEM 0xe8
#define ATTR_PCIE1_IO 0xd0
#define ATTR_PCIE1_MEM 0xd8
#define ATTR_SRAM 0x01
/*
......@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
/*
* Setup window for NAND controller.
*/
setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
/*
* Setup window for SRAM.
*/
setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
TARGET_SRAM, ATTR_SRAM, -1);
/*
......
arch/arm/mach-kirkwood/common.c
View file @ 7b70c427
......@@ -43,6 +43,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
.length = KIRKWOOD_PCIE_IO_SIZE,
.type = MT_DEVICE,
}, {
.virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
.pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
.length = KIRKWOOD_PCIE1_IO_SIZE,
.type = MT_DEVICE,
}, {
.virtual = KIRKWOOD_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
......@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
u32 dev, rev;
kirkwood_pcie_id(&dev, &rev);
if (rev == 0) /* catch all Kirkwood Z0's */
if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
mvsdio_data->clock = 100000000;
else
mvsdio_data->clock = 200000000;
......@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
u32 dev, rev;
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
rev == MV88F6281_REV_A1))
if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
rev == MV88F6281_REV_A1)) ||
(dev == MV88F6282_DEV_ID))
return 200000000;
return 166666667;
......@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
return "MV88F6192-Z0";
else if (rev == MV88F6192_REV_A0)
return "MV88F6192-A0";
else if (rev == MV88F6192_REV_A1)
return "MV88F6192-A1";
else
return "MV88F6192-Rev-Unsupported";
} else if (dev == MV88F6180_DEV_ID) {
if (rev == MV88F6180_REV_A0)
return "MV88F6180-Rev-A0";
else if (rev == MV88F6180_REV_A1)
return "MV88F6180-Rev-A1";
else
return "MV88F6180-Rev-Unsupported";
} else if (dev == MV88F6282_DEV_ID) {
if (rev == MV88F6282_REV_A0)
return "MV88F6282-Rev-A0";
else
return "MV88F6282-Rev-Unsupported";
} else {
return "Device-Unknown";
}
......@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
static int __init kirkwood_clock_gate(void)
{
unsigned int curr = readl(CLOCK_GATING_CTRL);
u32 dev, rev;
kirkwood_pcie_id(&dev, &rev);
printk(KERN_DEBUG "Gating clock of unused units\n");
printk(KERN_DEBUG "before: 0x%08x\n", curr);
/* Make sure those units are accessible */
writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
/* For SATA: first shutdown the phy */
if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
......@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
}
/* For PCIe 1: first shutdown the phy */
if (dev == MV88F6282_DEV_ID) {
if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
while (1)
if (readl(PCIE1_STATUS) & 0x1)
break;
writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
}
} else /* keep this bit set for devices that don't have PCIe1 */
kirkwood_clk_ctrl |= CGC_PEX1;
/* Now gate clock the required units */
writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
......
arch/arm/mach-kirkwood/common.h
View file @ 7b70c427
......@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
struct mtd_partition;
struct mtd_info;
#define KW_PCIE0 (1 << 0)
#define KW_PCIE1 (1 << 1)
/*
* Basic Kirkwood init functions used early by machine-setup.
*/
......@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
void kirkwood_pcie_init(void);
void kirkwood_pcie_init(unsigned int portmask);
void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
void kirkwood_spi_init(void);
......
arch/arm/mach-kirkwood/db88f6281-bp-setup.c
View file @ 7b70c427
......@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
};
static unsigned int db88f6281_mpp_config[] __initdata = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP37_GPIO,
MPP38_GPIO,
0
......@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
static int __init db88f6281_pci_init(void)
{
if (machine_is_db88f6281_bp())
kirkwood_pcie_init();
if (machine_is_db88f6281_bp()) {
u32 dev, rev;
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6282_DEV_ID)
kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
else
kirkwood_pcie_init(KW_PCIE0);
}
return 0;
}
subsys_initcall(db88f6281_pci_init);
......
arch/arm/mach-kirkwood/include/mach/bridge-regs.h
View file @ 7b70c427
......@@ -59,8 +59,9 @@
#define CGC_SATA1 (1 << 15)
#define CGC_XOR1 (1 << 16)
#define CGC_CRYPTO (1 << 17)
#define CGC_PEX1 (1 << 18)
#define CGC_GE1 (1 << 19)
#define CGC_TDM (1 << 20)
#define CGC_RESERVED ((1 << 18) | (0x6 << 21))
#define CGC_RESERVED (0x6 << 21)
#endif
arch/arm/mach-kirkwood/include/mach/irqs.h
View file @ 7b70c427
......@@ -23,6 +23,7 @@
#define IRQ_KIRKWOOD_XOR_10 7
#define IRQ_KIRKWOOD_XOR_11 8
#define IRQ_KIRKWOOD_PCIE 9
#define IRQ_KIRKWOOD_PCIE1 10
#define IRQ_KIRKWOOD_GE00_SUM 11
#define IRQ_KIRKWOOD_GE01_SUM 15
#define IRQ_KIRKWOOD_USB 19
......
arch/arm/mach-kirkwood/include/mach/kirkwood.h
View file @ 7b70c427
......@@ -16,36 +16,48 @@
* Marvell Kirkwood address maps.
*
* phys
* e0000000 PCIe Memory space
* e0000000 PCIe #0 Memory space
* e8000000 PCIe #1 Memory space
* f1000000 on-chip peripheral registers
* f2000000 PCIe I/O space
* f3000000 NAND controller address window
* f4000000 Security Accelerator SRAM
* f2000000 PCIe #0 I/O space
* f3000000 PCIe #1 I/O space
* f4000000 NAND controller address window
* f5000000 Security Accelerator SRAM
*
* virt phys size
* fee00000 f1000000 1M on-chip peripheral registers
* fef00000 f2000000 1M PCIe I/O space
* fed00000 f1000000 1M on-chip peripheral registers
* fee00000 f2000000 1M PCIe #0 I/O space
* fef00000 f3000000 1M PCIe #1 I/O space
*/
#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000
#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
#define KIRKWOOD_SRAM_SIZE SZ_2K
#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000
#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
#define KIRKWOOD_REGS_SIZE SZ_1M
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
/*
* Register Map
*/
......@@ -72,6 +84,9 @@
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70)
#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
......@@ -107,8 +122,12 @@
#define MV88F6192_DEV_ID 0x6192
#define MV88F6192_REV_Z0 0
#define MV88F6192_REV_A0 2
#define MV88F6192_REV_A1 3
#define MV88F6180_DEV_ID 0x6180
#define MV88F6180_REV_A0 2
#define MV88F6180_REV_A1 3
#define MV88F6282_DEV_ID 0x6282
#define MV88F6282_REV_A0 0
#endif
arch/arm/mach-kirkwood/include/mach/leds-ns2.h 0 → 100644
View file @ 7b70c427
/*
* arch/arm/mach-kirkwood/include/mach/leds-ns2.h
*
* Platform data structure for Network Space v2 LED driver
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NS2_H
#define __MACH_LEDS_NS2_H
struct ns2_led {
const char *name;
const char *default_trigger;
unsigned cmd;
unsigned slow;
};
struct ns2_led_platform_data {
int num_leds;
struct ns2_led *leds;
};
#endif /* __MACH_LEDS_NS2_H */
arch/arm/mach-kirkwood/mpp.c
View file @ 7b70c427
......@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
kirkwood_pcie_id(&dev, &rev);
if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
(dev == MV88F6282_DEV_ID))
return MPP_F6281_MASK;
if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
return MPP_F6192_MASK;
......
arch/arm/mach-kirkwood/mpp.h
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
View file @ 7b70c427
......@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
static int __init mv88f6281gtw_ge_pci_init(void)
{
if (machine_is_mv88f6281gtw_ge())
kirkwood_pcie_init();
kirkwood_pcie_init(KW_PCIE0);
return 0;
}
......
arch/arm/mach-kirkwood/netspace_v2-setup.c
View file @ 7b70c427
......@@ -39,6 +39,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <mach/leds-ns2.h>
#include <plat/time.h>
#include "common.h"
#include "mpp.h"
......@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
}
if (err)
pr_err("netspace_v2: failed to setup SATA0 power\n");
if (machine_is_netspace_max_v2()) {
err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
if (err == 0) {
err = gpio_direction_output(
NETSPACE_V2_GPIO_SATA1_POWER, 1);
if (err)
gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
}
if (err)
pr_err("netspace_v2: failed to setup SATA1 power\n");
}
}
/*****************************************************************************
......@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
* GPIO LEDs
****************************************************************************/
/*
* The blue front LED is wired to a CPLD and can blink in relation with the
* SATA activity.
*
* The following array detail the different LED registers and the combination
* of their possible values:
*
* cmd_led | slow_led | /SATA active | LED state
* | | |
* 1 | 0 | x | off
* - | 1 | x | on
* 0 | 0 | 1 | on
* 0 | 0 | 0 | blink (rate 300ms)
*/
#define NETSPACE_V2_GPIO_RED_LED 12
#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
static struct gpio_led netspace_v2_gpio_led_pins[] = {
{
.name = "ns_v2:blue:sata",
.default_trigger = "default-on",
.gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD,
.active_low = 1,
},
{
.name = "ns_v2:red:fail",
.gpio = NETSPACE_V2_GPIO_RED_LED,
.name = "ns_v2:red:fail",
.gpio = NETSPACE_V2_GPIO_RED_LED,
},
};
......@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
},
};
static void __init netspace_v2_gpio_leds_init(void)
{
int err;
/*****************************************************************************
* Dual-GPIO CPLD LEDs
****************************************************************************/
/* Configure register slow_led to allow SATA activity LED blinking */
err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow");
if (err == 0) {
err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
if (err)
gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
}
if (err)
pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
platform_device_register(&netspace_v2_gpio_leds);
}
static struct ns2_led netspace_v2_led_pins[] = {
{
.name = "ns_v2:blue:sata",
.cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD,
.slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
},
};
static struct ns2_led_platform_data netspace_v2_leds_data = {
.num_leds = ARRAY_SIZE(netspace_v2_led_pins),
.leds = netspace_v2_led_pins,
};
static struct platform_device netspace_v2_leds = {
.name = "leds-ns2",
.id = -1,
.dev = {
.platform_data = &netspace_v2_leds_data,
},
};
/*****************************************************************************
* Timer
......@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP7_GPO, /* Fan speed (bit 1) */
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Red led */
MPP14_GPIO, /* USB fuse */
MPP16_GPIO, /* SATA 0 power */
MPP17_GPIO, /* SATA 1 power */
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_SATA1_ACTn,
MPP21_SATA0_ACTn,
MPP22_GPIO, /* Fan speed (bit 0) */
MPP23_GPIO, /* Fan power */
MPP24_GPIO, /* USB mode select */
MPP25_GPIO, /* Fan rotation fail */
MPP26_GPIO, /* USB device vbus */
......@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
MPP30_GPIO, /* Blue led (command register) */
MPP31_GPIO, /* Board power off */
MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
MPP33_GPO, /* Fan speed (bit 2) */
0
};
......@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
i2c_register_board_info(0, netspace_v2_i2c_info,
ARRAY_SIZE(netspace_v2_i2c_info));
netspace_v2_gpio_leds_init();
platform_device_register(&netspace_v2_leds);
platform_device_register(&netspace_v2_gpio_leds);
platform_device_register(&netspace_v2_gpio_buttons);
if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
......@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
.timer = &netspace_v2_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_NETSPACE_MAX_V2
MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netspace_v2_timer,
MACHINE_END
#endif
arch/arm/mach-kirkwood/netxbig_v2-setup.c
View file @ 7b70c427
......@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
MPP3_SPI_MISO,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Request power-off */
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP13_GPIO, /* Rear power switch (on|auto) */
......@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
MPP3_SPI_MISO,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Request power-off */
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP13_GPIO, /* Rear power switch (on|auto) */
......@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
MPP15_GPIO, /* Rear power switch (auto|off) */
MPP16_GPIO, /* SATA HDD1 power */
MPP17_GPIO, /* SATA HDD2 power */
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP20_GE1_TXD0,
MPP21_GE1_TXD1,
MPP22_GE1_TXD2,
MPP23_GE1_TXD3,
MPP24_GE1_RXD0,
MPP25_GE1_RXD1,
MPP26_GE1_RXD2,
MPP27_GE1_RXD3,
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* CPLD extension ALE */
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP30_GE1_RXCTL,
MPP31_GE1_RXCLK,
MPP32_GE1_TCLKOUT,
MPP33_GE1_TXCTL,
MPP34_GPIO, /* Rear Push button */
MPP35_GPIO, /* Inhibit switch power-off */
MPP36_GPIO, /* SATA HDD1 presence */
......
arch/arm/mach-kirkwood/openrd-setup.c
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-kirkwood/pcie.c
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
View file @ 7b70c427
......@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
static int __init rd88f6192_pci_init(void)
{
if (machine_is_rd88f6192_nas())
kirkwood_pcie_init();
kirkwood_pcie_init(KW_PCIE0);
return 0;
}
......
arch/arm/mach-kirkwood/rd88f6281-setup.c
View file @ 7b70c427
......@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
static int __init rd88f6281_pci_init(void)
{
if (machine_is_rd88f6281())
kirkwood_pcie_init();
kirkwood_pcie_init(KW_PCIE0);
return 0;
}
......
arch/arm/mach-kirkwood/t5325-setup.c 0 → 100644
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-kirkwood/ts219-setup.c
View file @ 7b70c427
......@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
MPP3_SPI_MISO,
MPP4_SATA1_ACTn,
MPP5_SATA0_ACTn,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP13_UART1_TXD, /* PIC controller */
......@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
MPP15_GPIO, /* USB Copy button */
MPP16_GPIO, /* Reset button */
MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */
MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */
0
};
......@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
static int __init ts219_pci_init(void)
{
if (machine_is_ts219())
kirkwood_pcie_init();
if (machine_is_ts219())
kirkwood_pcie_init(KW_PCIE0);
return 0;
return 0;
}
subsys_initcall(ts219_pci_init);
......
arch/arm/mach-kirkwood/ts41x-setup.c
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-lpc32xx/Kconfig 0 → 100644
View file @ 7b70c427
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arch/arm/mach-lpc32xx/Makefile 0 → 100644
View file @ 7b70c427
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arch/arm/mach-lpc32xx/Makefile.boot 0 → 100644
View file @ 7b70c427
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x82000000
arch/arm/mach-lpc32xx/clock.c 0 → 100644
View file @ 7b70c427
This diff is collapsed.
arch/arm/mach-lpc32xx/clock.h 0 → 100644
View file @ 7b70c427
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arch/arm/mach-lpc32xx/common.c 0 → 100644
View file @ 7b70c427
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arch/arm/mach-lpc32xx/common.h 0 → 100644
View file @ 7b70c427
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arch/arm/mach-lpc32xx/gpiolib.c 0 → 100644
View file @ 7b70c427
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