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Commit f69eda00 authored by Russell King's avatar Russell King Committed by Russell King
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Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale trees

parents bc43fd40 dd1d2f44 271f5ca6 108d093f 78c2644f 0e0ba769 850b4293
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Documentation/arm/Samsung-S3C24XX/DMA.txt 0 → 100644
View file @ f69eda00
S3C2410 DMA
===========
Introduction
------------
The kernel provides an interface to manage DMA transfers
using the DMA channels in the cpu, so that the central
duty of managing channel mappings, and programming the
channel generators is in one place.
DMA Channel Ordering
--------------------
Many of the range do not have connections for the DMA
channels to all sources, which means that some devices
have a restricted number of channels that can be used.
To allow flexibilty for each cpu type and board, the
dma code can be given an dma ordering structure which
allows the order of channel search to be specified, as
well as allowing the prohibition of certain claims.
struct s3c24xx_dma_order has a list of channels, and
each channel within has a slot for a list of dma
channel numbers. The slots are searched in order, for
the presence of a dma channel number with DMA_CH_VALID
orred in.
If the order has the flag DMA_CH_NEVER set, then after
checking the channel list, the system will return no
found channel, thus denying the request.
A board support file can call s3c24xx_dma_order_set()
to register an complete ordering set. The routine will
copy the data, so the original can be discared with
__initdata.
Authour
-------
Ben Dooks,
Copyright (c) 2007 Ben Dooks, Simtec Electronics
Licensed under the GPL v2
Documentation/arm/Samsung-S3C24XX/Overview.txt
View file @ f69eda00
......@@ -8,13 +8,10 @@ Introduction
The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
by the 's3c2410' architecture of ARM Linux. Currently the S3C2410,
S3C2440 and S3C2442 devices are supported.
S3C2412, S3C2413, S3C2440 and S3C2442 devices are supported.
Support for the S3C2400 series is in progress.
Support for the S3C2412 and S3C2413 CPUs is being merged.
Configuration
-------------
......@@ -26,6 +23,22 @@ Configuration
please check the machine specific documentation.
Layout
------
The core support files are located in the platform code contained in
arch/arm/plat-s3c24xx with headers in include/asm-arm/plat-s3c24xx.
This directory should be kept to items shared between the platform
code (arch/arm/plat-s3c24xx) and the arch/arm/mach-s3c24* code.
Each cpu has a directory with the support files for it, and the
machines that carry the device. For example S3C2410 is contained
in arch/arm/mach-s3c2410 and S3C2440 in arch/arm/mach-s3c2440
Register, kernel and platform data definitions are held in the
include/asm-arm/arch-s3c2410 directory.
Machines
--------
......
arch/arm/Kconfig
View file @ f69eda00
......@@ -280,6 +280,7 @@ config ARCH_PXA
bool "PXA2xx-based"
depends on MMU
select ARCH_MTD_XIP
select GENERIC_TIME
help
Support for Intel's PXA2XX processor line.
......@@ -303,7 +304,7 @@ config ARCH_SA1100
Support for StrongARM 11x0 based boards.
config ARCH_S3C2410
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442"
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
help
Samsung S3C2410X CPU based systems, such as the Simtec Electronics
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
......@@ -363,7 +364,16 @@ source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2440/Kconfig"
source "arch/arm/mach-s3c2442/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig"
endif
source "arch/arm/mach-lh7a40x/Kconfig"
......@@ -377,7 +387,7 @@ source "arch/arm/mach-aaec2000/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-at91rm9200/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-netx/Kconfig"
......
arch/arm/Makefile
View file @ f69eda00
......@@ -124,7 +124,7 @@ endif
machine-$(CONFIG_ARCH_H720X) := h720x
machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_AT91) := at91rm9200
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_NETX) := netx
......@@ -149,7 +149,7 @@ MACHINE := arch/arm/mach-$(machine-y)/
else
MACHINE :=
endif
export TEXT_OFFSET GZFLAGS MMUEXT
# Do we have FASTFPE?
......@@ -161,6 +161,11 @@ endif
# If we have a machine-specific directory, then include it in the build.
core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
core-y += $(MACHINE)
core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2400/
core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2412/
core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2440/
core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2442/
core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2443/
core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
core-$(CONFIG_VFP) += arch/arm/vfp/
......@@ -168,6 +173,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
# If we have a common platform directory, then include it in the build.
core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
......
arch/arm/common/dmabounce.c
View file @ f69eda00
......@@ -258,10 +258,14 @@ map_single(struct device *dev, void *ptr, size_t size,
ptr = buf->safe;
dma_addr = buf->safe_dma_addr;
} else {
/*
* We don't need to sync the DMA buffer since
* it was allocated via the coherent allocators.
*/
consistent_sync(ptr, size, dir);
}
consistent_sync(ptr, size, dir);
return dma_addr;
}
......@@ -294,12 +298,12 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
DO_STATS ( device_info->bounce_count++ );
if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
unsigned long ptr;
void *ptr = buf->ptr;
dev_dbg(dev,
"%s: copy back safe %p to unsafe %p size %d\n",
__func__, buf->safe, buf->ptr, size);
memcpy(buf->ptr, buf->safe, size);
__func__, buf->safe, ptr, size);
memcpy(ptr, buf->safe, size);
/*
* DMA buffers must have the same cache properties
......@@ -309,8 +313,8 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
* bidirectional case because we know the cache
* lines will be coherent with the data written.
*/
ptr = (unsigned long)buf->ptr;
dmac_clean_range(ptr, ptr + size);
outer_clean_range(__pa(ptr), __pa(ptr) + size);
}
free_safe_buffer(device_info, buf);
}
......@@ -374,7 +378,10 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
default:
BUG();
}
consistent_sync(buf->safe, size, dir);
/*
* No need to sync the safe buffer - it was allocated
* via the coherent allocators.
*/
} else {
consistent_sync(dma_to_virt(dev, dma_addr), size, dir);
}
......
arch/arm/common/gic.c
View file @ f69eda00
......@@ -14,7 +14,9 @@
*
* o There is one CPU Interface per CPU, which sends interrupts sent
* by the Distributor, and interrupts generated locally, to the
* associated CPU.
* associated CPU. The base address of the CPU interface is usually
* aliased so that the same address points to different chips depending
* on the CPU it is accessed from.
*
* Note that IRQs 0-31 are special - they are local to each CPU.
* As such, the enable set/clear, pending set/clear and active bit
......@@ -31,10 +33,38 @@
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
static void __iomem *gic_dist_base;
static void __iomem *gic_cpu_base;
static DEFINE_SPINLOCK(irq_controller_lock);
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
};
#ifndef MAX_GIC_NR
#define MAX_GIC_NR 1
#endif
static struct gic_chip_data gic_data[MAX_GIC_NR];
static inline void __iomem *gic_dist_base(unsigned int irq)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
return gic_data->dist_base;
}
static inline void __iomem *gic_cpu_base(unsigned int irq)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
return gic_data->cpu_base;
}
static inline unsigned int gic_irq(unsigned int irq)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
return irq - gic_data->irq_offset;
}
/*
* Routines to acknowledge, disable and enable interrupts
*
......@@ -55,8 +85,8 @@ static void gic_ack_irq(unsigned int irq)
u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
writel(irq, gic_cpu_base + GIC_CPU_EOI);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}
......@@ -65,7 +95,7 @@ static void gic_mask_irq(unsigned int irq)
u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
......@@ -74,14 +104,14 @@ static void gic_unmask_irq(unsigned int irq)
u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
#ifdef CONFIG_SMP
static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
{
void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
unsigned int shift = (irq % 4) * 8;
unsigned int cpu = first_cpu(mask_val);
u32 val;
......@@ -95,6 +125,37 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
}
#endif
static void fastcall gic_handle_cascade_irq(unsigned int irq,
struct irq_desc *desc)
{
struct gic_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
unsigned int cascade_irq;
unsigned long status;
/* primary controller ack'ing */
chip->ack(irq);
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
cascade_irq = (status & 0x3ff);
if (cascade_irq > 1020)
goto out;
if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
do_bad_IRQ(cascade_irq, desc);
goto out;
}
cascade_irq += chip_data->irq_offset;
generic_handle_irq(cascade_irq);
out:
/* primary controller unmasking */
chip->unmask(irq);
}
static struct irq_chip gic_chip = {
.name = "GIC",
.ack = gic_ack_irq,
......@@ -105,15 +166,29 @@ static struct irq_chip gic_chip = {
#endif
};
void __init gic_dist_init(void __iomem *base)
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{
if (gic_nr >= MAX_GIC_NR)
BUG();
if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
BUG();
set_irq_chained_handler(irq, gic_handle_cascade_irq);
}
void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int max_irq, i;
u32 cpumask = 1 << smp_processor_id();
if (gic_nr >= MAX_GIC_NR)
BUG();
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
gic_dist_base = base;
gic_data[gic_nr].dist_base = base;
gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
writel(0, base + GIC_DIST_CTRL);
......@@ -158,8 +233,9 @@ void __init gic_dist_init(void __iomem *base)
/*
* Setup the Linux IRQ subsystem.
*/
for (i = 29; i < max_irq; i++) {
for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
set_irq_chip(i, &gic_chip);
set_irq_chip_data(i, &gic_data[gic_nr]);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
......@@ -167,9 +243,13 @@ void __init gic_dist_init(void __iomem *base)
writel(1, base + GIC_DIST_CTRL);
}
void __cpuinit gic_cpu_init(void __iomem *base)
void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
{
gic_cpu_base = base;
if (gic_nr >= MAX_GIC_NR)
BUG();
gic_data[gic_nr].cpu_base = base;
writel(0xf0, base + GIC_CPU_PRIMASK);
writel(1, base + GIC_CPU_CTRL);
}
......@@ -179,6 +259,7 @@ void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
{
unsigned long map = *cpus_addr(cpumask);
writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
/* this always happens on GIC0 */
writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
arch/arm/configs/at91sam9263ek_defconfig 0 → 100644
View file @ f69eda00
This diff is collapsed.
arch/arm/configs/ateb9200_defconfig
View file @ f69eda00
......@@ -1066,7 +1066,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_AT91=y
CONFIG_RTC_DRV_AT91RM9200=y
# CONFIG_RTC_DRV_TEST is not set
#
......
arch/arm/configs/csb337_defconfig
View file @ f69eda00
......@@ -355,10 +355,12 @@ CONFIG_MTD_CFI_UTIL=y
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
CONFIG_MTD_CSB337=y
#
# Self-contained MTD device drivers
......@@ -986,7 +988,7 @@ CONFIG_RTC_DRV_DS1307=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_AT91=y
CONFIG_RTC_DRV_AT91RM9200=y
# CONFIG_RTC_DRV_TEST is not set
# CONFIG_RTC_DRV_V3020 is not set
......
arch/arm/configs/csb637_defconfig
View file @ f69eda00
......@@ -355,10 +355,12 @@ CONFIG_MTD_CFI_UTIL=y
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
CONFIG_MTD_CSB637=y
#
# Self-contained MTD device drivers
......
arch/arm/configs/kafa_defconfig
View file @ f69eda00
......@@ -718,7 +718,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_AT91=y
CONFIG_RTC_DRV_AT91RM9200=y
# CONFIG_RTC_DRV_TEST is not set
#
......
arch/arm/configs/s3c2410_defconfig
View file @ f69eda00
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.19-rc4
# Fri Nov 3 17:41:31 2006
# Linux kernel version: 2.6.20
# Thu Feb 15 11:26:24 2007
#
CONFIG_ARM=y
# CONFIG_GENERIC_TIME is not set
......@@ -11,6 +11,8 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_VECTORS_BASE=0xffff0000
......@@ -37,13 +39,14 @@ CONFIG_SYSVIPC=y
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
......@@ -76,7 +79,9 @@ CONFIG_KMOD=y
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
#
# IO Schedulers
......@@ -110,6 +115,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
......@@ -122,54 +128,73 @@ CONFIG_ARCH_S3C2410=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_OMAP is not set
CONFIG_PLAT_S3C24XX=y
CONFIG_CPU_S3C244X=y
CONFIG_PM_SIMTEC=y
# CONFIG_S3C2410_BOOT_WATCHDOG is not set
# CONFIG_S3C2410_BOOT_ERROR_RESET is not set
# CONFIG_S3C2410_PM_DEBUG is not set
# CONFIG_S3C2410_PM_CHECK is not set
CONFIG_S3C2410_LOWLEVEL_UART_PORT=0
CONFIG_S3C2410_DMA=y
# CONFIG_S3C2410_DMA_DEBUG is not set
CONFIG_MACH_SMDK=y
#
# S3C24XX Implementations
# S3C2400 Machines
#
# CONFIG_MACH_AML_M5900 is not set
CONFIG_MACH_ANUBIS=y
CONFIG_MACH_OSIRIS=y
CONFIG_ARCH_BAST=y
CONFIG_BAST_PC104_IRQ=y
CONFIG_CPU_S3C2410=y
CONFIG_CPU_S3C2410_DMA=y
CONFIG_S3C2410_PM=y
CONFIG_S3C2410_GPIO=y
CONFIG_S3C2410_CLOCK=y
#
# S3C2410 Machines
#
CONFIG_ARCH_SMDK2410=y
CONFIG_ARCH_H1940=y
CONFIG_PM_H1940=y
CONFIG_MACH_N30=y
CONFIG_MACH_SMDK=y
CONFIG_ARCH_SMDK2410=y
CONFIG_ARCH_S3C2440=y
CONFIG_SMDK2440_CPU2440=y
CONFIG_SMDK2440_CPU2442=y
CONFIG_MACH_S3C2413=y
CONFIG_MACH_SMDK2413=y
CONFIG_MACH_VR1000=y
CONFIG_MACH_RX3715=y
CONFIG_ARCH_BAST=y
CONFIG_MACH_OTOM=y
CONFIG_MACH_NEXCODER_2440=y
CONFIG_MACH_VSTMS=y
CONFIG_S3C2410_CLOCK=y
CONFIG_S3C2410_PM=y
CONFIG_CPU_S3C2410_DMA=y
CONFIG_CPU_S3C2410=y
CONFIG_S3C2412_PM=y
CONFIG_MACH_AML_M5900=y
CONFIG_BAST_PC104_IRQ=y
CONFIG_MACH_VR1000=y
CONFIG_CPU_S3C2412=y
CONFIG_CPU_S3C244X=y
CONFIG_S3C2412_DMA=y
CONFIG_S3C2412_PM=y
#
# S3C2412 Machines
#
CONFIG_MACH_SMDK2413=y
CONFIG_MACH_S3C2413=y
CONFIG_MACH_VSTMS=y
CONFIG_CPU_S3C2440=y
CONFIG_S3C2440_DMA=y
#
# S3C2440 Machines
#
CONFIG_MACH_ANUBIS=y
CONFIG_MACH_OSIRIS=y
CONFIG_MACH_RX3715=y
CONFIG_ARCH_S3C2440=y
CONFIG_MACH_NEXCODER_2440=y
CONFIG_SMDK2440_CPU2440=y
CONFIG_CPU_S3C2442=y
#
# S3C2410 Boot
# S3C2442 Machines
#
# CONFIG_S3C2410_BOOT_WATCHDOG is not set
# CONFIG_S3C2410_BOOT_ERROR_RESET is not set
CONFIG_SMDK2440_CPU2442=y
CONFIG_CPU_S3C2443=y
#
# S3C2410 Setup
# S3C2443 Machines
#
CONFIG_S3C2410_DMA=y
# CONFIG_S3C2410_DMA_DEBUG is not set
# CONFIG_S3C2410_PM_DEBUG is not set
# CONFIG_S3C2410_PM_CHECK is not set
CONFIG_PM_SIMTEC=y
CONFIG_S3C2410_LOWLEVEL_UART_PORT=0
CONFIG_MACH_SMDK2443=y
#
# Processor Type
......@@ -196,6 +221,7 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
# CONFIG_OUTER_CACHE is not set
#
# Bus support
......@@ -303,6 +329,7 @@ CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
......@@ -385,6 +412,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
......@@ -530,6 +558,11 @@ CONFIG_BLK_DEV_IDE_BAST=y
# CONFIG_SCSI is not set
# CONFIG_SCSI_NETLINK is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
......@@ -682,7 +715,7 @@ CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_DIGIEPCA is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_ISI is not set
# CONFIG_MOXA_SMARTIO_NEW is not set
# CONFIG_SYNCLINKMP is not set
# CONFIG_N_HDLC is not set
# CONFIG_RISCOM8 is not set
......@@ -700,13 +733,14 @@ CONFIG_SERIAL_8250_NR_UARTS=8
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
# CONFIG_SERIAL_8250_FOURPORT is not set
# CONFIG_SERIAL_8250_ACCENT is not set
# CONFIG_SERIAL_8250_BOCA is not set
# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
# CONFIG_SERIAL_8250_HUB6 is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
......@@ -755,10 +789,6 @@ CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_RAW_DRIVER is not set
#
......@@ -863,6 +893,7 @@ CONFIG_SENSORS_LM85=m
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
......@@ -870,6 +901,7 @@ CONFIG_SENSORS_LM85=m
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
......@@ -951,6 +983,11 @@ CONFIG_FONT_8x16=y
#
# CONFIG_SOUND is not set
#
# HID Devices
#
CONFIG_HID=y
#
# USB support
#
......@@ -1028,6 +1065,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET_MII is not set
# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
......@@ -1179,9 +1217,6 @@ CONFIG_RAMFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS_FS=y
CONFIG_JFFS_FS_VERBOSE=0
# CONFIG_JFFS_PROC_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
......@@ -1191,7 +1226,7 @@ CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
......@@ -1284,6 +1319,11 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
......@@ -1296,6 +1336,8 @@ CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_DETECT_SOFTLOCKUP=y
......@@ -1311,12 +1353,10 @@ CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
......@@ -1339,6 +1379,7 @@ CONFIG_DEBUG_S3C2410_UART=0
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
......@@ -1346,3 +1387,4 @@ CONFIG_CRC32=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_IOMAP_COPY=y
arch/arm/kernel/crunch.c
View file @ f69eda00
......@@ -75,6 +75,7 @@ static struct notifier_block crunch_notifier_block = {
static int __init crunch_init(void)
{
thread_register_notifier(&crunch_notifier_block);
elf_hwcap |= HWCAP_CRUNCH;
return 0;
}
......
arch/arm/kernel/setup.c
View file @ f69eda00
......@@ -88,6 +88,9 @@ struct cpu_user_fns cpu_user;
#ifdef MULTI_CACHE
struct cpu_cache_fns cpu_cache;
#endif
#ifdef CONFIG_OUTER_CACHE
struct outer_cache_fns outer_cache;
#endif
struct stack {
u32 irq[3];
......
arch/arm/mach-at91rm9200/Kconfig → arch/arm/mach-at91/Kconfig
View file @ f69eda00
......@@ -9,11 +9,14 @@ config ARCH_AT91RM9200
bool "AT91RM9200"
config ARCH_AT91SAM9260
bool "AT91SAM9260"
bool "AT91SAM9260 or AT91SAM9XE"
config ARCH_AT91SAM9261
bool "AT91SAM9261"
config ARCH_AT91SAM9263
bool "AT91SAM9263"
endchoice
# ----------------------------------------------------------
......@@ -90,13 +93,22 @@ endif
if ARCH_AT91SAM9260
comment "AT91SAM9260 Board Type"
comment "AT91SAM9260 Variants"
config ARCH_AT91SAM9260_SAM9XE
bool "AT91SAM9XE"
depends on ARCH_AT91SAM9260
help
Select this if you are using Atmel's AT91SAM9XE System-on-Chip.
They are basicaly AT91SAM9260s with various sizes of embedded Flash.
comment "AT91SAM9260 / AT91SAM9XE Board Type"
config MACH_AT91SAM9260EK
bool "Atmel AT91SAM9260-EK Evaluation Kit"
bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
depends on ARCH_AT91SAM9260
help
Select this if you are using Atmel's AT91SAM9260-EK Evaluation Kit.
Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
endif
......@@ -118,17 +130,32 @@ endif
# ----------------------------------------------------------
if ARCH_AT91SAM9263
comment "AT91SAM9263 Board Type"
config MACH_AT91SAM9263EK
bool "Atmel AT91SAM9263-EK Evaluation Kit"
depends on ARCH_AT91SAM9263
help
Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
endif
# ----------------------------------------------------------
comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD
bool "Enable DataFlash Card support"
depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK)
depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK)
help
Enable support for the DataFlash card.
config MTD_NAND_AT91_BUSWIDTH_16
bool "Enable 16-bit data bus interface to NAND flash"
depends on (MACH_AT91SAM9261EK || MACH_AT91SAM9260EK)
depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK)
help
On AT91SAM926x boards both types of NAND flash can be present
(8 and 16 bit data bus width).
......
arch/arm/mach-at91rm9200/Makefile → arch/arm/mach-at91/Makefile
View file @ f69eda00
......@@ -13,6 +13,7 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
# AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
......@@ -31,6 +32,9 @@ obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
# AT91SAM9261 board-specific support
obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
# AT91SAM9263 board-specific support
obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
# LEDs support
led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
......
arch/arm/mach-at91rm9200/at91rm9200.c → arch/arm/mach-at91/at91rm9200.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91rm9200.c
* arch/arm/mach-at91/at91rm9200.c
*
* Copyright (C) 2005 SAN People
*
......@@ -117,6 +117,36 @@ static struct clk pioD_clk = {
.pmc_mask = 1 << AT91RM9200_ID_PIOD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
.name = "tc3_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
.name = "tc4_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
.name = "tc5_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
......@@ -132,7 +162,12 @@ static struct clk *periph_clocks[] __initdata = {
&twi_clk,
&spi_clk,
// ssc 0 .. ssc2
// tc0 .. tc5
&tc0_clk,
&tc1_clk,
&tc2_clk,
&tc3_clk,
&tc4_clk,
&tc5_clk,
&ohci_clk,
&ether_clk,
// irq0 .. irq6
......
arch/arm/mach-at91rm9200/at91rm9200_devices.c → arch/arm/mach-at91/at91rm9200_devices.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91rm9200_devices.c
* arch/arm/mach-at91/at91rm9200_devices.c
*
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
* Copyright (C) 2005 David Brownell
......@@ -315,7 +315,7 @@ static struct platform_device at91rm9200_mmc_device = {
.num_resources = ARRAY_SIZE(mmc_resources),
};
void __init at91_add_device_mmc(struct at91_mmc_data *data)
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
if (!data)
return;
......@@ -361,7 +361,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
platform_device_register(&at91rm9200_mmc_device);
}
#else
void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
#endif
......@@ -594,6 +594,10 @@ u8 at91_leds_timer;
void __init at91_init_leds(u8 cpu_led, u8 timer_led)
{
/* Enable GPIO to access the LEDs */
at91_set_gpio_output(cpu_led, 1);
at91_set_gpio_output(timer_led, 1);
at91_leds_cpu = cpu_led;
at91_leds_timer = timer_led;
}
......
arch/arm/mach-at91rm9200/at91rm9200_time.c → arch/arm/mach-at91/at91rm9200_time.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/at91rm9200_time.c
* linux/arch/arm/mach-at91/at91rm9200_time.c
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
......
arch/arm/mach-at91rm9200/at91sam9260.c → arch/arm/mach-at91/at91sam9260.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91sam9260.c
* arch/arm/mach-at91/at91sam9260.c
*
* Copyright (C) 2006 SAN People
*
......@@ -14,6 +14,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/cpu.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
......@@ -27,7 +28,11 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
}
};
static struct map_desc at91sam9260_sram_desc[] __initdata = {
{
.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
.length = AT91SAM9260_SRAM0_SIZE,
......@@ -37,7 +42,14 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
.pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
.length = AT91SAM9260_SRAM1_SIZE,
.type = MT_DEVICE,
},
}
};
static struct map_desc at91sam9xe_sram_desc[] __initdata = {
{
.pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
.type = MT_DEVICE,
}
};
/* --------------------------------------------------------------------
......@@ -107,13 +119,28 @@ static struct clk spi1_clk = {
.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9260_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ether_clk = {
.name = "ether_clk",
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
......@@ -137,6 +164,21 @@ static struct clk usart5_clk = {
.pmc_mask = 1 << AT91SAM9260_ID_US5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
.name = "tc3_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
.name = "tc4_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
.name = "tc5_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
......@@ -152,14 +194,18 @@ static struct clk *periph_clocks[] __initdata = {
&spi0_clk,
&spi1_clk,
// ssc
// tc0 .. tc2
&tc0_clk,
&tc1_clk,
&tc2_clk,
&ohci_clk,
&ether_clk,
&macb_clk,
&isi_clk,
&usart3_clk,
&usart4_clk,
&usart5_clk,
// tc3 .. tc5
&tc3_clk,
&tc4_clk,
&tc5_clk,
// irq0 .. irq2
};
......@@ -213,7 +259,7 @@ static struct at91_gpio_bank at91sam9260_gpio[] = {
static void at91sam9260_reset(void)
{
at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
......@@ -221,11 +267,37 @@ static void at91sam9260_reset(void)
* AT91SAM9260 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9xe_initialize(void)
{
unsigned long cidr, sram_size;
cidr = at91_sys_read(AT91_DBGU_CIDR);
switch (cidr & AT91_CIDR_SRAMSIZ) {
case AT91_CIDR_SRAMSIZ_32K:
sram_size = 2 * SZ_16K;
break;
case AT91_CIDR_SRAMSIZ_16K:
default:
sram_size = SZ_16K;
}
at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
at91sam9xe_sram_desc->length = sram_size;
iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
}
void __init at91sam9260_initialize(unsigned long main_clock)
{
/* Map peripherals */
iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
if (cpu_is_at91sam9xe())
at91sam9xe_initialize();
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
at91_arch_reset = at91sam9260_reset;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
......
arch/arm/mach-at91rm9200/at91sam9260_devices.c → arch/arm/mach-at91/at91sam9260_devices.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91sam9260_devices.c
* arch/arm/mach-at91/at91sam9260_devices.c
*
* Copyright (C) 2006 Atmel
*
......@@ -128,7 +128,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
static u64 eth_dmamask = 0xffffffffUL;
static struct eth_platform_data eth_data;
static struct at91_eth_data eth_data;
static struct resource eth_resources[] = {
[0] = {
......@@ -155,7 +155,7 @@ static struct platform_device at91sam9260_eth_device = {
.num_resources = ARRAY_SIZE(eth_resources),
};
void __init at91_add_device_eth(struct eth_platform_data *data)
void __init at91_add_device_eth(struct at91_eth_data *data)
{
if (!data)
return;
......@@ -192,7 +192,7 @@ void __init at91_add_device_eth(struct eth_platform_data *data)
platform_device_register(&at91sam9260_eth_device);
}
#else
void __init at91_add_device_eth(struct eth_platform_data *data) {}
void __init at91_add_device_eth(struct at91_eth_data *data) {}
#endif
......@@ -229,7 +229,7 @@ static struct platform_device at91sam9260_mmc_device = {
.num_resources = ARRAY_SIZE(mmc_resources),
};
void __init at91_add_device_mmc(struct at91_mmc_data *data)
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
if (!data)
return;
......@@ -275,7 +275,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
platform_device_register(&at91sam9260_mmc_device);
}
#else
void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
#endif
......@@ -515,6 +515,10 @@ u8 at91_leds_timer;
void __init at91_init_leds(u8 cpu_led, u8 timer_led)
{
/* Enable GPIO to access the LEDs */
at91_set_gpio_output(cpu_led, 1);
at91_set_gpio_output(timer_led, 1);
at91_leds_cpu = cpu_led;
at91_leds_timer = timer_led;
}
......
arch/arm/mach-at91rm9200/at91sam9261.c → arch/arm/mach-at91/at91sam9261.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91sam9261.c
* arch/arm/mach-at91/at91sam9261.c
*
* Copyright (C) 2005 SAN People
*
......@@ -97,6 +97,21 @@ static struct clk spi1_clk = {
.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91SAM9261_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91SAM9261_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91SAM9261_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9261_ID_UHP,
......@@ -121,7 +136,9 @@ static struct clk *periph_clocks[] __initdata = {
&spi0_clk,
&spi1_clk,
// ssc 0 .. ssc2
// tc0 .. tc2
&tc0_clk,
&tc1_clk,
&tc2_clk,
&ohci_clk,
&lcdc_clk,
// irq0 .. irq2
......@@ -208,7 +225,7 @@ static struct at91_gpio_bank at91sam9261_gpio[] = {
static void at91sam9261_reset(void)
{
at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
......
arch/arm/mach-at91rm9200/at91sam9261_devices.c → arch/arm/mach-at91/at91sam9261_devices.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/at91sam9261_devices.c
* arch/arm/mach-at91/at91sam9261_devices.c
*
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
* Copyright (C) 2005 David Brownell
......@@ -159,7 +159,7 @@ static struct platform_device at91sam9261_mmc_device = {
.num_resources = ARRAY_SIZE(mmc_resources),
};
void __init at91_add_device_mmc(struct at91_mmc_data *data)
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
if (!data)
return;
......@@ -192,7 +192,7 @@ void __init at91_add_device_mmc(struct at91_mmc_data *data)
platform_device_register(&at91sam9261_mmc_device);
}
#else
void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
#endif
......@@ -513,6 +513,10 @@ u8 at91_leds_timer;
void __init at91_init_leds(u8 cpu_led, u8 timer_led)
{
/* Enable GPIO to access the LEDs */
at91_set_gpio_output(cpu_led, 1);
at91_set_gpio_output(timer_led, 1);
at91_leds_cpu = cpu_led;
at91_leds_timer = timer_led;
}
......
arch/arm/mach-at91/at91sam9263.c 0 → 100644
View file @ f69eda00
/*
* arch/arm/mach-at91/at91sam9263.c
*
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/module.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9263_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
.length = AT91SAM9263_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
.length = AT91SAM9263_SRAM1_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
.name = "pioCDE_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioCDE_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc0_clk,
&mmc1_clk,
// can
&twi_clk,
&spi0_clk,
&spi1_clk,
// ssc0 .. ssc1
// ac97
&tcb_clk,
// pwmc
&macb_clk,
// 2dge
&udc_clk,
&isi_clk,
&lcdc_clk,
// dma
&ohci_clk,
// irq0 .. irq1
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91sam9263_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOE,
.clock = &pioCDE_clk,
}
};
static void at91sam9263_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9263_initialize(unsigned long main_clock)
{
/* Map peripherals */
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
at91_arch_reset = at91sam9263_reset;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9263_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
0, /* Parallel IO Controller A */
0, /* Parallel IO Controller B */
0, /* Parallel IO Controller C, D and E */
0,
0,
6, /* USART 0 */
6, /* USART 1 */
6, /* USART 2 */
0, /* Multimedia Card Interface 0 */
0, /* Multimedia Card Interface 1 */
4, /* CAN */
0, /* Two-Wire Interface */
6, /* Serial Peripheral Interface 0 */
6, /* Serial Peripheral Interface 1 */
5, /* Serial Synchronous Controller 0 */
5, /* Serial Synchronous Controller 1 */
6, /* AC97 Controller */
0, /* Timer Counter 0, 1 and 2 */
0, /* Pulse Width Modulation Controller */
3, /* Ethernet */
0,
0, /* 2D Graphic Engine */
3, /* USB Device Port */
0, /* Image Sensor Interface */
3, /* LDC Controller */
0, /* DMA Controller */
0,
3, /* USB Host port */
0, /* Advanced Interrupt Controller (IRQ0) */
0, /* Advanced Interrupt Controller (IRQ1) */
};
void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9263_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
arch/arm/mach-at91/at91sam9263_devices.c 0 → 100644
View file @ f69eda00
This diff is collapsed.
arch/arm/mach-at91rm9200/at91sam926x_time.c → arch/arm/mach-at91/at91sam926x_time.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/at91sam926x_time.c
* linux/arch/arm/mach-at91/at91sam926x_time.c
*
* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
......@@ -30,7 +30,6 @@
* Returns number of microseconds since last timer interrupt. Note that interrupts
* will have been disabled by do_gettimeofday()
* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
* 'tick' is usecs per jiffy (linux/timex.h).
*/
static unsigned long at91sam926x_gettimeoffset(void)
{
......@@ -39,7 +38,7 @@ static unsigned long at91sam926x_gettimeoffset(void)
elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
return (unsigned long)(elapsed * 1000000) / LATCH;
return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
}
/*
......
arch/arm/mach-at91rm9200/board-1arm.c → arch/arm/mach-at91/board-1arm.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-1arm.c
* linux/arch/arm/mach-at91/board-1arm.c
*
* Copyright (C) 2005 SAN People
*
......
arch/arm/mach-at91rm9200/board-carmeva.c → arch/arm/mach-at91/board-carmeva.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-carmeva.c
* linux/arch/arm/mach-at91/board-carmeva.c
*
* Copyright (c) 2005 Peer Georgi
* Conitec Datasystems
......@@ -134,7 +134,7 @@ static void __init carmeva_board_init(void)
/* Compact Flash */
// at91_add_device_cf(&carmeva_cf_data);
/* MMC */
at91_add_device_mmc(&carmeva_mmc_data);
at91_add_device_mmc(0, &carmeva_mmc_data);
}
MACHINE_START(CARMEVA, "Carmeva")
......
arch/arm/mach-at91rm9200/board-csb337.c → arch/arm/mach-at91/board-csb337.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-csb337.c
* linux/arch/arm/mach-at91/board-csb337.c
*
* Copyright (C) 2005 SAN People
*
......@@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/mtd/physmap.h>
#include <asm/hardware.h>
#include <asm/setup.h>
......@@ -112,6 +113,42 @@ static struct spi_board_info csb337_spi_devices[] = {
},
};
#define CSB_FLASH_BASE AT91_CHIPSELECT_0
#define CSB_FLASH_SIZE 0x800000
static struct mtd_partition csb_flash_partitions[] = {
{
.name = "uMON flash",
.offset = 0,
.size = MTDPART_SIZ_FULL,
.mask_flags = MTD_WRITEABLE, /* read only */
}
};
static struct physmap_flash_data csb_flash_data = {
.width = 2,
.parts = csb_flash_partitions,
.nr_parts = ARRAY_SIZE(csb_flash_partitions),
};
static struct resource csb_flash_resources[] = {
{
.start = CSB_FLASH_BASE,
.end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device csb_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &csb_flash_data,
},
.resource = csb_flash_resources,
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
static void __init csb337_board_init(void)
{
/* Serial */
......@@ -130,7 +167,9 @@ static void __init csb337_board_init(void)
/* SPI */
at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
/* MMC */
at91_add_device_mmc(&csb337_mmc_data);
at91_add_device_mmc(0, &csb337_mmc_data);
/* NOR flash */
platform_device_register(&csb_flash);
}
MACHINE_START(CSB337, "Cogent CSB337")
......
arch/arm/mach-at91rm9200/board-csb637.c → arch/arm/mach-at91/board-csb637.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-csb637.c
* linux/arch/arm/mach-at91/board-csb637.c
*
* Copyright (C) 2005 SAN People
*
......@@ -23,6 +23,7 @@
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <asm/hardware.h>
#include <asm/setup.h>
......@@ -81,6 +82,42 @@ static struct at91_udc_data __initdata csb637_udc_data = {
.pullup_pin = AT91_PIN_PB1,
};
#define CSB_FLASH_BASE AT91_CHIPSELECT_0
#define CSB_FLASH_SIZE 0x1000000
static struct mtd_partition csb_flash_partitions[] = {
{
.name = "uMON flash",
.offset = 0,
.size = MTDPART_SIZ_FULL,
.mask_flags = MTD_WRITEABLE, /* read only */
}
};
static struct physmap_flash_data csb_flash_data = {
.width = 2,
.parts = csb_flash_partitions,
.nr_parts = ARRAY_SIZE(csb_flash_partitions),
};
static struct resource csb_flash_resources[] = {
{
.start = CSB_FLASH_BASE,
.end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device csb_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &csb_flash_data,
},
.resource = csb_flash_resources,
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
static void __init csb637_board_init(void)
{
/* Serial */
......@@ -95,6 +132,8 @@ static void __init csb637_board_init(void)
at91_add_device_i2c();
/* SPI */
at91_add_device_spi(NULL, 0);
/* NOR flash */
platform_device_register(&csb_flash);
}
MACHINE_START(CSB637, "Cogent CSB637")
......
arch/arm/mach-at91rm9200/board-dk.c → arch/arm/mach-at91/board-dk.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-dk.c
* linux/arch/arm/mach-at91/board-dk.c
*
* Copyright (C) 2005 SAN People
*
......@@ -194,7 +194,7 @@ static void __init dk_board_init(void)
#else
/* MMC */
at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
at91_add_device_mmc(&dk_mmc_data);
at91_add_device_mmc(0, &dk_mmc_data);
#endif
/* NAND */
at91_add_device_nand(&dk_nand_data);
......
arch/arm/mach-at91rm9200/board-eb9200.c → arch/arm/mach-at91/board-eb9200.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-eb9200.c
* linux/arch/arm/mach-at91/board-eb9200.c
*
* Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest
* by Andrew Patrikalakis
......@@ -109,7 +109,7 @@ static void __init eb9200_board_init(void)
at91_add_device_spi(NULL, 0);
/* MMC */
/* only supports 1 or 4 bit interface, not wired through to SPI */
at91_add_device_mmc(&eb9200_mmc_data);
at91_add_device_mmc(0, &eb9200_mmc_data);
}
MACHINE_START(ATEB9200, "Embest ATEB9200")
......
arch/arm/mach-at91rm9200/board-ek.c → arch/arm/mach-at91/board-ek.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-ek.c
* linux/arch/arm/mach-at91/board-ek.c
*
* Copyright (C) 2005 SAN People
*
......@@ -154,7 +154,7 @@ static void __init ek_board_init(void)
#else
/* MMC */
at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
at91_add_device_mmc(&ek_mmc_data);
at91_add_device_mmc(0, &ek_mmc_data);
#endif
/* NOR Flash */
platform_device_register(&ek_flash);
......
arch/arm/mach-at91rm9200/board-kafa.c → arch/arm/mach-at91/board-kafa.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-kafa.c
* linux/arch/arm/mach-at91/board-kafa.c
*
* Copyright (C) 2006 Sperry-Sun
*
......
arch/arm/mach-at91rm9200/board-kb9202.c → arch/arm/mach-at91/board-kb9202.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-kb9202.c
* linux/arch/arm/mach-at91/board-kb9202.c
*
* Copyright (c) 2005 kb_admin
* KwikByte, Inc.
......@@ -122,7 +122,7 @@ static void __init kb9202_board_init(void)
/* USB Device */
at91_add_device_udc(&kb9202_udc_data);
/* MMC */
at91_add_device_mmc(&kb9202_mmc_data);
at91_add_device_mmc(0, &kb9202_mmc_data);
/* I2C */
at91_add_device_i2c();
/* SPI */
......
arch/arm/mach-at91rm9200/board-sam9260ek.c → arch/arm/mach-at91/board-sam9260ek.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-ek.c
* linux/arch/arm/mach-at91/board-sam9260ek.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2006 Atmel
......@@ -118,7 +118,7 @@ static struct spi_board_info ek_spi_devices[] = {
/*
* MACB Ethernet device
*/
static struct __initdata eth_platform_data ek_macb_data = {
static struct __initdata at91_eth_data ek_macb_data = {
.phy_irq_pin = AT91_PIN_PA7,
.is_rmii = 1,
};
......@@ -187,7 +187,7 @@ static void __init ek_board_init(void)
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* MMC */
at91_add_device_mmc(&ek_mmc_data);
at91_add_device_mmc(0, &ek_mmc_data);
}
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
......
arch/arm/mach-at91rm9200/board-sam9261ek.c → arch/arm/mach-at91/board-sam9261ek.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/board-ek.c
* linux/arch/arm/mach-at91/board-sam9261ek.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2006 Atmel
......@@ -243,7 +243,7 @@ static void __init ek_board_init(void)
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
#else
/* MMC */
at91_add_device_mmc(&ek_mmc_data);
at91_add_device_mmc(0, &ek_mmc_data);
#endif
}
......
arch/arm/mach-at91/board-sam9263ek.c 0 → 100644
View file @ f69eda00
/*
* linux/arch/arm/mach-at91/board-sam9263ek.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam926x_mc.h>
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 2 = USART0 .. USART2
* 3 = DBGU
*/
static struct at91_uart_config __initdata ek_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 3, 0, -1, -1, } /* ttyS0, ..., ttyS3 */
};
static void __init ek_map_io(void)
{
/* Initialize processor: 16.367 MHz crystal */
at91sam9263_initialize(16367660);
/* Setup the serial ports and console */
at91_init_serial(&ek_uart_config);
}
static void __init ek_init_irq(void)
{
at91sam9263_init_interrupts(NULL);
}
/*
* USB Host port
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
.vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 },
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PA25,
.pullup_pin = 0, /* pull-up driven by UDC */
};
/*
* SPI devices.
*/
static struct spi_board_info ek_spi_devices[] = {
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
{ /* DataFlash card */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
};
/*
* MCI (SD/MMC)
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.wire4 = 1,
.det_pin = AT91_PIN_PE18,
.wp_pin = AT91_PIN_PE19,
// .vcc_pin = ... not connected
};
/*
* NAND flash
*/
static struct mtd_partition __initdata ek_nand_partition[] = {
{
.name = "Partition 1",
.offset = 0,
.size = 64 * 1024 * 1024,
},
{
.name = "Partition 2",
.offset = 64 * 1024 * 1024,
.size = MTDPART_SIZ_FULL,
},
};
static struct mtd_partition *nand_partitions(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(ek_nand_partition);
return ek_nand_partition;
}
static struct at91_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
// .det_pin = ... not connected
.rdy_pin = AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
.partition_info = nand_partitions,
#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
.bus_width_16 = 1,
#else
.bus_width_16 = 0,
#endif
};
static void __init ek_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* USB Host */
at91_add_device_usbh(&ek_usbh_data);
/* USB Device */
at91_add_device_udc(&ek_udc_data);
/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* MMC */
at91_add_device_mmc(1, &ek_mmc_data);
/* NAND */
at91_add_device_nand(&ek_nand_data);
}
MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
/* Maintainer: Atmel */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = ek_map_io,
.init_irq = ek_init_irq,
.init_machine = ek_board_init,
MACHINE_END
arch/arm/mach-at91rm9200/clock.c → arch/arm/mach-at91/clock.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/clock.c
* linux/arch/arm/mach-at91/clock.c
*
* Copyright (C) 2005 David Brownell
* Copyright (C) 2005 Ivan Kokshaysky
......@@ -525,27 +525,6 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
return 0;
}
/*
* Several unused clocks may be active. Turn them off.
*/
static void __init at91_periphclk_reset(void)
{
unsigned long reg;
struct clk *clk;
reg = at91_sys_read(AT91_PMC_PCSR);
list_for_each_entry(clk, &clocks, node) {
if (clk->mode != pmc_periph_mode)
continue;
if (clk->users > 0)
reg &= ~clk->pmc_mask;
}
at91_sys_write(AT91_PMC_PCDR, reg);
}
static struct clk *const standard_pmc_clocks[] __initdata = {
/* four primary clocks */
&clk32k,
......@@ -586,7 +565,7 @@ int __init at91_clock_init(unsigned long main_clock)
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
/*
* USB clock init: choose 48 MHz PLLB value, turn all clocks off,
* USB clock init: choose 48 MHz PLLB value,
* disable 48MHz clock during usb peripheral suspend.
*
* REVISIT: assumes MCK doesn't derive from PLLB!
......@@ -596,16 +575,10 @@ int __init at91_clock_init(unsigned long main_clock)
if (cpu_is_at91rm9200()) {
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260()) {
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
} else if (cpu_is_at91sam9261()) {
uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
}
at91_sys_write(AT91_CKGR_PLLBR, 0);
......@@ -634,11 +607,34 @@ int __init at91_clock_init(unsigned long main_clock)
(unsigned) main_clock / 1000000,
((unsigned) main_clock % 1000000) / 1000);
/* disable all programmable clocks */
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
return 0;
}
/*
* Several unused clocks may be active. Turn them off.
*/
static int __init at91_clock_reset(void)
{
unsigned long pcdr = 0;
unsigned long scdr = 0;
struct clk *clk;
list_for_each_entry(clk, &clocks, node) {
if (clk->users > 0)
continue;
if (clk->mode == pmc_periph_mode)
pcdr |= clk->pmc_mask;
if (clk->mode == pmc_sys_mode)
scdr |= clk->pmc_mask;
pr_debug("Clocks: disable unused %s\n", clk->name);
}
/* disable all other unused peripheral clocks */
at91_periphclk_reset();
at91_sys_write(AT91_PMC_PCDR, pcdr);
at91_sys_write(AT91_PMC_SCDR, scdr);
return 0;
}
late_initcall(at91_clock_reset);
arch/arm/mach-at91rm9200/clock.h → arch/arm/mach-at91/clock.h
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/clock.h
* linux/arch/arm/mach-at91/clock.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......
arch/arm/mach-at91rm9200/generic.h → arch/arm/mach-at91/generic.h
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/generic.h
* linux/arch/arm/mach-at91/generic.h
*
* Copyright (C) 2005 David Brownell
*
......@@ -12,11 +12,13 @@
extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
extern void __init at91sam9260_initialize(unsigned long main_clock);
extern void __init at91sam9261_initialize(unsigned long main_clock);
extern void __init at91sam9263_initialize(unsigned long main_clock);
/* Interrupts */
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[]);
/* Timer */
......
arch/arm/mach-at91rm9200/gpio.c → arch/arm/mach-at91/gpio.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/gpio.c
* linux/arch/arm/mach-at91/gpio.c
*
* Copyright (C) 2005 HP Labs
*
......
arch/arm/mach-at91rm9200/irq.c → arch/arm/mach-at91/irq.c
View file @ f69eda00
/*
* linux/arch/arm/mach-at91rm9200/irq.c
* linux/arch/arm/mach-at91/irq.c
*
* Copyright (C) 2004 SAN People
* Copyright (C) 2004 ATMEL
......
arch/arm/mach-at91rm9200/leds.c → arch/arm/mach-at91/leds.c
View file @ f69eda00
......@@ -86,10 +86,6 @@ static int __init leds_init(void)
if (!at91_leds_timer || !at91_leds_cpu)
return -ENODEV;
/* Enable PIO to access the LEDs */
at91_set_gpio_output(at91_leds_timer, 1);
at91_set_gpio_output(at91_leds_cpu, 1);
leds_event = at91_leds_event;
leds_event(led_start);
......
arch/arm/mach-at91rm9200/pm.c → arch/arm/mach-at91/pm.c
View file @ f69eda00
/*
* arch/arm/mach-at91rm9200/pm.c
* arch/arm/mach-at91/pm.c
* AT91 Power Management
*
* Copyright (C) 2005 David Brownell
......@@ -80,6 +80,8 @@ static int at91_pm_verify_clocks(void)
#warning "Check SAM9260 USB clocks"
} else if (cpu_is_at91sam9261()) {
#warning "Check SAM9261 USB clocks"
} else if (cpu_is_at91sam9263()) {
#warning "Check SAM9263 USB clocks"
}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
......
arch/arm/mach-ep93xx/clock.c
View file @ f69eda00
......@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <asm/div64.h>
#include <asm/hardware.h>
......@@ -124,7 +125,7 @@ static unsigned long calc_pll_rate(u32 config_word)
return (unsigned long)rate;
}
void ep93xx_clock_init(void)
static int __init ep93xx_clock_init(void)
{
u32 value;
......@@ -153,4 +154,7 @@ void ep93xx_clock_init(void)
printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
clk_f.rate / 1000000, clk_h.rate / 1000000,
clk_p.rate / 1000000);
return 0;
}
arch_initcall(ep93xx_clock_init);
arch/arm/mach-ep93xx/core.c
View file @ f69eda00
......@@ -152,22 +152,30 @@ struct sys_timer ep93xx_timer = {
/*************************************************************************
* GPIO handling for EP93xx
*************************************************************************/
static unsigned char gpio_int_enable[2];
static unsigned char gpio_int_type1[2];
static unsigned char gpio_int_type2[2];
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static void update_gpio_ab_int_params(int port)
static void update_gpio_int_params(int abf)
{
if (port == 0) {
if (abf == 0) {
__raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
__raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
__raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
__raw_writeb(gpio_int_enable[0], EP93XX_GPIO_A_INT_ENABLE);
} else if (port == 1) {
__raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE);
} else if (abf == 1) {
__raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
__raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
__raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
__raw_writeb(gpio_int_enable[1], EP93XX_GPIO_B_INT_ENABLE);
__raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE);
} else if (abf == 2) {
__raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE);
__raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2);
__raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1);
__raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE);
} else {
BUG();
}
}
......@@ -192,8 +200,13 @@ void gpio_line_config(int line, int direction)
local_irq_save(flags);
if (direction == GPIO_OUT) {
if (line >= 0 && line < 16) {
gpio_int_enable[line >> 3] &= ~(1 << (line & 7));
update_gpio_ab_int_params(line >> 3);
/* Port A/B. */
gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
update_gpio_int_params(line >> 3);
} else if (line >= 40 && line < 48) {
/* Port F. */
gpio_int_unmasked[2] &= ~(1 << (line & 7));
update_gpio_int_params(2);
}
v = __raw_readb(data_direction_register);
......@@ -244,8 +257,7 @@ EXPORT_SYMBOL(gpio_line_set);
/*************************************************************************
* EP93xx IRQ handling
*************************************************************************/
static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
struct irq_desc *desc)
static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned char status;
int i;
......@@ -267,37 +279,46 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
}
}
static void ep93xx_gpio_ab_irq_mask_ack(unsigned int irq)
static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int gpio_irq = IRQ_EP93XX_GPIO(16) + (((irq + 1) & 7) ^ 4);
desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
}
static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
{
int line = irq - IRQ_EP93XX_GPIO(0);
int port = line >> 3;
gpio_int_enable[port] &= ~(1 << (line & 7));
update_gpio_ab_int_params(port);
gpio_int_unmasked[port] &= ~(1 << (line & 7));
update_gpio_int_params(port);
if (line >> 3) {
__raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
} else {
if (port == 0) {
__raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
} else if (port == 1) {
__raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
} else if (port == 2) {
__raw_writel(1 << (line & 7), EP93XX_GPIO_F_INT_ACK);
}
}
static void ep93xx_gpio_ab_irq_mask(unsigned int irq)
static void ep93xx_gpio_irq_mask(unsigned int irq)
{
int line = irq - IRQ_EP93XX_GPIO(0);
int port = line >> 3;
gpio_int_enable[port] &= ~(1 << (line & 7));
update_gpio_ab_int_params(port);
gpio_int_unmasked[port] &= ~(1 << (line & 7));
update_gpio_int_params(port);
}
static void ep93xx_gpio_ab_irq_unmask(unsigned int irq)
static void ep93xx_gpio_irq_unmask(unsigned int irq)
{
int line = irq - IRQ_EP93XX_GPIO(0);
int port = line >> 3;
gpio_int_enable[port] |= 1 << (line & 7);
update_gpio_ab_int_params(port);
gpio_int_unmasked[port] |= 1 << (line & 7);
update_gpio_int_params(port);
}
......@@ -306,40 +327,51 @@ static void ep93xx_gpio_ab_irq_unmask(unsigned int irq)
* edge (1) triggered, while gpio_int_type2 controls whether it
* triggers on low/falling (0) or high/rising (1).
*/
static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
{
int port;
int line;
line = irq - IRQ_EP93XX_GPIO(0);
gpio_line_config(line, GPIO_IN);
if (line >= 0 && line < 16) {
gpio_line_config(line, GPIO_IN);
} else {
gpio_line_config(EP93XX_GPIO_LINE_F(line), GPIO_IN);
}
port = line >> 3;
line &= 7;
if (type & IRQT_RISING) {
gpio_int_enabled[port] |= 1 << line;
gpio_int_type1[port] |= 1 << line;
gpio_int_type2[port] |= 1 << line;
} else if (type & IRQT_FALLING) {
gpio_int_enabled[port] |= 1 << line;
gpio_int_type1[port] |= 1 << line;
gpio_int_type2[port] &= ~(1 << line);
} else if (type & IRQT_HIGH) {
gpio_int_enabled[port] |= 1 << line;
gpio_int_type1[port] &= ~(1 << line);
gpio_int_type2[port] |= 1 << line;
} else if (type & IRQT_LOW) {
gpio_int_enabled[port] |= 1 << line;
gpio_int_type1[port] &= ~(1 << line);
gpio_int_type2[port] &= ~(1 << line);
} else {
gpio_int_enabled[port] &= ~(1 << line);
}
update_gpio_ab_int_params(port);
update_gpio_int_params(port);
return 0;
}
static struct irq_chip ep93xx_gpio_ab_irq_chip = {
.ack = ep93xx_gpio_ab_irq_mask_ack,
.mask = ep93xx_gpio_ab_irq_mask,
.unmask = ep93xx_gpio_ab_irq_unmask,
.set_type = ep93xx_gpio_ab_irq_type,
static struct irq_chip ep93xx_gpio_irq_chip = {
.name = "GPIO",
.ack = ep93xx_gpio_irq_mask_ack,
.mask = ep93xx_gpio_irq_mask,
.unmask = ep93xx_gpio_irq_unmask,
.set_type = ep93xx_gpio_irq_type,
};
......@@ -350,12 +382,21 @@ void __init ep93xx_init_irq(void)
vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
for (irq = IRQ_EP93XX_GPIO(0); irq <= IRQ_EP93XX_GPIO(23); irq++) {
set_irq_chip(irq, &ep93xx_gpio_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
}
......@@ -461,8 +502,6 @@ void __init ep93xx_init_devices(void)
{
unsigned int v;
ep93xx_clock_init();
/*
* Disallow access to MaverickCrunch initially.
*/
......@@ -477,8 +516,4 @@ void __init ep93xx_init_devices(void)
platform_device_register(&ep93xx_rtc_device);
platform_device_register(&ep93xx_ohci_device);
#ifdef CONFIG_CRUNCH
elf_hwcap |= HWCAP_CRUNCH;
#endif
}
arch/arm/mach-pxa/generic.c
View file @ f69eda00
......@@ -338,6 +338,27 @@ static struct platform_device i2c_device = {
.num_resources = ARRAY_SIZE(i2c_resources),
};
#ifdef CONFIG_PXA27x
static struct resource i2c_power_resources[] = {
{
.start = 0x40f00180,
.end = 0x40f001a3,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PWRI2C,
.end = IRQ_PWRI2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c_power_device = {
.name = "pxa2xx-i2c",
.id = 1,
.resource = i2c_power_resources,
.num_resources = ARRAY_SIZE(i2c_resources),
};
#endif
void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
i2c_device.dev.platform_data = info;
......@@ -392,6 +413,9 @@ static struct platform_device *devices[] __initdata = {
&stuart_device,
&pxaficp_device,
&i2c_device,
#ifdef CONFIG_PXA27x
&i2c_power_device,
#endif
&i2s_device,
&pxartc_device,
};
......
arch/arm/mach-realview/Kconfig
View file @ f69eda00
......@@ -10,10 +10,21 @@ config MACH_REALVIEW_EB
config REALVIEW_MPCORE
bool "Support MPcore tile"
depends on MACH_REALVIEW_EB
select CACHE_L2X0
help
Enable support for the MPCore tile on the Realview platform.
Since there are device address and interrupt differences, a
kernel built with this option enabled is not compatible with
other tiles.
config REALVIEW_MPCORE_REVB
bool "Support MPcore RevB tile"
depends on REALVIEW_MPCORE
default n
help
Enable support for the MPCore RevB tile on the Realview platform.
Since there are device address differences, a
kernel built with this option enabled is not compatible with
other tiles.
endmenu
arch/arm/mach-realview/platsmp.c
View file @ f69eda00
......@@ -52,13 +52,14 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
smp_wmb();
/*
* Synchronise with the boot thread.
......@@ -102,6 +103,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
break;
......
arch/arm/mach-realview/realview_eb.c
View file @ f69eda00
......@@ -31,6 +31,7 @@
#include <asm/mach-types.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/icst307.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -57,7 +58,26 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
.pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
},
#ifdef CONFIG_REALVIEW_MPCORE
{
.virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE),
.pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE),
.pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE),
.pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE),
.length = SZ_8K,
.type = MT_DEVICE,
},
#endif
{
.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
.length = SZ_4K,
......@@ -138,19 +158,29 @@ static void __init gic_init_irq(void)
#ifdef CONFIG_REALVIEW_MPCORE
unsigned int pldctrl;
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
pldctrl |= 0x00800000; /* New irq mode */
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
#ifdef CONFIG_REALVIEW_MPCORE
gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64);
gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE));
gic_cascade_irq(1, IRQ_EB_IRQ1);
#endif
}
static void __init realview_eb_init(void)
{
int i;
#ifdef CONFIG_REALVIEW_MPCORE
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff);
#endif
clk_register(&realview_clcd_clk);
platform_device_register(&realview_flash_device);
......
arch/arm/mach-s3c2400/Kconfig 0 → 100644
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# arch/arm/mach-s3c2400/Kconfig
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
menu "S3C2400 Machines"
endmenu
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# arch/arm/mach-s3c2400/Makefile
#
# Copyright 2007 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_CPU_S3C2400) += gpio.o
# Machine support
arch/arm/mach-s3c2410/s3c2400-gpio.c → arch/arm/mach-s3c2400/gpio.c
View file @ f69eda00
/* linux/arch/arm/mach-s3c2410/s3c2400-gpio.c
/* linux/arch/arm/mach-s3c2400/gpio.c
*
* Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
*
......
arch/arm/mach-s3c2410/Kconfig
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arch/arm/mach-s3c2410/bast-irq.c
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......@@ -39,7 +39,7 @@
#include <asm/arch/bast-map.h>
#include <asm/arch/bast-irq.h>
#include "irq.h"
#include <asm/plat-s3c24xx/irq.h>
#if 0
#include <asm/debug-ll.h>
......
arch/arm/mach-s3c2410/bast.h
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/* linux/arch/arm/mach-s3c2410/bast.h
extern void bast_init_irq(void);
arch/arm/mach-s3c2410/clock.c
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arch/arm/mach-s3c2410/irq.c
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arch/arm/mach-s3c2410/mach-amlm5900.c
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arch/arm/mach-s3c2410/mach-bast.c
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......@@ -50,9 +50,9 @@
#include <linux/serial_8250.h>
#include "clock.h"
#include "devs.h"
#include "cpu.h"
#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
#include "usb-simtec.h"
#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
......
arch/arm/mach-s3c2410/mach-h1940.c
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arch/arm/mach-s3c2410/mach-otom.c
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......@@ -32,10 +32,10 @@
#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include "s3c2410.h"
#include "clock.h"
#include "devs.h"
#include "cpu.h"
#include <asm/plat-s3c24xx/s3c2410.h>
#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
static struct map_desc otom11_iodesc[] __initdata = {
/* Device area */
......
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