- 27 Jun, 2024 39 commits
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Rafał Miłecki authored
MT7988 has on-SoC controller that can control up to 8 PWM interfaces. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240604064302.487-1-zajec5@gmail.comSigned-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Rafał Miłecki authored
OpenWrt One is the first ever OpenWrt product. It's based on MT7981B (AKA Filogic 820) and has 1 GiB or DDR4 RAM. The rest of peripherals remains to be added later. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
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Rafał Miłecki authored
OpenWrt One is the first ever OpenWrt product. It's based on MT7981B and has entered an early production stage. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Rafał Miłecki authored
OpenWrt project (with the help of MediaTek and Banana Pi) has produced its very first own hardware. It needs its own prefix. Signed-off-by:
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Frank Wunderlich authored
Add devicetree for Bananapi R3 Mini SBC. Key features: - MediaTek MT7986A(Filogic 830) Quad core ARM Cortex A53 - Wifi 6 2.4G/5G (MT7976C) - 2G DDR RAM - 8G eMMC flash - 128MB Nand flash - 2x 2.5GbE network port - 1x M.2 Key B USB interface - 1x M.2 KEY M PCIe interface - 1x USB2.0 interface source: https://wiki.banana-pi.org/Banana_Pi_BPI-R3_MiniCo-developed-by:
Eric Woudstra <ericwouds@gmail.com> Signed-off-by:
Tianling Shen <cnsztl@gmail.com> Signed-off-by:
Frank Wunderlich <frank-w@public-files.de> Reviewed-by:
Daniel Golle <daniel@makrotopia.org> Reviewed-by:
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Frank Wunderlich authored
Add MT7988A based BananaPi R3 Mini. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Reviewed-by:
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Rafał Miłecki authored
MT7981 (Filogic 820) uses efuse for storing calibration data. Signed-off-by:
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Rafał Miłecki authored
Align "clocks" array entries to start at the same column. Fixes: cf294275 ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T") Signed-off-by:
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Geert Uytterhoeven authored
Overlay syntactic sugar for generating target-path fragments is supported by the version of dtc supplied with the kernel since commit 50aafd60 ("scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc"). Hence convert the Bananapi R3 overlay devicetree source files to sugar syntax, improving readability. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2fd900a30b5a0f7de4ea68f60bac250794b8cdb4.1716984213.git.geert+renesas@glider.beSigned-off-by:
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Pin-yen Lin authored
Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it complies with the panel's unprepare delay (the time to power down completely) of the power sequence. Explicit configuration on the regulator node is required because mt8192-asurada uses the same power supply for the panel and the anx7625 DP bridge. For example, the power sequence could be violated in this sequence: 1. Bridge on: panel goes off, but regulator doesn't turn off (refcount=1). 2. Bridge off: regulator turns off (refcount=0). 3. Bridge resume -> regulator turns on but the bridge driver doesn't check the delay. Or in this sequence: 1. Bridge on: panel goes off. The regulator doesn't turn off (refcount=1), but the .unprepared_time in panel_edp is still updated. 2. Bridge off, regulator goes off (refcount=0). 3. Panel on, but the panel driver uses the wrong .unprepared_time to check the unprepare delay. Fixes: f9f00b1f ("arm64: dts: mediatek: asurada: Add display regulators") Signed-off-by:
Pin-yen Lin <treapking@chromium.org> Reviewed-by:
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Michael Walle authored
Add basic support for the Kontron 3.5" single board computer featuring a Mediatek i1200 SoC (MT8395/MT8195). Signed-off-by:
Michael Walle <mwalle@kernel.org> Reviewed-by:
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Michael Walle authored
Add the compatible string for the Kontron 3.5"-SBC-i1200 single board computer. Signed-off-by:
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Macpaul Lin authored
This patch fixes an issue where xhci1 was not functioning properly because the state and PHY settings were incorrect. The introduction of the 'force-mode' property in the phy-mtk-tphy driver allows for the correct initialization of xhci1 by updating the Device Tree settings accordingly. The necessary fixup which added support for the 'force-mode' switch in the phy-mtk-tphy driver. commit 9b273030 ("phy: mediatek: tphy: add support force phy mode switch") Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com Prior to this fix, the system would exhibit the following probe failure messages for xhci1: xhci-mtk 11290000.usb: supply vbus not found, using dummy regulator xhci-mtk 11290000.usb: uwk - reg:0x400, version:104 xhci-mtk 11290000.usb: xHCI Host Controller xhci-mtk 11290000.usb: new USB bus registered, assigned bus number 5 xhci-mtk 11290000.usb: clocks are not stable (0x1003d0f) xhci-mtk 11290000.usb: can't setup: -110 xhci-mtk 11290000.usb: USB bus 5 deregistered xhci-mtk: probe of 11290000.usb failed with error -110 With the application of this dts fixup, the aforementioned initialization errors are resolved and xhci1 is working. Signed-off-by:
Macpaul Lin <macpaul.lin@mediatek.com> Link: https://lore.kernel.org/r/20240216095751.4937-1-macpaul.lin@mediatek.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Add a devicetree for the Cherry Dojo (HP Chromebook x360 13b-ca0002sa) convertible type machine. Differences with the already supported Tomato machines include: - Different speaker amplifiers (Dual MAX98380, one per channel) - I2C Touchscreen is on a different address (though still a HID device) - Has NVMe storage on the PCIe0 controller - Slightly different keyboard top row keymap Link: https://lore.kernel.org/r/20240314103500.93158-3-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Add the MT8195 Cherry platform's Dojo machine, a convertible design commercially known as the HP Chromebook x360 (13b-ca0002sa). Acked-by:
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AngeloGioacchino Del Regno authored
The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-19-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-18-angelogioacchino.delregno@collabora.comSigned-off-by:
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Chen-Yu Tsai authored
The "mediatek,drive-strength-adv" pin config property has been deprecated in favor of the generic "drive-strength-microamp" property. Drop or convert all instances. A value of 0 disables the advanced mode, which is the hardware default. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20240412075516.1199846-1-wenst@chromium.orgSigned-off-by:
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Chen-Yu Tsai authored
The "output-enable" property is set on uart1's RTS pin. This is bogus because the hardware does not actually have a controllable output buffer. Secondly, the implementation incorrectly treats this property as a request to switch the pin to GPIO output. This does not fit the intended semantic of "output-enable" and it does not have any affect either because the pin is muxed to the UART function, not the GPIO function. Drop the property. Fixes: cd894e27 ("arm64: dts: mt8183: Add krane-sku176 board") Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the necessary power supplies to safely enable CPU and GPU frequency scaling. Link: https://lore.kernel.org/r/20240409114211.310462-6-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Enable the PCIe0 PHY to be able to set calibrations read from eFuses, improving the stability and performance of the PCIe link. While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing the USB ports to finally switch to gadget mode if needed, and configure the VBUS/ID pins of both USB ports for the same. Link: https://lore.kernel.org/r/20240409114211.310462-5-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
The paris pinctrl driver supports specifying the RSEL drive strength in microamperes as well as internal bits definitions: choose to specify those in uA to avoid using hardware specific values in device trees. Link: https://lore.kernel.org/r/20240409114211.310462-4-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
GPIOs 25 and 26 do not support pull-up/pull-down when those are muxed as I2C6's SDA6/SCL6 lines: set those to bias-disable to avoid warning messages from the pinctrl driver. Fixes: 96564b1e ("arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board") Link: https://lore.kernel.org/r/20240409114211.310462-3-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
The thermal zones in MT8183 had cryptic names and all of them, apart from the cpu-thermal zone, had no thermal trips, hence those were not probed at all. Refactor the tzts1..5 and tztsABB thermal zones to add the correct thermal trips and give them a meaningful name, corresponding to the actually monitored thermal zone. While at it, also rename the thermal sensor node to "thermal-sensor". Now the thermal zones are probing and their temperatures can be read. Fixes: b325ce39 ("arm64: dts: mt8183: add thermal zone node") Link: https://lore.kernel.org/r/20240410083002.1357857-4-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: c7a72805 ("arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-3-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: 1e5b6725 ("arm64: dts: mediatek: mt8195: Add AP domain thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-2-angelogioacchino.delregno@collabora.comSigned-off-by:
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Macpaul Lin authored
Add basic device-tree for the Genio 700 EVK board. The Genio 700 EVK is based on MediaTek MT8390 SoC. MT8390 hardware register maps are identical to MT8188. The Genio 700 EVK has following features: - MT8390 SoC - MT6365 PMIC - MT6319 Buck IC - 12V DC Jack - 2x4GB LPDDR4X - 64GB eMMC 5.1 - 64Mb SPI NOR - M.2 Key A-E slot with PCIe Gen2 and USB 2.0 - 2x DSI LCM ports - 2x touch sensor ports - 2x MIPI-CSI, as camera daughter board slots - USB 2 micro USB connector - USB 3 with 1 to 2 hub: - M.2 Key B slot - Type-C connector, with DisplayPort over Type-C - HDMI 2.0 TX port with Type A HDMI connector - eDP port - Gigabit Ethernet with RJ45 connector - SD card slot - Earphone Jack - Analog Microphone - 2x Digital Microphone - 3x UART with serial-to-usb converters and micro USB connectors Signed-off-by:
Chris-QJ Chen <chris-qj.chen@mediatek.com> Signed-off-by:
Pablo Sun <pablo.sun@mediatek.com> Signed-off-by:
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Macpaul Lin authored
1. Add compatible for MT8390. 2. Add bindings for the MediaTek mt8390-evk board, also known as the "Genio 700-EVK". The MT8390 and MT8188 belong to the same SoC family, with only minor differences in their physical characteristics. They utilize unique efuse values for differentiation. The booting process and configurations are managed by boot loaders, firmware, and TF-A. Consequently, the part numbers and procurement channels vary. Signed-off-by:
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Rafał Miłecki authored
MT7981 (Filogic 820) is a low cost version of MT7986 (Filogic 830) with the same watchdog controller. It also comes with on-SoC 802.11ax wireless. Signed-off-by:
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Rafał Miłecki authored
Add bindings of two on-SoC XHCI controllers. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add compatible for MT8188 VPP mutex, having different bits to activate mute for various hardware IPs. Acked-by:
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AngeloGioacchino Del Regno authored
None of the MT8192 Chromebooks had their chassis-type specified: add the right definition for each. Reviewed-by:
David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20240313141538.1438167-3-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Define the chassis type on the remaining MT8183 Chromebooks. Link: https://lore.kernel.org/r/20240313141538.1438167-2-angelogioacchino.delregno@collabora.comSigned-off-by:
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Daniel Danzberger authored
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles. Reviewed-by:
Daniel Danzberger <dd@embedd.com> Co-developed-by:
Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by:
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Lorenzo Bianconi authored
Introduce Airoha EN7581 entry in Airoha dts binding. Acked-by:
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Rafał Miłecki authored
Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. It has 256 MiB of RAM, some LEDs & buttons and (not described yet) 4 Ethernet ports. Signed-off-by:
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Rafał Miłecki authored
MT7981 contains on-SoC PIN controller that is also a GPIO provider. Signed-off-by:
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Rafał Miłecki authored
Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. Signed-off-by:
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Rafał Miłecki authored
Cudy is a Chinese company providing networking products. Signed-off-by:
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- 26 May, 2024 1 commit
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Linus Torvalds authored
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