- 04 Sep, 2013 12 commits
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Gabor Juhos authored
The Ralink RT3883 SoCs have a built-in PCI Host Controller device. The patch adds a platform driver and device tree binding documentation for that. The patch also enables the HW_HAS_PCI config option. This is required in order to be able to enable the PCI support. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Acked-by:
John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5758/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Jim Quinlan authored
The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A stale misprediction address in either the JTB or the CRS may trigger a prefetch inside a region that is currently being used by a DMA engine, which is not IO-coherent. This prefetch will fetch a line into the scache, and that line will soon become stale (ie wrong) during/after the DMA. Mayhem ensues. In dma-default.c, the r10000 is handled as a special case in the same way that we want to handle Zephyr. So we generalize the exception cases into a function, and include Zephyr as one of the processors that needs this special care. Signed-off-by:
Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5776/Signed-off-by:
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John Crispin authored
Add a helper for reseting different devices on the SoC. Signed-off-by:
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Gabor Juhos authored
Override certain CPU features to help GCC to optimize the generated code. Saves about 150KB in the vmlinux image with a generic configuration. text data bss dec hex filename 3824158 134820 234192 41931702 3ffb92 vmlinux.no-override 3664054 138804 234192 4037050 3d99ba vmlinux.override Signed-off-by: -
John Crispin authored
Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by:
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John Crispin authored
The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by:
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Gabor Juhos authored
The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by:
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John Crispin authored
Select the the EHCI and OHCI symbols. Signed-off-by:
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John Crispin authored
Make the code print which of SDRAM, DDR1 or DDR2 was detected. Signed-off-by:
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John Crispin authored
Make plat_time_init() call clocksource_of_init() allowing the systick cevt to load. Signed-off-by:
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John Crispin authored
Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent of the SoC master clock. If we want to automatic frequency scaling to work we need to use the systick timer as the clock source. Signed-off-by:
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John Crispin authored
Adds a driver for the periodic timer found on Ralink SoC. Signed-off-by:
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- 03 Sep, 2013 26 commits
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Ganesan Ramalingam authored
Add a default built-in device tree for XLP2xx SoC. The new file xlp_fvp.dts has updated entries for I2C and memory. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5705/Signed-off-by:
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Ganesan Ramalingam authored
Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by:
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Ganesan Ramalingam authored
XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this. Signed-off-by:
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Jayachandran C authored
On XLP2xx, wakeup code does not need to enable clock on the core. Update xlp/wakeup.c to handle this. Signed-off-by:
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Ganesan Ramalingam authored
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by:
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Jayachandran C authored
The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII Signed-off-by:
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Jayachandran C authored
XLP2XX is first in the series of 28nm XLPII processors. The changes are to: * Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c. * Add a cpu_is_xlpii() function to check for XLPII processors. * Update xlp_mmu_init() to use config4 to enable extended TLB. Signed-off-by:
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Jayachandran C authored
The flash chipselects can span 32MB, fix this in the built-in device tree. Signed-off-by:
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Jayachandran C authored
Do not pass a memory section in the built-in DTB, and let the boot code use the values from the DRAM BARs. Signed-off-by:
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Jayachandran C authored
Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees. Signed-off-by:
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Gabor Juhos authored
The ath79 code uses static clock devices and provides its own clk_{get,put} implementations. Change the code to use dynamically allocated clock devices and register the clocks within the clkdev framework. Additionally, remove the local clk_{get,put} implementation. The clkdev framework has a common implementation of those. Also move the call of ath79_clock_init() from plat_mem_init() to plat_time_init(). Otherwise it would not be possible to use memory allocation functions from ath79clock_init() becasuse the memory subsystem is not yet initialized when plat_mem_init() runs. Signed-off-by: -
Gabor Juhos authored
Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by:
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Gabor Juhos authored
Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: -
Gabor Juhos authored
The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by:
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Gabor Juhos authored
The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by:
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Felix Fietkau authored
The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: stable@vger.kernel.org Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Gabor Juhos authored
The ath79 code supports various SoCs which are using either a 24Kc or a 74Kc core. The 74Kc core has DSP support, so don't hardwire the values to zero. Commit 00dc5ce2 (MIPS: ath79: don't hardcode the unavailability of the DSP ASE) has fixed this already, but that change got reverted by 47503256 (MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.) Reported-by:
Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by:
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John Crispin authored
This add a default config for the Lantiq XWAY SoC. Signed-off-by:
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Thomas Langer authored
The clocks of the serial ports were not setup properly. Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Acked-by:
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Thomas Langer authored
Add cpu-feature-override.h for the GPON SoC Signed-off-by:
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John Crispin authored
This driver so far only reads the core voltage. Signed-off-by:
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Ralf Baechle authored
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James Hogan authored
Add a uImage build target for MIPS, which builds uImage.gz (a U-Boot image of vmlinux.bin.gz), and then symlinks it to uImage. This allows for the use of other compression algorithms in future, and is how a few other architectures do it. It's enabled conditionally on load-y >= 0xffffffff80000000 which hopefully allows 64bit kernels to also work as long as the load and entry address can be represented by the 32bit addresses in the U-Boot image format. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5795/Signed-off-by:
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James Hogan authored
The vmlinux load address and entry address is calculated in multiple places: - arch/mips/Makefile defines load-y from CONFIG_PHYSICAL_START (or defined by the platform) and passes it to arch/mips/boot/compressed/Makefile. - arch/mips/boot/compressed/Makefile calculates kernel entry using nm. - arch/mips/lasat/image/Makefile calculates both load and entry address using nm. Lets combine these in the main Makefile and then pass them as Make parameters to each of the three boot image Makefiles (in boot/, boot/compressed, lasat/image/). The boot/ Makefile doesn't currently use them, but will soon need to for U-Boot image targets. The existing load-y definition is used in preference to calculating the load address using nm. Signed-off-by:
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James Hogan authored
Split out the arch/mips/boot/ and arch/mips/boot/compressed/ targets into boot-y and bootz-y variables. This makes it slightly cleaner to add new targets. Signed-off-by:
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James Hogan authored
Add symlink to include/dt-bindings from arch/mips/boot/dts/include/ to match the ones in ARM and Meta architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299aa (kbuild: create an "include chroot" for DT bindings) merged in v3.10-rc1 for details. MIPS structures it's dts files a little differently to other architectures, having a separate dts directory for each SoC/platform, but most of the definitions in the dt-bindings/ directory are common so for now lets just have a single "include chroot" for all MIPS platforms. Signed-off-by:
Steven. J. Hill <steven.hill@imgtec.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kbuild@vger.kernel.org Acked-by:
Stephen Warren <swarren@nvidia.com> Patchwork: http://patchwork.linux-mips.org/patch/5745/Signed-off-by:
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- 26 Aug, 2013 2 commits
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David Daney authored
Some toolchains (including Cavium OCTEON SDK) are emitting .eh_frame sections by default. Discard them as they are useless in the kernel. Signed-off-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5684/Signed-off-by:
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David Daney authored
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip GPIO pins, this driver handles them all. Configuring the pins as interrupt sources is handled elsewhere (OCTEON's irq handling code). Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5633/Signed-off-by:
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