- 08 Dec, 2023 1 commit
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Neil Armstrong authored
Document the DisplayPort controller found in the Qualcomm SM8650 SoC, the Controller base addresses and layout differ and thus cannot use the SM8350 compatible as fallback. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571131/ Link: https://lore.kernel.org/r/20231207-topic-sm8650-upstream-dp-v1-1-b762c06965bb@linaro.orgSigned-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- 06 Dec, 2023 1 commit
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Dmitry Baryshkov authored
On sc7280 there are two clk bits for WB2: vbif_cli and clk_ctrl. While programming the VBIF params of WB, the driver should be toggling the former bit, while the sc7180_mdp, sc7280_mdp and sm8250_mdp structs list the latter one. Correct that to ensure proper programming sequence for WB2 on these platforms. Fixes: 255f0561 ("drm/msm/dpu: sc7180: add missing WB2 clock control") Fixes: 3ce16638 ("drm/msm/dpu: add writeback support for sc7280") Fixes: 53324b99 ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog") Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by:
Paloma Arellano <quic_parellan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570185/ Link: https://lore.kernel.org/r/20231203002437.1291595-1-dmitry.baryshkov@linaro.org
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- 05 Dec, 2023 38 commits
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Dmitry Baryshkov authored
It is incorrect to use devm-managed memory allocations for DRM data structures exposed to userspace. They should use drmm_ allocations. Change struct dpu_encoder allocation to use drmm_encoder_alloc(). This removes the need to perform any actions on encoder destruction. Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by:
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Dmitry Baryshkov authored
Drop the dpu_encoder_phys_ops' destroy() callback. No phys backend implements it anymore, so it is useless. Reviewed-by:
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Dmitry Baryshkov authored
Change struct allocation of encoder's phys backend data to use drmm_kzalloc(). This removes the need to perform any actions on encoder destruction. Reviewed-by:
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Dmitry Baryshkov authored
Change struct dpu_crtc allocation to use drmm_crtc_alloc_with_planes(). This removes the need to perform any actions on CRTC destruction. Reviewed-by:
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Dmitry Baryshkov authored
Change struct dpu_plane allocation to use drmm_universal_plane_alloc(). This removes the need to perform any actions on plane destruction. Reviewed-by:
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Dmitry Baryshkov authored
There is little point in disabling QoS on plane destruction: it happens during DPU device destruction process, after which there will be no running planes. Reviewed-by:
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Dmitry Baryshkov authored
The field dpu_plane::lock was never used for protecting any kind of data. Drop it now. Reviewed-by:
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Dmitry Baryshkov authored
Use devm_kzalloc to create HW block structure. This allows us to remove corresponding kfree and drop all dpu_hw_*_destroy() functions as well as dpu_rm_destroy(), which becomes empty afterwards. Reviewed-by:
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Dmitry Baryshkov authored
Use devm_kzalloc to create MDP TOP structure. This allows us to remove corresponding kfree and drop dpu_hw_mdp_destroy() function. Reviewed-by:
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Dmitry Baryshkov authored
Use devm_kzalloc to create VBIF data structure. This allows us to remove corresponding kfree and drop dpu_hw_vbif_destroy() function. Reviewed-by:
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Dmitry Baryshkov authored
Use devm_kzalloc to create interrupts data structure. This allows us to remove corresponding kfree and drop dpu_hw_intr_destroy() function. Reviewed-by:
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Dmitry Baryshkov authored
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If the value is NULL, then the function will return 0 instead of a proper return code. Replace IS_ERR_OR_NULL() with IS_ERR() in the dpu_hw_intr_init() error check. Reviewed-by:
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Dmitry Baryshkov authored
It was noticed that dpu_kms_hw_init()'s error path contains several labels which point to the same code path. Replace all of them with a single label. Suggested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
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Dmitry Baryshkov authored
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects, from none to otherwise inexplicable DSI timeouts. Provide a way for MDSS driver to vote on this bus. A note regarding vote values. Newer platforms have corresponding bandwidth values in the vendor DT files. For the older platforms there was a static vote in the mdss_mdp and rotator drivers. I choose to be conservative here and choose this value as a default. Co-developed-by:
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Dmitry Baryshkov authored
There are just two places where we set the bandwidth: in the resume and in the suspend paths. Drop the wrapping function msm_mdss_icc_request_bw() and call icc_set_bw() directly. Signed-off-by:
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Konrad Dybcio authored
The DPU1 driver needs to handle all MDPn<->DDR paths, as well as CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are calculated, but the latter one has static predefines spanning all SoCs. In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename the path-related struct members to include "mdp_". Signed-off-by:
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Dmitry Baryshkov authored
Stop using hand-written reset function for ICC release, use devm_of_icc_get() instead. Signed-off-by:
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Neil Armstrong authored
Add DSI Controller version 2.8.0 support for the SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add DSI PHY support for the SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add Mobile Display Subsystem (MDSS) support for the SM8650 platform. Reviewed-by:
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Neil Armstrong authored
Add DPU version 10.0 support for the SM8650 platform. Signed-off-by:
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Neil Armstrong authored
Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform. Reviewed-by:
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Neil Armstrong authored
Document the DPU Display Controller on the SM8650 Platform. Reviewed-by:
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Neil Armstrong authored
Document the DSI Controller on the SM8650 Platform. Reviewed-by:
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Neil Armstrong authored
Document the DSI PHY on the SM8650 Platform. Reviewed-by:
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Richard Acayan authored
The Snapdragon 670 uses similar clocks (with one frequency added) to the Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU with configuration from the Pixel 3a downstream kernel. Since revision 4.0 is SDM845, reuse some configuration from its catalog entry. Link: https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsiSigned-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
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Richard Acayan authored
Add support for the MDSS block on the SDM670 platform. Reviewed-by:
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Richard Acayan authored
Add documentation for the SDM670 display subsystem, adapted from the SDM845 and SM6125 documentation. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Richard Acayan authored
The SDM670 display controller has the same requirements as the SDM845 display controller, despite having distinct properties as described in the catalog. Add the compatible for SDM670 to the SDM845 controller. Acked-by:
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Richard Acayan authored
The SDM670 has DSI ports. Add the compatible for the controller. Acked-by:
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Dmitry Baryshkov authored
After folding QSEED3LITE and QSEED4 feature bits into QSEED3_COMPATIBLE several VIG feature masks became equal. Drop these duplicates. Signed-off-by:
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Dmitry Baryshkov authored
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4 are all related to different versions of the same HW scaling block. Corresponding driver parts use scaler_blk.version to identify the correct way to program the hardware. In order to simplify the driver codepath, merge these three feature bits into QSEED3_COMPATIBLE bin. Signed-off-by:
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Dmitry Baryshkov authored
In order to check whether the SSPP block has scaler and CSC subblocks the funcion dpu_plane_atomic_check_pipe() uses macros which enumerate all possible scaler and CSC features. Replace those checks with the scaler and CSC subblock length checks in order to be able to drop those two macros. Suggested-by:
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Dmitry Baryshkov authored
As the subblock info is now mostly gone, inline and drop the macro DPU_HW_SUBBLK_INFO. Reviewed-by:
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Dmitry Baryshkov authored
As we have dropped the variadic parts of SSPP sub-blocks declarations, deduplicate them now, reducing memory cruft. Reviewed-by:
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Dmitry Baryshkov authored
In preparation to deduplicating SSPP subblocks, drop the (unused) `smart_dma_priority' field from struct dpu_sspp_sub_blks. If it is needed later (e.g. for SmartDMA v1), it should be added to the SSPP declarations themselves. Reviewed-by:
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Dmitry Baryshkov authored
The field `id' is not used for subblocks. The handling code usually knows, which sub-block it is now looking at. Drop the field completely. Reviewed-by:
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Marijn Suijten authored
The SSPP scaler subblk is responsible for reporting its version (via the .id field, feature bits on the parent SSPP block, and since recently also from reading a register to supersede a read-but-unset version field in the catalog), leaving this global qseed_type field logically unused. Remove this dead code to lighten the catalog and bringup-overhead. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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