- 06 Nov, 2023 8 commits
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Tvrtko Ursulin authored
Iterators operate on struct intel_gt so lets move it to intel_gt.h in order to make i915_drv.h less of a dumping ground for stuff. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by:
Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231102093248.362659-2-tvrtko.ursulin@linux.intel.com
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Tvrtko Ursulin authored
Unused macro after 99919be7 ("drm/i915/gem: Zap the i915_gem_object_blt code") removed some code. Signed-off-by:
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Ville Syrjälä authored
The code to determine the pre-ICL DSI port control register is repeated several times. Consolidate. vlv_dsi_clear_device_ready() is left with the open-coded version due to the weirdness with port A vs. C on VLV/CHV. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231101114212.9345-6-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
GLK has its own glk_dsi_clear_device_ready() so remove the dead GLK checks from vlv_dsi_clear_device_ready(). Sadly BXT still uses vlv_dsi_clear_device_ready() so the code still looks like a mess due to the difference in VLV/CHV vs. BXT port A/C shenanigans. Signed-off-by:
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Ville Syrjälä authored
Stop repeating the same logic to determine the correct config space register for MCHBAR. Signed-off-by:
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Ville Syrjälä authored
'reg' is a very non-descriptive name. Just get rid of the silly local variable and spell out the full register name always. Signed-off-by:
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Ville Syrjälä authored
We have the same code to determine the CHICKEN_TRANS register offset sprinkled in a dozen places. Hoover it up into a small helper. TODO: find a better home for this Signed-off-by:
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Jouni Högander authored
We are preparing for Xe. Xe_bo doesn't have obj->base. Due to this use intel_bo_to_drm_bo instead in intel_prepare_plane_fb. Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
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- 03 Nov, 2023 1 commit
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Ville Syrjälä authored
On GLK CDCLK frequency needs to be at least 2*96 MHz when accessing the audio hardware. Currently we bump the CDCLK frequency up temporarily (if not high enough already) whenever audio hardware is being accessed, and drop it back down afterwards. With a single active pipe this works just fine as we can switch between all the valid CDCLK frequencies by changing the cd2x divider, which doesn't require a full modeset. However with multiple active pipes the cd2x divider trick no longer works, and thus we end up blinking all displays off and back on. To avoid this let's just bump the CDCLK frequency to >=2*96MHz whenever multiple pipes are active. The downside is slightly higher power consumption, but that seems like an acceptable tradeoff. With a single active pipe we can stick to the current more optiomal (from power comsumption POV) behaviour. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9599Signed-off-by:
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- 02 Nov, 2023 1 commit
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Jouni Högander authored
We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence implementation. Lets drop i915_sw_fence usage from display code and use dma_fence interfaces directly. For this purpose stack dma fences from related objects into new plane state. Drm_gem_plane_helper_prepare_fb can be used for fences in new fb. Separate local implementation is used for Stacking fences from old fb into new plane state. Then wait for these stacked fences during atomic commit. There is no be need for separate GPU reset handling in intel_atomic_commit_fence_wait as the fences are signaled when GPU hang is detected and GPU is being reset. v4: - Drop to_new_plane_state suffix from add_dma_resv_fences - Use dma_resv_usage_rw(false) (DMA_RESV_USAGE_WRITE) v3: - Rename add_fences and it's parameters - Remove signaled check - Remove waiting old_plane_state fences v2: - Add fences from old fb into new_plane_state->uapi.fence rather than into old_plane_state->uapi.fence Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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- 01 Nov, 2023 4 commits
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Ville Syrjälä authored
Since we're asked to disable FECSTALL_DIS_DPTSTREAM_DPTTG when the transcoder is disabled it seems prudent to also clear it when enabliing the transcoder w/o FEC, just in case someone else left it enabled by mistake. Signed-off-by:
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Ville Syrjälä authored
Follow the bspec sequence more closely and clear ACT sent just before triggering the allocation. Can't see why we'd want to deviate from the spec sequence here. Signed-off-by:
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Ville Syrjälä authored
Bspec tells us that we should disable the transcoder before deleting the payload. Looks like this has been reversed since MST support was added. I suppose this shouldn't matter in practice since the downstream device shouldn't really do anything with the new payload until we send the ACT. But I see no compelling reason to deviate from the bspec sequence regardless. Signed-off-by:
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Ville Syrjälä authored
The DP modeset sequence asks us to disable TRANSCONF before clearing the FECSTALL_DIS_DPTSTREAM_DPTTG bit, although we are still asked to wait for the transcoder to stop only after both steps have been done. Signed-off-by:
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- 31 Oct, 2023 10 commits
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Nirmoy Das authored
Handle platforms with multiple GTs by iterate over all GTs. Add a Fixes commit so this gets propagated for MTL support. Fixes: 213c4367 ("drm/i915/mtl: Remove the 'force_probe' requirement for Meteor Lake") Suggested-by:
John Harrison <john.c.harrison@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231025102826.16955-1-nirmoy.das@intel.com
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Suraj Kandpal authored
When we dock a monitor we end up with a enable and disable connector cycle but if hdcp content is running we get the userspace in enabled state and driver maintaining a undesired state which causes the content to stop playing and we only enable hdcp if the userspace state in desired. This patch fixes that. --v2 -Move code to intel_hdcp [Jani] Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Suraj Kandpal authored
Let's convert intel_hdcp_enable to a blanket function which just has some conditions which needs to be checked before connectors enable hdcp. This cleans up code and avoids code duplication. --v3 -Keep function name as intel_hdcp_enable() [Jani] Signed-off-by:
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Suraj Kandpal authored
Rename hdcp 1.4 enablement function from _intel_hdcp_enable to intel_hdcp1_enable to better represent what version of hdcp is being enabled Signed-off-by:
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Ville Syrjälä authored
We are asked to reprogram PEG_BAND_GAP_DATA prior to enabling hotplug detection on the g45 HDMI/DP ports. Currently we do said reprogamming from the DP/HDMI connector initialization functions. That code should be mostly platform agnostic so clearly not the best place for this. Move the workaround to the place where we actually enable HPD detection. Signed-off-by:
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Ville Syrjälä authored
We have a bit of duplicated code around the DPLL disabling. Extract that to a new function, and for symmetry also do the same for the enable direction. Signed-off-by:
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Ville Syrjälä authored
The extra DPLL power domain is currently handled in three places: - combo_pll_enable() - combo_pll_disable() - readout_dpll_hw_state() First two of those are low level PLL funcs, but the third is a higher level thing. So the current situation is rather inconsistent. Unify this by moving the PLL enable/disable up one level. This also means the extra power domain could be trivially be used by other platforms as well. Signed-off-by:
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Ville Syrjälä authored
Just include the JSL/EHL DPLL4 extra power domain in the dpll_info struct. This way the same approach could be used by other platforms as well (should the need arise), and we don't have to sprinkle platform checks all over the place. Note that I'm perhaps slightly abusing things here as power_domain==0 (which is actually POWER_DOMAIN_DISPLAY_CORE) now indicates that no extra power domain is needed. I suppose using POWER_DOMAIN_INVALID would be more correct, but then we'd have to sprinkle that to all the other DPLLs. Signed-off-by:
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Ville Syrjälä authored
Use named initializers when populating the DPLL info. This is just more convenient and less error prone as we no longer have to keep the initializers in a specific order. Signed-off-by:
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Ville Syrjälä authored
Apparently some BDW machines (eg. HP Pavilion 15-ab) shipped with a VBT inherited from some earlier HSW model. On HSW the HDMI level shift value could go up to 11, whereas on BDW the maximum value is 9. The DDI code does clamp the bogus value, but it does so with a WARN which we don't really want. To avoid that let's just sanitize the bogus VBT HDMI level shift value ahead of time for all BDW machines. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9461Signed-off-by:
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- 30 Oct, 2023 3 commits
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Jani Nikula authored
Keep the display build lists together. v2: Rebase Reviewed-by:
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Jani Nikula authored
Unify the line continuations and indents, and sort the build lists. Reviewed-by:
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Chaitanya Kumar Borah authored
eDP specification supports HBR3 link rate since v1.4a. Moreover, C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. Cc: <stable@vger.kernel.org> BSpec: 70073 74224 Signed-off-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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- 29 Oct, 2023 4 commits
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Lucas De Marchi authored
As done with the hw readout, properly abstract the C10/C20 phy details inside intel_cx0_phy.c. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231018222831.4132968-3-lucas.demarchi@intel.com
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Lucas De Marchi authored
intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking it to the rest of the driver. Start abstracting this by exporting a single PLL hw readout that handles the differences between C20 and C10 internally to that compilation unit. Signed-off-by:
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Lucas De Marchi authored
With MTL adding PICA between the port and the real phy, the path add for DG2 stopped being followed and newer platforms are simply using the older path for TC phys. LNL is no different than MTL in this aspect, so just add it to the mess. In future the phy and port designation and deciding if it's TC should better be cleaned up. To make it just a bit better, also change intel_phy_is_snps() to show this is DG2-only. Signed-off-by:
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Lucas De Marchi authored
For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() accordingly. This reverts the change in commit e388ae97 ("drm/i915/display: Eliminate IS_METEORLAKE checks") that turned that into a display engine version check. The phy <-> port connection is very SoC-specific and not related to that version. IS_LUNARLAKE() is defined to 0 in i915 as it's expected that the (upcoming) xe driver is the one defining the platform, with i915 only driving the display side. Bspec: 70818 Reviewed-by:
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- 27 Oct, 2023 1 commit
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Jani Nikula authored
Move sprite_name() where its only user is, and convert it to a function, removing the implicit dev_priv usage. Signed-off-by:
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- 26 Oct, 2023 8 commits
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Mika Kahola authored
Every know and then we receive the following error when running for example IGT test kms_flip. [drm] *ERROR* PHY G Read 0d80 failed after 3 retries. [drm] *ERROR* PHY G Write 0d81 failed after 3 retries. Since the error is sporadic in nature, the patch proposes to reset the message bus after every successful or unsuccessful read or write operation. v2: Add FIXME's to indicate the experimental nature of this workaround (Rodrigo) v3: Dropping the additional delay as moving reset to *_read_once() and *_write_once() functions seem unnecessary delay Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231016125544.719963-1-mika.kahola@intel.com
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Vinod Govindapillai authored
Display device and display runtime info is exposed as part of i915_display_capabilities debugfs entry. Remove this information from i915_ capabilities as it is now reduntant. Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
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Jouni Högander authored
Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231024124109.384973-24-jouni.hogander@intel.com
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Jouni Högander authored
Signed-off-by:
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Jouni Högander authored
v2: Change device parameter permissions to 0400 Cc: Luca Coelho <luciano.coelho@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jouni Högander authored
Also make module parameter as non writable. Signed-off-by:
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Jouni Högander authored
Signed-off-by:
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Jouni Högander authored
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