- 30 Apr, 2024 26 commits
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Sung Joon Kim authored
[why & how] The recout x offset was incorrect which led to wrong viewport calculation. For stereo side-by-side case, the slice index should be 0 for both split pipes. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
HWSS set_cursor_attributes copies the stream's cursor attributes to the hubp cursor attributes. set_cursor_position might attempt to program the cursor attributes but will program them wrong if they're not set correctly. We need to call HWSS set_cursor_attributes first to ensure hubp has the right attributes to be programmed. Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
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Harry Wentland authored
We're seeing issues when user-space tries to do an atomic update of the primary surface, as well as the cursor. These two updates are separate calls into DC and don't currently act as an atomic update. This might lead to cursor updates being locked out and cursors stuttering. In order to solve this problem we want to separate the setting and programming of cursor attributes and position. That's what we're doing in this patch. The subsequent patch will then be able to use the cursor setters in independent cursor updates, as well as in atomic commits. Reviewed-by:
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Joshua Aberback authored
This reverts commit 0a571e86. [Why] The change being reverted incorrectly assumes that a pointer type was intended, however copying to a new structure is correct. As well, there is no compiler error, it was instead an error in the testing framework being used. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Ilya Bakoulin authored
Not every ASIC implements dp_set_dsc_config. Add condition to prevent calls to unimplemented function. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During DP tunnel creation, CM preallocates BW and reduces estimated BW of other DPIA. CM release preallocation only when allocation is complete. Display mode validation logic validates timings based on bw available per host router. In multi display setup, this causes bw allocation failure when allocation greater than estimated bw. [How] Do zero alloc to make the CM to release preallocation and update estimated BW correctly for all DPIAs per host router. Reviewed-by:
PeiChen Huang <peichen.huang@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Hersen Wu authored
[Why] DSC debugfs, such as dp_dsc_clock_en_read, use aconnector->dc_link to find pipe_ctx for display. Displays connected to MST hub share the same dc_link. DSC instance is from pipe_ctx. This causes incorrect DSC instance for display connected to MST hub. [How] Add aconnector->sink check to find pipe_ctx. CC: stable@vger.kernel.org Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Hawking Zhang authored
Add initial soc24 support. v1: Add soc24 common ip block. v2: Switch to new select_se_sh/enter_safe_mode interface. v3: squash in correct ext rev id, etc. (Alex) Signed-off-by:Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] It's possible that the write hasn't fully completed by the time we send (and flush) a command to DMCUB to notify idle to request IPS2 exit. [How] Perform a readback of the volatile structure into dc_dmub_srv state. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Ethan Bitnun authored
[Description] - Block FPO if the max stretch refresh rate is low enough to cause a flicker by storing the maximum safe refresh decrease from nominal in stream. - Brought over various Freesync Luminance functions to dc. Use these new functions to block fpo if we will flicker. - Generalized increase/reduce dependent functions to reduce code clutter and allow for easier use. - Added a debug option to enable the feature. Disabled by default. Co-authored-by:
Ethan Bitnun <etbitnun@amd.com> Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Hawking Zhang authored
Add enum definitions for soc24. v2: Updates (Alex) v3: Updates (Alex) v4: Fix clash with display code (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add gc v12_0_0 register offset and shift masks header files. (Hawking) v2: Update gc v12_0_0 register offset and shift masks header files to LSD version. (Likun) v3: Update gc v12_0_0 register offset and shift masks header files to RE3 version. (Likun) v4: Updates (Alex) v5: updates (Alex) Signed-off-by: -
George Shen authored
[Why] Upon disconnecting a UHBR SST display, the disconnection and the SetTimings to disable the display can occur such that link_set_dpms_off occurs after the disconnection has already processed (link->type is dc_connection_none). Thus, the AUX related operations should be skipped when clearing the payload allocation table. Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Gabe Teeger authored
New request from KMD/VBIOS in order to support new UMA carveout model. This fixes a null dereference from accessing Ctx->dc_bios->integrated_info while it was NULL. DAL parses through the BIOS and extracts the necessary integrated_info but was missing a case for the new BIOS version 2.3. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Avoid race condition which puts LTTPR into bad state during UHBR LT. [HOW] Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Sung-huai Wang authored
[Why] TCON data is corrupted after electro static discharge test. Once the TCON data get corrupted, they will get themselves reset and send HPD_IRQ to source side. [How] Support HPD_IRQ for internal link, and restore the PSR/Replay setup. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Sung-huai Wang <danny.wang@amd.com> Tested-by:
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Sung Joon Kim authored
[why & how] Need to update the function pointers that perform the power up and down sequence to reuse the modified sequence as a requirement. Reviewed-by:
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Swapnil Patel authored
[Why & How] Currently DCN315 clk manager is missing code to enable/disable dtbclk. Because of this, "optimized_required" flag is constantly set and this prevents FreeSync from engaging for certain high bandwidth display Modes which require DTBCLK. Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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Natanel Roizenman authored
[WHY] When switching from "Extend" to "Second Display Only" we sometimes call resource_get_otg_master_for_stream on a stream for the eDP, which is disconnected. This leads to a null pointer dereference. [HOW] Added a null check in dc_resource.c/resource_log_pipe_topology_update. CC: stable@vger.kernel.org Reviewed-by:
Natanel Roizenman <natanel.roizenman@amd.com> Tested-by:
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Dennis Chan authored
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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Rodrigo Siqueira authored
Drop unnecessary semicolon that can create a problem of double semicolon in some compilers. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Rodrigo Siqueira authored
This commit add some DPCX IRQ types. Signed-off-by:
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Rodrigo Siqueira authored
In the DCN20 resource initialization, ensure that DMCUB support starts configured as true. Signed-off-by:
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Rodrigo Siqueira authored
This commit adds, updates, and removes some of the comments used in the DC code. Signed-off-by:
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Philip Yang authored
RDMA device with limited scatter-gather ability requires contiguous VRAM buffer allocation for RDMA peer direct support. Add a new KFD alloc memory flag and store as bo alloc flag AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS. When pin this bo to export for RDMA peerdirect access, this will set TTM_PL_FLAG_CONTIFUOUS flag, and ask VRAM buddy allocator to get contiguous VRAM. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Ma Jun authored
Assign value to clock to fix the warning below: "Using uninitialized value res. Field res.clock is uninitialized" Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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- 26 Apr, 2024 14 commits
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Nathan Chancellor authored
-Wframe-larger-than=2048 is a part of both CFLAGS and CFLAGS_REMOVE for dml2_core_dcn4_calcs.o, which means that it ultimately gets removed altogether for 64-bit targets, as 2048 is the default FRAME_WARN value for 64-bit platforms, resulting in no -Wframe-larger-than coverage for this file. Remove -Wframe-larger-than from CFLAGS_REMOVE_dml2_core_dcn4_calcs.o and move to $(frame_warn_flag) for CFLAGS_dml2_core_dcn4_calcs.o, as that accounts for the fact that -Wframe-larger-than may need to be larger than 2048 in certain situations, such as when the sanitizers are enabled. Fixes: 00c39110 ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
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Nathan Chancellor authored
When building with tip of tree Clang, there are some new instances of -Wframe-larger-than from the new display code (which become fatal with CONFIG_WERROR=y): drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:754:6: error: stack frame size (2488) exceeds limit (2048) in 'dml2_core_shared_mode_support' [-Werror,-Wframe-larger-than] 754 | bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params) | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:9834:6: error: stack frame size (2152) exceeds limit (2048) in 'dml2_core_shared_mode_programming' [-Werror,-Wframe-larger-than] 9834 | bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params) | ^ 2 errors generated. These warnings do not occur when CONFIG_K{A,C,M}SAN are disabled, so add $(frame_warn_flag) to dml2_core_shared.o's CFLAGS, which was added in commit 6740ec97 ("drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2") to account for this situation. Fixes: 00c39110 ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by: -
Srinivasan Shanmugam authored
This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc` function. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Fixes: 70839da6 ("drm/amd/display: Add new DCN401 sources") Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add miscellaneous changes to enable DCN401 init Signed-off-by:
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Aurabindo Pillai authored
Update macros to cover DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Update for DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Expose linear modifier definitions for use with DCN401 Signed-off-by:
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Aurabindo Pillai authored
Remove a duplicate definition of an SPL related enum transform.h Since its used in SPL, it has been moved to its own header. Signed-off-by:
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Aurabindo Pillai authored
Add initial support for DCN 4.0.1. Signed-off-by:
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Aurabindo Pillai authored
Update register headers. Signed-off-by:
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Aurabindo Pillai authored
GFX12 swizzle mode and GCC formats changed and is much simpler. Use a seperate function for the same. Changes: * Swizzle mode is now 3 bits only * DCC enablement doesn't come from tiling_flags, it is always set in modifiers * DCC max compressed block size of 128B Signed-off-by:
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Aurabindo Pillai authored
define new gfx12 uapi flags Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add GFX12 swizzle mode definitions for use with DCN401 Signed-off-by:
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Rodrigo Siqueira authored
Add some missing HDCP registers to be used in DCN35. Signed-off-by:
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