- 08 Aug, 2016 40 commits
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Rex Zhu authored
they were controled by module parameter. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Chunming Zhou authored
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Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
This is a workaround to let VCE soft reset work. RB1_BUSY bit is always set, so remove its checking now, and we will depend on RB0_BUSY currently. After we find the root cause of RB1_BUSY, we can add it back. Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
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Tom St Denis authored
Partially undo changes made by commit: drm/amd/amdgpu: don't track state in UVD clockgating To keep bypass even if CG flags are not set. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
It's handled by DPM/PP properly. Signed-off-by:
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Tom St Denis authored
CG was being enabled in reverse sense from dpm/powerplay. Also fix the default CLK_EN signal to enable all of the blocks. Signed-off-by:
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Tom St Denis authored
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Leo Liu authored
This will make clock and power gated when no block decoded, for example when paused during the playback. Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Marek Olšák authored
It's useful for debugging. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Ken Wang authored
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Ken Wang authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Flora Cui authored
V2: fix the return value for fill failure and validate bo before filling data Reviewed-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
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Flora Cui authored
so that bo could be set to some pattern Signed-off-by:
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Alex Deucher authored
This got leftover somehow when I cleaned this up. Reviewed-by:
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Eric Huang authored
Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
It's already covered by the default case, but add it for consistency. Reviewed-by:
Alexandre Demers <alexandre.f.demers@gmail.com> Reviewed-by:
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Alex Deucher authored
Looks like this got missed when we ported the code from radeon. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Enable the PG_EN bit just before the SMU would be tasked with the PG transition. Signed-off-by:
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Tom St Denis authored
There's no need to track CG state anymore. Signed-off-by:
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Tom St Denis authored
This is handled properly by both DPM and PP externally. Signed-off-by:
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Tom St Denis authored
Adds support for PM locks around access to registers that might have race conditions on PG transistions. Signed-off-by:
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